A method for fractional frequency synthesis based on asynchronous logic instructions
By monitoring the spatial level state of the parallel latch array in real time under asynchronous logic instructions and mapping it to the modulator, the problem of phase compensation lag under asynchronous logic instructions is solved, the phase continuity and frequency consistency of the frequency synthesizer are realized, and the spectral purity and locking speed are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN JINKETAI COMM EQUIP CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-06-30
Smart Images
Figure CN122316342A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a fractional frequency synthesis method based on asynchronous logic instructions, belonging to the field of baseband application processing integrated circuit technology. Background Technology
[0002] The baseband application processing integrated circuit integrates a fractional-order frequency-locked loop (PLL) circuit to generate a local oscillation signal. With the increasing demands for spectral purity in broadband communication, fractional-order frequency synthesis technology driven by pure digital logic has become a common method for clock generation. In practical applications, the baseband chip receives asynchronous logic instructions through an external interface to update the frequency control word. The physical transition edges of these asynchronous logic instructions exhibit random distribution characteristics in the time domain relative to the internal reference clock. To correct timing offsets, existing technologies use digital time converters to capture the deviation of the instruction pulse edges and combine this with a multiplier to calculate the phase compensation amount to inject into the feedback loop. Due to the pipeline delay of the clock cycle generated when digital integrated circuits process wide-word-length multiplication operations, the operating phase of the voltage-controlled oscillator has already changed by the time the compensation value is injected into the accumulator register. This arithmetic logic-based feedback path creates a time-domain misalignment between computation time and phase deviation, leading to a disruption of phase continuity.
[0003] Specifically, existing technologies suffer from the following shortcomings: 1. Pipeline lag caused by arithmetic and logic operations leads to phase compensation delays, preventing the feedback loop from synchronously correcting phase deviations at the moment of frequency command updates; 2. Asynchronous updates result in phase truncation, disrupting the coherence of the fractional frequency division sequence, generating transient spurious signals, and reducing frequency consistency. While increasing the sampling frequency or pipeline stages shortens the single calculation time, it is limited by the integrated chip's power consumption and wiring area, and cannot eliminate the periodic delay of the arithmetic processing itself. Achieving instantaneous phase stitching at the moment of asynchronous command issuance without relying on complex arithmetic operations has become a key limitation in improving the performance of fully integrated frequency synthesizers.
[0004] Therefore, how to eliminate the arithmetic processing delay when updating the frequency of asynchronous logic instructions and maintain the phase continuity of the feedback loop has become the technical problem to be solved by this invention. Summary of the Invention
[0005] To address the problems mentioned in the background section, the technical solution of this invention is as follows: A fractional frequency synthesis method based on asynchronous logic instructions includes the following steps: Step S101: Real-time monitoring of the triggering time of asynchronous logic instructions; using the parallel latch array integrated inside the baseband application processing integrated chip to capture the transient spatial level state of the multiphase voltage-controlled oscillator at the triggering time; obtaining the original quantization parameters; the original quantization parameters characterize the time deviation between the start edge of the asynchronous logic instruction and the local reference clock reference edge. Step S102: Based on the preset hard-wired topology mapping logic, the original quantization parameters are translated into discrete phase residual values. The discrete phase residual values represent the phase truncation error generated at the moment of asynchronous frequency control word update. The hard-wired topology mapping logic directly maps the parallel latch result to the accumulator register pin of the modulator through physical wiring to achieve hysteresis-free conversion of the original quantization parameters into phase compensation values. Step S103: Inject the discrete phase residual value as the initial phase bias. - The modulator's phase accumulation path is used to calculate the difference between the target frequency control word carried by the asynchronous logic instruction and the current frequency control word in real time, and to dynamically adjust the frequency control based on the absolute value range of the difference. - The modulator's operating order is adjusted, and phase stitching is achieved through a preset phase register at the frequency switching moment, thereby maintaining the phase continuity of the phase-locked loop at the moment of frequency word overwriting.
[0006] Preferably, step S101 specifically includes: step S1011, using a parallel latch array composed of multiple D flip-flops, synchronously sampling the 16 equally spaced phase tap levels of the multiphase voltage-controlled oscillator output at the start edge of the asynchronous logic instruction; step S1012, determining the physical phase distribution of the asynchronous logic instruction within the local reference clock cycle based on the physical spatial location of the level flip boundary in the parallel latch array, and obtaining spatially encoded data characterizing the time deviation as the original quantization parameter.
[0007] Preferably, step S102 specifically includes: step S1021, generating binary fractional codes based on the level-flipping boundary positions in the parallel latch array using a priority encoder with pure combinational logic; step S1022, coupling the binary fractional codes to the most significant bit pin of the internal accumulator register of the Delta-Sigma modulator using hardware metal trace topology, completing the asynchronous data translation of the original quantization parameters to eliminate pipeline delay introduced by the arithmetic logic unit.
[0008] Preferably, the operation of adjusting the operating order of the Delta-Sigma modulator in step S103 includes: step S1031, calculating the absolute value of the difference between the target frequency control word and the current frequency control word; step S1032, when the absolute value of the difference is lower than a preset threshold of 1000Hz, setting the operating order of the Delta-Sigma modulator to the 3rd or 4th order; step S1033, when the absolute value of the difference reaches or exceeds the preset threshold of 1000Hz, reducing the operating order of the Delta-Sigma modulator to the 1st or 2nd order to prevent transient value overflow in the modulation path.
[0009] Preferably, the method includes a local reference clock phase accumulation deviation compensation step based on asynchronous logic instructions: Step S1041, continuously monitor the time interval between two adjacent arrivals of asynchronous logic instructions, and count the total number of actual cycles of the local reference clock within the time interval; Step S1042, compare the total number of actual cycles with the nominal number of protocol cycles to obtain drift characteristic parameters characterizing the physical drift law of the local reference clock; Step S1043, perform feedforward incremental correction on the target frequency control word based on the drift characteristic parameters.
[0010] Preferably, step S1042 further includes: step S10421, determining the frequency temperature drift slope of the local crystal oscillator based on the difference between the nominal number of protocol cycles and the actual total number of cycles; step S10422, converting the frequency temperature drift slope into a frequency control word compensation amount to achieve real-time tracking and compensation for ambient temperature fluctuations.
[0011] Preferably, the loop gain adaptive matching step is included: step S1051, while injecting the discrete phase residual value into the Delta-Sigma modulator, the output current signal strength of the charge pump is adjusted; step S1052, the output current signal strength of the charge pump is linearly and synchronously increased with the increase of the target frequency control word, so as to maintain the phase-locked loop bandwidth fluctuation within a preset range of 10%.
[0012] Preferably, the phase stitching operation in step S103 includes: loading the discrete phase residual value into the initial phase register of the Delta-Sigma modulator, forcing the Delta-Sigma modulator to start accumulating from the phase bias state represented by the discrete phase residual value in the first reference clock cycle when the asynchronous logic instruction takes effect.
[0013] Preferably, the method relies entirely on the digital logic hard core inside the baseband application processing integrated chip. The digital logic hard core includes a flip-flop array, a combinational logic priority encoder, and topology routing between register pins. The method does not involve software intervention from an external floating-point processor.
[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention eliminates the arithmetic delay generated by digital integrated circuits when processing high-precision phase compensation by constructing a topological direct mapping mechanism from spatial phase sequence to phase word. It utilizes a parallel latch array to directly capture the transient level state of the multiphase clock network at the instant of asynchronous logic instruction transitions, and directly couples the captured spatial distribution information to the modulator's internal register through a combinational logic encoder. This hardware-level direct mapping method replaces the traditional serial operation links of measurement, calculation, and compensation, ensuring that the injection of phase residuals and frequency updates are synchronized in the physical time domain. This avoids phase slippage caused by pipeline delays in the arithmetic multiplier and maintains the phase continuity of the feedback loop at the instant of frequency instruction overwriting.
[0015] 2. By converting the time deviation between the asynchronous instruction start edge and the reference clock reference edge into a discrete phase residual value and injecting it as an initial condition into the generation process of the fractional frequency division sequence, the phase truncation caused by asynchronous frequency updates is repaired. This mechanism transforms the originally independent asynchronous timing characteristics into usable phase compensation resources, enabling the fractional frequency division control logic to adjust the accumulation state in real time according to the precise phase footprint of the asynchronous pulse arrival, eliminating transient broadband spurious signals during frequency switching. This phase stitching technology based on physical mechanisms improves the frequency consistency of the integrated circuit in a pure digital frequency modulation architecture without relying on external analog tuning devices.
[0016] 3. Combining a dynamic linkage strategy of digital frequency control word difference and modulation order, this method reduces noise floor through order increase processing in fine-tuning mode and prevents transient overflow of the modulation register through order decrease processing in large frequency offset mode. This closed-loop control logic, which adaptively configures modulation parameters according to the frequency hopping amplitude, enables the system to pursue ultimate frequency resolution while ensuring loop stability during rapid locking. The synergistic cooperation of multiple mechanisms enhances the adaptability of the feedback loop to different modulation depth requirements, achieving a balance between steady-state spectral purity and transient response speed. Attached Figure Description
[0017] Figure 1 This is the overall flowchart of the fractional frequency synthesis method for asynchronous logic instructions of the present invention; Figure 2 This is a schematic diagram illustrating the collaborative relationship of the various logical steps of the present invention under the triggering of asynchronous instructions.
[0018] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0020] A fractional frequency synthesis method based on asynchronous logic instructions includes the following steps: Step S101: Real-time monitoring of the triggering time of asynchronous logic instructions; using the parallel latch array integrated inside the baseband application processing integrated chip to capture the transient spatial level state of the multiphase voltage-controlled oscillator at the triggering time; obtaining the original quantization parameters; the original quantization parameters characterize the time deviation between the start edge of the asynchronous logic instruction and the local reference clock reference edge. Step S102: Based on the preset hard-wired topology mapping logic, the original quantization parameters are translated into discrete phase residual values. The discrete phase residual values represent the phase truncation error generated at the moment of asynchronous frequency control word update. The hard-wired topology mapping logic directly maps the parallel latch result to the accumulator register pin of the modulator through physical wiring to achieve hysteresis-free conversion of the original quantization parameters into phase compensation values. Step S103: Inject the discrete phase residual value as the initial phase bias. - The modulator's phase accumulation path is used to calculate the difference between the target frequency control word carried by the asynchronous logic instruction and the current frequency control word in real time, and to dynamically adjust the frequency control based on the absolute value range of the difference. - The modulator's operating order is adjusted, and phase stitching is achieved through a preset phase register at the frequency switching moment, thereby maintaining the phase continuity of the phase-locked loop at the moment of frequency word overwriting.
[0021] Preferably, step S101 specifically includes: step S1011, using a parallel latch array composed of multiple D flip-flops, synchronously sampling the 16 equally spaced phase tap levels of the multiphase voltage-controlled oscillator output at the start edge of the asynchronous logic instruction; step S1012, determining the physical phase distribution of the asynchronous logic instruction within the local reference clock cycle based on the physical spatial location of the level flip boundary in the parallel latch array, and obtaining spatially encoded data characterizing the time deviation as the original quantization parameter.
[0022] Preferably, step S102 specifically includes: step S1021, generating binary fractional codes based on the level-flipping boundary positions in the parallel latch array using a priority encoder with pure combinational logic; step S1022, coupling the binary fractional codes to the most significant bit pin of the internal accumulator register of the Delta-Sigma modulator using hardware metal trace topology, completing the asynchronous data translation of the original quantization parameters to eliminate pipeline delay introduced by the arithmetic logic unit.
[0023] Preferably, the operation of adjusting the operating order of the Delta-Sigma modulator in step S103 includes: step S1031, calculating the absolute value of the difference between the target frequency control word and the current frequency control word; step S1032, when the absolute value of the difference is lower than a preset threshold of 1000Hz, setting the operating order of the Delta-Sigma modulator to the 3rd or 4th order; step S1033, when the absolute value of the difference reaches or exceeds the preset threshold of 1000Hz, reducing the operating order of the Delta-Sigma modulator to the 1st or 2nd order to prevent transient value overflow in the modulation path.
[0024] Preferably, the logic for calculating the discrete phase residual value in step S102 follows the following formula: ,in, Here, ΔT represents the discrete phase residual value, and ΔT is the time deviation represented by the original quantization parameter. The period of the local reference clock. This is the accumulator bit width of the Delta-Sigma modulator.
[0025] Preferably, the method includes a local reference clock phase accumulation deviation compensation step based on asynchronous logic instructions: Step S1041, continuously monitor the time interval between two adjacent arrivals of asynchronous logic instructions, and count the total number of actual cycles of the local reference clock within the time interval; Step S1042, compare the total number of actual cycles with the nominal number of protocol cycles to obtain drift characteristic parameters characterizing the physical drift law of the local reference clock; Step S1043, perform feedforward incremental correction on the target frequency control word based on the drift characteristic parameters.
[0026] Preferably, step S1042 further includes: step S10421, determining the frequency temperature drift slope of the local crystal oscillator based on the difference between the nominal number of protocol cycles and the actual total number of cycles; step S10422, converting the frequency temperature drift slope into a frequency control word compensation amount to achieve real-time tracking and compensation for ambient temperature fluctuations.
[0027] Preferably, the loop gain adaptive matching step is included: step S1051, while injecting the discrete phase residual value into the Delta-Sigma modulator, the output current signal strength of the charge pump is adjusted; step S1052, the output current signal strength of the charge pump is linearly and synchronously increased with the increase of the target frequency control word, so as to maintain the phase-locked loop bandwidth fluctuation within a preset range of 10%.
[0028] Preferably, the phase stitching operation in step S103 includes: loading the discrete phase residual value into the initial phase register of the Delta-Sigma modulator, forcing the Delta-Sigma modulator to start accumulating from the phase bias state represented by the discrete phase residual value in the first reference clock cycle when the asynchronous logic instruction takes effect.
[0029] Preferably, the method relies entirely on the digital logic hard core inside the baseband application processing integrated chip. The digital logic hard core includes a flip-flop array, a combinational logic priority encoder, and topology routing between register pins. The method does not involve software intervention from an external floating-point processor.
[0030] Example 1: This example combines Figures 1 to 2 This section describes a fractional frequency synthesis method based on asynchronous logic instructions, such as... Figure 1As shown in the diagram, the process begins with the input of asynchronous logic instructions and the updating of the target frequency control word. The core execution path consists of three key steps. Step S101 involves acquiring the original quantization parameters, achieved by real-time monitoring of the asynchronous logic instruction trigger moment and capturing the transient spatial level state of the multiphase voltage-controlled oscillator using a parallel latch array. This is followed by step S102, which translates the parameters into discrete phase residual values. The core of this step lies in achieving a hysteresis-free conversion from the original quantization parameters to the phase compensation values based on hard-wired topology mapping logic. Finally, step S103 is executed to inject the phase bias and adjust the order, that is, injecting the discrete phase residual values as the initial phase bias into the modulator. The system performs phase accumulation path and dynamically adjusts the running order to complete phase stitching. While the main process is running, the system also performs local reference clock phase accumulation deviation compensation in parallel. By acquiring parameters that characterize the drift of the local reference clock and using these parameters to perform feedforward incremental correction on the target frequency control word, the system also implements loop gain adaptive matching. By synchronously adjusting the output current signal strength of the charge pump, the system maintains the bandwidth fluctuation of the phase-locked loop within a preset range. All these mechanisms work together to maintain the loop phase continuity, thereby effectively suppressing transient broadband spurious signals and shortening the lock-in time, ultimately achieving a balance between steady-state spectral purity and transient response speed.
[0031] like Figure 2 As shown, at the instant the asynchronous logic instruction is triggered, the system, on the one hand, uses a parallel latch array to capture the transient spatial level state of the multiphase voltage-controlled oscillator and translates the original quantization parameters into discrete phase residual values according to the hard-wired topology mapping logic. On the other hand, the discrete phase residual values are used as the initial phase bias injection into the phase accumulation path of the modulator. At the logic node marked as simultaneous, the system not only performs the loop gain adaptive matching step by adjusting the output current signal strength of the charge pump to make it linearly and synchronously increase with the increase of the target frequency control word, but also simultaneously performs dynamic adjustment of the modulator's operating order to complete phase stitching. Finally, it performs feedforward incremental correction of the target frequency control word according to the drift characteristic parameters. The entire set of interactive logic aims to maintain the phase continuity of the phase-locked loop at the instant of frequency word overwriting, thereby achieving a balance between steady-state spectral purity and transient response speed.
[0032] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.
[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims
1. A fractional-N frequency synthesis method based on asynchronous logic instructions, characterized in that, Includes the following steps: Step S101: Real-time monitoring of the triggering time of asynchronous logic instructions; using the parallel latch array integrated inside the baseband application processing integrated chip to capture the transient spatial level state of the multiphase voltage-controlled oscillator at the triggering time; obtaining the original quantization parameters; the original quantization parameters characterize the time deviation between the start edge of the asynchronous logic instruction and the local reference clock reference edge. Step S102: Based on the preset hard-wired topology mapping logic, the original quantization parameters are translated into discrete phase residual values. The discrete phase residual values represent the phase truncation error generated at the moment of asynchronous frequency control word update. The hard-wired topology mapping logic directly maps the parallel latch result to the accumulator register pin of the modulator through physical wiring to achieve hysteresis-free conversion of the original quantization parameters into phase compensation values. Step S103, inject the discrete phase residual value as initial phase bias - The phase accumulation path of the modulator, and real-time calculate the difference between the target frequency control word carried by the asynchronous logic instruction and the current frequency control word, dynamically adjust according to the absolute value range of the difference - The operating order of the modulator, and the phase stitching is completed by presetting the phase register at the frequency switching moment, so as to maintain the phase continuity of the phase-locked loop at the moment of frequency word overwriting.
2. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, Step S101 specifically includes: Step S1011, using a parallel latch array composed of multiple D flip-flops, synchronously sampling the 16 equally spaced phase tap levels of the multiphase voltage-controlled oscillator output at the start edge of the asynchronous logic instruction; Step S1012, based on the physical spatial location of the level flip boundary in the parallel latch array, determining the physical phase distribution of the asynchronous logic instruction within the local reference clock cycle, and obtaining spatially encoded data characterizing the time deviation as the original quantization parameter.
3. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, Step S102 specifically includes: Step S1021, generating binary fractional codes based on the level-flipping boundary positions in the parallel latch array using a priority encoder with pure combinational logic; Step S1022, coupling the binary fractional codes to the most significant bit pin of the internal accumulator register of the Delta-Sigma modulator using hardware metal trace topology, completing the asynchronous data translation of the original quantization parameters to eliminate pipeline delay introduced by the arithmetic logic unit.
4. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, The operation of adjusting the operating order of the Delta-Sigma modulator in step S103 includes: step S1031, calculating the absolute value of the difference between the target frequency control word and the current frequency control word; step S1032, when the absolute value of the difference is lower than the preset threshold of 1000Hz, setting the operating order of the Delta-Sigma modulator to the 3rd or 4th order; step S1033, when the absolute value of the difference reaches or exceeds the preset threshold of 1000Hz, reducing the operating order of the Delta-Sigma modulator to the 1st or 2nd order to prevent transient value overflow in the modulation path.
5. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, The local reference clock phase accumulation deviation compensation step based on asynchronous logic instructions includes: Step S1041, continuously monitor the time interval between two adjacent arrivals of asynchronous logic instructions, and count the total number of actual cycles of the local reference clock within the time interval; Step S1042, compare the total number of actual cycles with the nominal number of protocol cycles to obtain the drift characteristic parameter characterizing the physical drift law of the local reference clock. Step S1043: Perform feedforward incremental correction on the target frequency control word based on the drift characteristic parameters.
6. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 5, characterized in that, Step S1042 further includes: Step S10421, determining the frequency temperature drift slope of the local crystal oscillator based on the difference between the nominal number of protocol cycles and the actual total number of cycles; Step S10422, converting the frequency temperature drift slope into a frequency control word compensation amount to achieve real-time tracking and compensation for ambient temperature fluctuations.
7. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, The loop gain adaptive matching step includes: Step S1051, while injecting the discrete phase residual value into the Delta-Sigma modulator, adjusting the output current signal strength of the charge pump; Step S1052, making the output current signal strength of the charge pump linearly and synchronously increase with the increase of the target frequency control word, so as to maintain the fluctuation of the phase-locked loop bandwidth within a preset range of 10%.
8. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, The phase stitching operation in step S103 includes: loading the discrete phase residual value into the initial phase register of the Delta-Sigma modulator, forcing the Delta-Sigma modulator to start accumulating from the phase bias state represented by the discrete phase residual value in the first reference clock cycle when the asynchronous logic instruction takes effect.
9. The fractional frequency synthesis method based on asynchronous logic instructions according to claim 1, characterized in that, The method relies entirely on the digital logic hard core inside the baseband application processing integrated chip. The digital logic hard core includes a flip-flop array, a combinational logic priority encoder, and topology routing between register pins. The method does not involve software intervention from an external floating-point processor.