Satellite communication navigation chip and satellite communication navigation system

Abstract

The application discloses a satellite communication navigation chip and a satellite communication navigation system, and belongs to the technical field of wideband satellite communication. The satellite communication navigation chip comprises a chip main body, a radio frequency front end module, a first analog / digital converter, a shared baseband bus, a GNSS receiving module, a baseband modulation and demodulation module and a shared module which are arranged on the chip main body. The satellite communication necessary function modules are highly integrated in a single chip, and low power consumption, small size and high reliability design are realized. The satellite communication navigation chip supports dynamic expansion of array element scale, can realize 8-array element, 16-array element or even higher scale digital beamforming and signal processing through FPGA, and remarkably improves the positioning precision, anti-interference capability and wideband communication performance of the satellite communication navigation system.

Description

Technical Field

[0001] This invention relates to the field of broadband satellite communication technology, specifically to a satellite communication and navigation chip and a satellite communication and navigation system. Background Technology

[0002] With the rapid development of broadband satellite communication, satellite terminals need to simultaneously possess high-precision GNSS positioning and timing, broadband communication modulation and demodulation, and efficient radio frequency front-end processing capabilities to meet the demands for low latency, high throughput, and strong anti-interference. Traditional satellite communication terminals mostly adopt discrete or multi-chip module designs, resulting in large size, high power consumption, high cost, and low integration. Furthermore, the expansion of array antennas requires a large amount of additional hardware, making it difficult to adapt to the miniaturization and array-based trends of LEO terminals.

[0003] While there has been some exploration of chip integration in existing technologies, they all have obvious limitations: they do not integrate GNSS, satellite communication modem, and complete broadband radio frequency links (filtering, amplification, frequency conversion) into a single chip, and they have not proposed effective solutions for the standardized application of broadband communication terminals in low-altitude economic scenarios.

[0004] Furthermore, while beamforming-related patents involve FPGA-controlled array expansion, they are not integrated with the GNSS / modem / RF front-end. L / S band LEO system terminals such as Globalstar mostly use commercial discrete chip solutions, resulting in low integration and complex array expansion.

[0005] The common problems of existing technologies include: (1) GNSS, modem, and RF front-end (filtering, amplification, frequency conversion) are difficult to achieve high integration on a single chip; (2) LEO broadband terminal optimization in S / L band is insufficient; (3) the expansion of array element scale depends on multiple chips or external hardware, which is costly and has poor scalability. Summary of the Invention

[0006] The purpose of this invention is to provide a satellite communication and navigation chip and a satellite communication and navigation system to solve at least one of the above-mentioned problems.

[0007] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A satellite communication and navigation chip includes: a chip body, the chip body integrating: Radio frequency front-end module; used to receive RF signals and perform pre-processing on the RF signals; The first analog-to-digital / digital-to-analog converter is communicatively connected to the RF front-end module and is used to receive the signal processed by the RF front-end module and convert it into a digital signal. A shared baseband bus is communicatively connected to a first analog-to-digital / digital-to-analog converter (ADC) for receiving digital signals transmitted by the first ADC, including GNSS digital signals and satellite communication digital signals. GNSS receiver module; The GNSS receiver module is connected to the shared baseband bus for communication and is used to receive GNSS digital signals transmitted by the shared baseband bus, and to measure pseudorange and carrier phase through the received GNSS digital signals; Baseband modulation and demodulation module; The baseband modulation and demodulation module is connected to the shared baseband bus and is used to receive satellite communication digital signals transmitted by the shared baseband bus and demodulate the received satellite communication digital signals. The shared module is bidirectionally connected to both the GNSS receiver module and the baseband modem module to provide shared signals and data output.

[0008] Furthermore, the aforementioned RF front-end module includes a low-noise amplifier, an on-chip filter, a power amplifier, and a frequency converter that are connected in sequence; the low-noise amplifier is used to receive RF signals.

[0009] Furthermore, the aforementioned RF front-end module includes a low-noise amplifier, a power amplifier, and a frequency converter; the low-noise amplifier is used to receive RF signals; the low-noise amplifier is connected to the power amplifier through an on-chip filter located on the periphery of the chip body.

[0010] Furthermore, the aforementioned low-noise amplifier has a common source cascode topology; the on-chip filter is a SAW filter or a BAW filter; the power amplifier has a Class AB structure; and the frequency converter is a passive mixer integrated with a VCO and PLL structure.

[0011] Furthermore, the aforementioned RF signals include GNSS signals and satellite communication signals, with the satellite communication signals having a frequency band of at least one of U, S, L, C, Ku, K, and Ka.

[0012] Furthermore, the aforementioned GNSS receiver module integrates four parallel channels.

[0013] Furthermore, the chip also includes uplink data processing; the RF front-end module is also used to upconvert analog intermediate frequency signals to RF signals; The first analog-to-digital / digital-to-analog converter is also used to convert digital signals into analog intermediate frequency signals; The baseband modulation and demodulation module is also used to modulate satellite communication digital signals and transmit them to the first analog-to-digital / digital-to-analog converter via a shared baseband bus.

[0014] Furthermore, the aforementioned satellite communication and navigation chip also includes a timing module, which is communicatively connected to the shared baseband bus, the GNSS receiving module, and the baseband modem module to achieve time calibration.

[0015] Furthermore, the aforementioned shared module includes a second analog-to-digital / digital-to-analog converter, a clock synchronization unit, and a power management unit.

[0016] A satellite communication and navigation system includes: a phased array antenna, a dynamic configuration bus, an FPGA chip, and N of the above-mentioned satellite communication and navigation chips, where N is a positive integer; The satellite communication and navigation chip includes a 4-channel digital I / Q output and input interface. All satellite communication and navigation chips are connected in parallel between the phased array antenna and the dynamic configuration bus. The dynamic configuration bus is also connected to the FPGA chip.

[0017] The present invention has the following beneficial effects: (1) The satellite communication and navigation chip of the present invention integrates the complete radio frequency front-end module, baseband modulation and demodulation module, GNSS receiving module and other necessary satellite communication functional modules into a single chip. It is optimized for S / L band LEO broadband terminals, reducing the size by more than 50%, reducing power consumption by more than 30%, and significantly reducing cost.

[0018] (2) The satellite communication and navigation chip of the present invention supports dynamic expansion of array element scale. Specifically, a single chip integrates 4 array element GNSS processing capabilities, and FPGA realizes digital beamforming and signal processing of 8 array elements, 16 array elements or even higher scale, which significantly improves the positioning accuracy, anti-interference capability and broadband communication performance of the satellite communication and navigation system.

[0019] (3) This invention achieves low-cost array expansion through the “chip + FPGA” architecture, breaks through the existing module channel limitations, is suitable for high-performance LEO satellite communication terminals, and improves link redundancy and mobility. Attached Figure Description

[0020] Figure 1 This is a block diagram of the internal structure of a satellite communication and navigation chip provided in an embodiment of the present invention; Figure 2 An extended schematic diagram of the satellite communication and navigation chip provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the L1 / S signal spectrum of the satellite communication and navigation chip provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the correlation peak curve of the satellite communication and navigation chip after Doppler compensation, provided in an embodiment of the present invention. Figure 5 The extended beam pattern of the four satellite communication and navigation chips provided in this embodiment of the invention.

[0021] In the image: 100 - the main body of the chip. Detailed Implementation

[0022] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0023] like Figure 1 As shown, this embodiment provides a satellite communication and navigation chip, including a chip body 100, and an integrated radio frequency front-end module, a first analog-to-digital / digital-to-analog converter, a shared baseband bus, a GNSS receiver module, a baseband modem module, and a shared module. This chip highly integrates the essential functional modules for satellite communication into a single chip, achieving a low-power, small-size, and highly reliable design.

[0024] The chip body 100 is manufactured on a single silicon-based chip. Preferably, the chip body 100 is packaged in SiP or Flip-Chip and can be directly integrated with a satellite communication antenna. When the chip body 100 is packaged in SiP, a SAW filter can be integrated into the chip body 100.

[0025] Preferably, the chip body 100 employs a 28nm RF-SOI process, or a compatible 40nm or 28nm CMOS RF process. These processes provide excellent RF performance in the S / L band, specifically in terms of: low parasitic capacitance, which helps reduce high-frequency losses; transistors with high characteristic frequencies and highest oscillation frequencies, ensuring good high-frequency gain and speed; and support for forward body bias (FBB) technology, which can dynamically adjust power consumption and linearity to optimize power consumption while meeting system requirements. Furthermore, these processes also support high-density digital logic integration, facilitating the integration of digital control and RF circuitry onto the same chip.

[0026] The radio frequency front-end module is used to receive RF (Radio Frequency) input signals and perform pre-processing on the RF signals. The RF signals include GNSS signals, satellite communication signals in at least one of the frequency bands U, S, L, C, Ku, K and Ka. That is, the satellite communication and navigation chip described in this invention can realize multi-band satellite communication functions.

[0027] In this embodiment, the radio frequency front-end module includes a low-noise amplifier (LNA), an on-chip filter, a power amplifier (PA), and a frequency converter that are connected in sequence, that is, a complete radio frequency front-end module is integrated within the chip body 100.

[0028] The low-noise amplifier (LNA) is used to receive RF signals and employs a cascode topology, which provides high gain while effectively suppressing the Miller effect. Its input is optimized for noise and input impedance through source inductor degradation matching, and the load consists of an on-chip spiral inductor and MIM capacitors, saving off-chip components while ensuring good resonant characteristics. This LNA also supports dynamic adjustment via the forward back bias (FBB) voltage, with an adjustment range of 0.5V to 2V.

[0029] Typically, at a 2.4GHz operating frequency, by properly setting this bias voltage, a noise figure of no more than 1.8dB and a gain of 16dB can be achieved, while the power consumption per channel is controlled to within 50mW. This performance allows it to meet the requirements of a low-power, high-sensitivity receiver link.

[0030] The RF signal is then input to the on-chip filter after passing through a low-noise amplifier (LNA). After filtering, the signal is input to the subsequent circuitry inside the chip. Preferably, the on-chip filter is located outside the chip.

[0031] Preferably, the on-chip filter is a SAW filter or a BAW filter.

[0032] In existing technologies, SAW (Surface Acoustic Wave) and BAW (Bulk Acoustic Wave) filters are typically designed off-chip, primarily due to significant differences in material systems, fabrication processes, and physical structures compared to CMOS processes. However, in this embodiment, the following design scheme is adopted for the system-level integration of SAW / BAW filters: 1) For SAW filters, the separately manufactured filter dies and RF transceiver chips are packaged in the same module to balance performance and integration; or the filter chips are packaged on the wafer to achieve ultra-miniaturization of the integrated module. 2) For BAW filters, SAW filters are replaced in frequency bands above 2.5GHz. With the continuous improvement of the integration of BAW filters and the complete single-chip integration with the RF front-end module, the packaging complexity is significantly reduced.

[0033] The power amplifier (PA) receives the signal transmitted from the on-chip filter, amplifies it, and then inputs it to the subsequent circuitry inside the chip. Preferably, the power amplifier (PA) adopts a Class AB structure, achieving a good balance between efficiency and linearity. Its output 1dB compression point is not less than 20dBm, which can meet the requirements of low-Earth orbit satellite systems like Globalstar for the output power and linearity of the transmission link. Furthermore, this power amplifier (PA) requires only a few external matching components or simple passive filters to operate normally, facilitating system integration and helping to reduce circuit board area and material costs.

[0034] The inverter receives the signal transmitted from the power amplifier (PA) and, after frequency conversion, inputs it to the subsequent circuitry inside the chip. Preferably, the inverter employs a passive mixer combined with an integrated VCO and PLL structure, achieving a balance between low power consumption and high linearity. It supports two receiving architectures: one is a direct RF-to-baseband (RF-to-BB) downconversion method, which simplifies the zero-IF path; the other is a low-IF architecture, which helps avoid DC offset and flicker noise issues. Regarding image rejection performance, this scheme achieves a rejection ratio better than 50dB, effectively reducing the impact of image interference on the received signal, thereby ensuring the quality of subsequent demodulation.

[0035] In other embodiments of the present invention, the radio frequency front-end module may also include only a low-noise amplifier (LNA), a power amplifier (PA), and a frequency converter. In this case, the low-noise amplifier (LNA) is communicatively connected to the power amplifier (PA) through an on-chip filter located on the periphery of the chip body 100, and the power amplifier (PA) is communicatively connected to the frequency converter. The structures of the low-noise amplifier (LNA), the on-chip filter, the power amplifier (PA), and the frequency converter are the same as described above, and will not be repeated here.

[0036] The first analog-to-digital / digital-to-analog converter (AD / DA) is connected to the frequency converter and the shared baseband bus respectively. It is used to receive the signals transmitted by the frequency converter and convert them into digital signals, such as GNSS digital signals and satellite communication digital signals, and input the digital signals to the shared baseband bus.

[0037] The GNSS receiver module communicates with the shared baseband bus to receive GNSS digital signals transmitted via the shared baseband bus and measures pseudorange and carrier phase using the received GNSS digital signals. The GNSS receiver module pre-integrates four parallel channels, supporting parallel acquisition and tracking of multiple frequency points (L1 / L2 / L5 / S) and multiple constellations (GPS / BeiDou / Galileo / GLONASS).

[0038] The baseband modem module communicates with the shared baseband bus to receive satellite digital signals transmitted via the shared baseband bus and demodulate the received signals. This module integrates forward error correction (FEC) encoding / decoding, modulation / demodulation, and MAC layer protocol processing functions. The FEC encoding / decoding is compatible with DVB-S2X and 3GPP NTN standards, effectively improving channel transmission reliability. The module supports data transmission rates of at least 2 Mbps and incorporates Doppler compensation capabilities for low Earth orbit (LEO) satellites, with a compensation range of ±40 kHz, enabling stable carrier synchronization under high-speed relative motion.

[0039] Preferably, the baseband modulation and demodulation module is also tightly coupled with the GNSS receiving module through the on-chip PPS timing signal and the shared observation data interface, thereby completing the integration of communication and navigation. It can use GNSS timing to assist communication synchronization and also enhance positioning performance with the help of the communication link.

[0040] More preferably, the chip body 100 also integrates a timing module, which is communicatively connected to the shared baseband bus, the GNSS receiving module and the baseband modulation and demodulation module, respectively, for time calibration.

[0041] The shared module is communicatively connected to the GNSS receiving module and the baseband modulation and demodulation module. The shared module includes a second analog-to-digital / digital-to-analog converter, a clock synchronization unit, and a power management unit, which are used to provide shared signals and data outputs. The output signal is an analog intermediate frequency signal (IF signal).

[0042] The satellite communication and navigation chip in this embodiment also includes uplink data processing, wherein: The RF front-end module is also used to upconvert analog intermediate frequency signals to RF signals; The first analog-to-digital / digital-to-analog converter is also used to convert digital signals into analog intermediate frequency signals; The baseband modulation and demodulation module is also used to modulate satellite communication digital signals and transmit them to the first analog-to-digital / digital-to-analog converter via a shared baseband bus.

[0043] The satellite communication and navigation chip in this embodiment implements the following processing flow for receiving satellite communication signals: The RF signal (at least one of GNSS signal, S-band satellite communication signal, L-band satellite communication signal, C-band satellite communication signal, and U-band satellite communication signal) is transmitted to a low-noise amplifier (LNA). The LNA then outputs the amplified RF signal to an on-chip filter. The on-chip filter filters the signal and transmits it to a power amplifier. After amplitude adjustment by the power amplifier, the signal is transmitted to a frequency converter. The frequency converter adjusts the frequency, and the frequency-adjusted signal is converted from analog to digital by a first analog-to-digital converter (AD / DA) and transmitted to the baseband bus. The GNSS receiver module receives GNSS digital signals transmitted via a shared baseband bus, measures pseudorange and carrier phase, thereby obtaining the distance between satellites and satellite communication terminals as well as information on carrier signal changes. Simultaneously, the digital signal processor within the baseband modulation and demodulation module performs data modulation on the received satellite communication digital signals transmitted via the shared baseband bus, extracting useful data such as navigation messages.

[0044] The satellite communication and navigation chip of this embodiment was simulated and compared with the traditional discrete solution. The simulation comparison results are shown in Table 1.

[0045] Table 1. Simulation Comparison Results of Satellite Communication and Navigation Chip (In This Embodiment) and Traditional Discrete Multi-Chip Solution As can be seen, compared with the traditional discrete solution, the satellite communication and navigation chip in this embodiment reduces the noise figure, power consumption and chip area, and improves GNSS positioning accuracy, modem data rate and anti-interference capability.

[0046] The satellite communication and navigation chip provided in this embodiment supports dynamic expansion of array element scale. For example, a single chip can integrate 4 array element GNSS processing capabilities, and FPGA can be used to realize digital beamforming and signal processing of 8, 16, or even higher scale array elements, which significantly improves the positioning accuracy, anti-interference and anti-spoofing capabilities, and broadband communication performance of the terminal.

[0047] like Figure 2 As shown, this embodiment also provides a satellite communication and navigation system, including: a phased array antenna, a dynamic configuration bus, an FPGA chip, and N of the above-mentioned satellite communication and navigation chips, where N is a positive integer.

[0048] The satellite communication and navigation chip includes a 4-channel digital I / Q output and input interface. All satellite communication and navigation chips are connected in parallel between the phased array antenna and the dynamic configuration bus. The dynamic configuration bus is also connected to the FPGA chip, thereby realizing digital beamforming and signal processing of 4-element, 8-element, 16-element or even higher scale.

[0049] In this embodiment, the FPGA chip includes a high-speed SerDes interface, a digital beamforming module, a multi-channel synchronization module, and an amplitude and phase adjustment module. It is capable of digital beamforming, performing synchronization calibration between multiple channels, phase and amplitude calibration of each channel, and dynamic adjustment of array element configuration. The high-speed SerDes interface communicates with the dynamic configuration bus and supports a data rate of at least 10Gbps per channel, thereby ensuring the high throughput and low latency required for real-time multi-channel beamforming.

[0050] The satellite communication and navigation system in this embodiment uses a 4-element chip as the basic unit and can be flexibly expanded to 8 or 16 elements. As the number of elements increases, the array gain increases according to the law of 10lg(N): when expanded to 16 elements, the array gain can increase by 6dB; correspondingly, the signal-to-noise ratio (SNR) of the received signal is improved by more than 6dB compared with the 4-element system, and the anti-interference capability (measured by the interference-to-signal ratio J / S tolerance) is improved by 10dB; in addition, the beamwidth is significantly narrowed to 11°, and the sidelobe level is lower than -18dB, thereby obtaining sharper directivity and better spatial filtering performance.

[0051] Even after expansion, the system still supports hot-swappable dynamic configuration, meaning that array elements can be dynamically added or removed, or the operating mode adjusted, without power interruption, and the processing latency for the entire beamforming process is less than 10 microseconds. This low-latency characteristic makes it ideal for use in satellite communication antennas for highly maneuverable low-Earth orbit (LEO) satellite terminals. In this application scenario, beamforming effectively improves the link margin—by ​​at least 6 dB—thus enhancing the reliability of the communication link; simultaneously, due to more precise beam pointing, combined with array signal processing, the terminal's positioning accuracy can be better than 1 meter.

[0052] Furthermore, GNSS observation data and baseband data from the baseband modulation and demodulation module are jointly processed within the FPGA chip, achieving integrated communication and navigation at the entire array level. This means that the satellite communication antenna is not only used for communication beamforming but also participates in the reception and processing of GNSS signals, thereby further enhancing anti-interference capabilities and positioning continuity.

[0053] Simulations were performed on the satellite communication and navigation system of this embodiment with array sizes of 4, 8, and 16 elements. The simulation results are shown in Table 2.

[0054] Table 2 Simulation results of multi-element expansion performance like Figures 3 to 5The diagram shows the signal processing flow and key simulation results of the satellite communication and navigation chip provided in this embodiment under the S / L band low-orbit broadband satellite communication scenario. It intuitively verifies the GNSS positioning, modem demodulation, anti-Doppler interference, and beamforming performance of the satellite communication and navigation chip after array element expansion.

[0055] The simulation uses a 3GPP NTN LEO channel model (Doppler ±40kHz, Rayleigh fading), with an operating frequency of 2.4GHz and 28nm RF-SOI process parameters.

[0056] Figure 3 The diagram shows the spectrum of the input L1 / S signal. As can be seen from the spectrum curves in the diagram, the Doppler frequency shift caused by the high-speed motion of the LEO satellite, as well as issues such as signal spectrum broadening and peak shift before pre-compensation, will lead to GNSS lockout and modem demodulation failure if not handled properly.

[0057] Figure 4 This is a schematic diagram of the correlation peak curve after Doppler compensation. The curve shape shows that the correlation peak is extremely sharp and the main-to-side lobe ratio is extremely high after compensation, proving that the Doppler compensation algorithm (shared by the chip's GNSS and modem) achieves complete pseudocode / carrier alignment, with an acquisition success rate close to 100%. The red curve represents the correlation peak after Doppler frequency offset compensation; the green curve represents the correlation peak finally used for GNSS acquisition and modem demodulation after compensation and filtering. It can be observed that the green curve is sharper and has lower sidelobes than the red curve; the blue curve represents the incoherent amplitude envelope signal finally used for acquisition decision by baseband processing.

[0058] The three curves—original RF correlation peak, filtered I-channel correlation peak, and amplitude envelope—show the end-to-end performance from the original signal to the filtered signal and envelope extraction, with the interference immunity significantly improved to +55 dB. Specific numerical comparison results are shown in Table 3. Table 3. Comparison of numerical values ​​of original RF correlation peaks, filtered I-channel correlation peaks, and amplitude envelopes. Figure 5 The digital beamforming pattern of the 16-element array (4 four-element chips + FPGA expansion) shows that the array gain strictly follows the 10lg(N) rule, the signal-to-noise ratio (SNR) is improved by 6dB, the beamwidth is significantly compressed, and the anti-interference capability is improved quadratically with the number of array elements.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A satellite communication and navigation chip, characterized in that, include: Chip body (100), wherein the chip body (100) integrates: RF front-end module; Used to receive RF signals and perform preprocessing on the RF signals; A first analog-to-digital (ADI) / digital-to-analog (DAC); the first ADI / DAC is communicatively connected to the RF front-end module and is used to receive the signal pre-processed by the RF front-end module and convert it into a digital signal; A shared baseband bus; the shared baseband bus is communicatively connected to the first analog-to-digital / digital-to-analog converter and is used to receive digital signals transmitted by the first analog-to-digital / digital-to-analog converter, the digital signals including GNSS digital signals and satellite communication digital signals; GNSS receiver module; The GNSS receiving module is communicatively connected to the shared baseband bus and is used to receive GNSS digital signals transmitted by the shared baseband bus, and to measure pseudorange and carrier phase through the received GNSS digital signals; Baseband modulation and demodulation module; The baseband modulation and demodulation module is connected to the shared baseband bus and is used to receive the satellite communication digital signal transmitted by the shared baseband bus and demodulate the received satellite communication digital signal. Shared modules; The shared module is bidirectionally connected to both the GNSS receiving module and the baseband modulation and demodulation module to provide shared signals and data output.

2. The satellite communication and navigation chip according to claim 1, characterized in that, The radio frequency front-end module includes a low-noise amplifier, an on-chip filter, a power amplifier, and a frequency converter that are connected in sequence; the low-noise amplifier is used to receive RF signals.

3. The satellite communication and navigation chip according to claim 1, characterized in that, The radio frequency front-end module includes a low-noise amplifier, a power amplifier, and a frequency converter; the low-noise amplifier is used to receive RF signals; the low-noise amplifier is connected to the power amplifier through an on-chip filter located on the periphery of the chip body (100).

4. The satellite communication and navigation chip according to claim 2 or 3, characterized in that, The low-noise amplifier has a common source cascode topology; the on-chip filter is a SAW filter or a BAW filter; the power amplifier has a Class AB structure; and the frequency converter is a passive mixer integrated with a VCO and PLL structure.

5. The satellite communication and navigation chip according to claim 1, characterized in that, The RF signal includes GNSS signal and satellite communication signal, and the frequency band of the satellite communication signal is at least one of U, S, L, C, Ku, K and Ka.

6. The satellite communication and navigation chip according to claim 1, characterized in that, The GNSS receiver module integrates four parallel channels.

7. The satellite communication and navigation chip according to claim 1, characterized in that, The chip also includes uplink data processing; the radio frequency front-end module is also used to upconvert analog intermediate frequency signals to radio frequency signals; The first analog-to-digital / digital-to-analog converter is also used to convert digital signals into analog intermediate frequency signals; The baseband modulation and demodulation module is also used to modulate satellite communication digital signals and transmit them to the first analog-to-digital / digital-to-analog converter via the shared baseband bus.

8. The satellite communication and navigation chip according to claim 7, characterized in that, It also includes a time synchronization module, which is communicatively connected to the shared baseband bus, the GNSS receiving module, and the baseband modulation and demodulation module, respectively, for time calibration.

9. The satellite communication and navigation chip according to claim 1, characterized in that, The shared module includes a second analog-to-digital / digital-to-analog converter, a clock synchronization unit, and a power management unit.

10. A satellite communication and navigation system, characterized in that, include: The system comprises a phased array antenna, a dynamic configuration bus, an FPGA chip, and N satellite communication and navigation chips as described in any one of claims 1 to 9, wherein N is a positive integer; The satellite communication and navigation chip includes a 4-channel digital I / Q output and input interface. All the satellite communication and navigation chips are connected in parallel between the phased array antenna and the dynamic configuration bus. The dynamic configuration bus is also connected to the FPGA chip.

Images