Event timeout detection method, device and chip

Abstract

This disclosure provides an event timeout detection method, apparatus, and chip. The method includes: based on a first event signal, sending a timing start signal to a timing module via an event trigger module to trigger the timing module to start timing; detecting a second event signal; if the second event signal is detected, sending a timing stop signal to the timing module via the event trigger module to control the timing module to stop timing; if the timing module does not receive the timing stop signal within a timing threshold, generating a timeout interrupt signal. Therefore, this disclosure, through a hardware detection link constructed by an event trigger module and a timing module, can realize timeout detection for different types of events, ensuring the accuracy of timeout detection and the stability of system operation.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and in particular to an event timeout detection method, apparatus, electronic device, storage medium, and chip for internal event processing of a chip. Background Technology

[0002] In embedded systems or System-on-a-Chip (SoC) architectures, efficient data interaction between data transceiver modules (such as UART, SPI, and other communication peripherals) and data transfer modules (such as DMA) typically relies on event triggering and response mechanisms. However, in real-world operating environments, this mechanism may encounter the following abnormal situations: 1. Random events not generated on time: External modules fail to initiate data requests to the chip system's data transceiver module according to the timing protocol. This situation may cause system processes to suspend, state machines to stall, or computing resources to wait ineffectively, resulting in a waste of system resources.

[0003] 2. Single event processing timeout: After receiving a data send / receive request, the data transfer module fails to complete the data transfer operation within the preset time window due to hardware failure, bus congestion, or software deadlock, resulting in task execution timeout.

[0004] Existing on-chip timeout detection mechanisms mainly rely on software polling of the central processing unit (CPU) or basic system timers. However, these mechanisms consume a lot of CPU computing power, resulting in a decrease in overall operating efficiency and an increase in power consumption. Moreover, the detection granularity of such mechanisms is relatively coarse, making it difficult to accurately capture transient anomalies.

[0005] Therefore, there is an urgent need for a timeout protection mechanism that can balance high-precision detection with low resource consumption to meet the design requirements of high-performance, low-power chips. Summary of the Invention

[0006] In view of this, this disclosure provides an event timeout detection scheme, which aims to solve the problems of poor flexibility, low real-time performance and high resource consumption of existing internal chip event timeout detection, and to achieve efficient detection of timeouts of different types of events inside the chip, thereby improving the stability and reliability of chip system operation.

[0007] According to a first aspect of this disclosure, an event timeout detection method is provided, applied to a main device including an event triggering module and a timing module. The method includes: sending a timing start signal to the timing module through the event triggering module based on a first event signal to trigger the timing module to start timing; detecting a second event signal; if the second event signal is detected, sending a timing stop signal to the timing module through the event triggering module to control the timing module to stop timing; and generating a timeout interrupt signal if the timing module does not receive a timing stop signal within a timing threshold.

[0008] According to a second aspect of this disclosure, an event timeout detection device is provided, comprising: a peripheral module, an event triggering module, a timing module, and a processor; the peripheral module is configured to generate a first event signal and a second event signal; the event triggering module is connected to the peripheral module and the timing module, and is configured to send a timing start signal to the timing module based on the first event signal, and to send a timing stop signal to the timing module based on the second event signal; the timing module is connected to the processor, and is configured to start a timing operation based on the timing start signal, stop the timing operation based on the timing stop signal, and send a timeout interrupt signal to the processor if no timing stop signal is received within a timing threshold.

[0009] According to a third aspect of this disclosure, a chip is provided, including an event timeout detection device as described in the second aspect, for performing timeout detection on single or random events within the chip via the event timeout detection device.

[0010] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to perform an operation corresponding to the event timeout detection method described in the first aspect.

[0011] According to a fifth aspect of this disclosure, a computer-readable storage medium is provided, wherein computer instructions are stored thereon, which, when executed by a processor, cause the processor to perform the event timeout detection method as described in the first aspect.

[0012] The event timeout detection scheme disclosed herein establishes a hardware control mechanism based on the coordinated operation of an event triggering module and a timing module. This mechanism starts timing based on a first event signal and stops timing based on a second event signal. If no stop signal is received within the timing threshold, a timeout interrupt is automatically generated. This scheme has broad scenario adaptability and can flexibly adapt to timeout monitoring of various events within the chip, effectively preventing process deadlocks and system failures, and significantly enhancing the stability and reliability of chip operation. Furthermore, thanks to the fully hardware-based detection closed loop, this scheme completely abandons the traditional software polling mode, significantly reducing CPU resource consumption while improving system response speed. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic diagram of the hardware architecture of a master device suitable for executing the event timeout detection methods of the embodiments of this disclosure.

[0015] Figure 2 A flowchart of the event timeout detection method of the exemplary embodiments of this disclosure.

[0016] Figure 3 This is a flowchart illustrating an event timeout detection method as another exemplary embodiment of the present disclosure.

[0017] Figures 4A to 4B For corresponding Figure 3 The diagram shows the hardware architecture of the event timeout detection method.

[0018] Figure 5 This is a flowchart illustrating an event timeout detection method as another exemplary embodiment of the present disclosure.

[0019] Figures 6A to 6B For corresponding Figure 5 The diagram shows the hardware architecture of the event timeout detection method.

[0020] Figure 7 A structural block diagram of an event timeout detection apparatus for disclosing an exemplary embodiment.

[0021] Figure 8 A simplified structural diagram of an electronic device that is an exemplary embodiment of this disclosure. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art should fall within the protection scope of this disclosure.

[0023] Reference is made to the accompanying drawings, which form part of the detailed description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0024] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the embodiments described herein. Throughout this specification, references to “embodiment,” “one embodiment,” or “some embodiments” mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment herein. Therefore, the phrases “in an embodiment,” “in one embodiment,” or “some embodiments” appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any way that does not mutually exclude particular features, structures, functions, or characteristics associated with two embodiments.

[0025] As used in the description and appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] As described throughout this document and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0027] In the event processing system inside the chip, there are event requests, data interactions and processing operations between various peripherals. In actual operation, two typical abnormal situations are likely to occur: one is that random event requests time out without response, that is, after the processing of the preceding event is completed, the subsequent new random event is not generated and a request is initiated within the preset time; the other is that the processing within a single event request times out, that is, after a single event request is initiated, the corresponding processing module does not complete the event processing and provide feedback within the specified time.

[0028] If the aforementioned anomalies are not detected and handled in a timely manner, they will cause the internal event processing flow of the chip to stall, data transmission to be interrupted, and may even lead to the malfunction of the entire chip system, reducing the stability and reliability of the chip. In existing technologies, the detection of timeouts for internal chip events mostly adopts a single hardware timing or software polling method. Hardware timing is inflexible and cannot adapt to different types of event timeout detection requirements, while software polling consumes a large amount of CPU resources and has low real-time performance, making it difficult to accurately and efficiently implement timeout protection for various events.

[0029] Based on the various problems existing in the prior art, the embodiments of this disclosure provide an event timeout detection method that can adapt to the timeout detection of different types of events inside the chip, and has the advantages of high detection accuracy and low resource consumption.

[0030] The specific implementations of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings: To facilitate readers' clear understanding of the specific implementation methods of the various embodiments of this disclosure, the application scenarios are first briefly described below.

[0031] Figure 1 This is a hardware architecture diagram suitable for implementing the event timeout detection methods of the embodiments of this disclosure. As shown, the methods of the embodiments of this disclosure are applied to a main device 100. In this embodiment, the main device 100 can be regarded as an application carrier of a chip.

[0032] The main device 100 mainly includes: an event triggering module 102, a timing module 104, a data transfer module 106, a data storage module 107, a data transceiver module 108, and a central processing unit 110.

[0033] Event Trigger Module 102 (ETB) is a programmable module adapted to different application scenarios. It listens for different event signals (such as data transfer completion signal, new event transmission request signal, etc.) from Data Transfer Module 106 and Data Transceiver Module 108, and uses them as the trigger source for starting / stopping the timing.

[0034] The timing module 104 is used to perform corresponding timing start / stop operations based on the timing start signal or timing stop signal from the event triggering module 102, thereby determining whether there is an abnormal situation of timeout in the processing of events inside the chip. In this embodiment, the timing threshold of the timing module 104 can be dynamically configured according to different business scenarios (such as random event interval threshold, single event processing time threshold) to realize timeout detection of different types of events.

[0035] The data transfer module 106 is responsible for performing high-speed data transfer operations (such as receiving data transfer and sending data transfer) between the data storage module 107 and the data transceiver module 108, avoiding the occupation of the central processing unit 110's resources. In some embodiments, the data transfer module 106 is, for example, a direct memory access controller (DMA), and the data storage module 107 is, for example, a static random access memory (SRAM).

[0036] The data transceiver module 108 can communicate with the external device 120 to perform serial / parallel data interaction with the external device 120 (such as a sensor, communication module, or other chip), receiving data from the external device 120 or sending data to the external device 120. In some embodiments, the data transceiver module 108 can support multiple communication protocols, including but not limited to UART / SPI / I2C.

[0037] The central processing unit 110 can be a CPU or an MCU, which is the core of system control and exception handling, and is responsible for global scheduling and fault recovery.

[0038] It should be noted that, in order to highlight the technical focus of this invention and avoid confusion caused by irrelevant information, Figure 1 Only the hardware configuration relevant to the technical solution of this application is shown. Those skilled in the art can arbitrarily adjust the hardware architecture of the main device 100 according to actual application needs, and this disclosure does not impose any restrictions on it.

[0039] Event timeout detection method Figure 2 This is a flowchart illustrating the event timeout detection method of an exemplary embodiment of the present disclosure, which mainly includes: Step 202: Based on the first event signal, send a timing start signal to the timing module through the event triggering module to trigger the timing module to start timing.

[0040] In some embodiments, the event triggering module 102 is a programmable module. The system can perform dynamic programming on the event triggering module 102 according to different timeout detection application scenarios to customize the generation logic and recognition type of the first event signal, thereby being compatible with timeout detection requirements in multiple scenarios and improving the versatility and scalability of this solution.

[0041] For example, in applications that perform timeout detection on random events within a chip, the first event signal can be specifically configured as a data reception completion signal output by the data transfer module 106. Under this configuration, the event triggering module 102 is set to monitor the status output bus of the data transfer module 106 in real time. Once it detects a data reception completion signal indicating the end of the data transfer task, the event triggering module 102 immediately generates and sends a timing start signal to the timing module 104. This mechanism ensures that the timeout timing starts the instant the data reception action is completed, achieving precise monitoring of the initiation time of the next random event.

[0042] For example, in applications that perform timeout detection for single events within a chip, the first event signal can be specifically configured as a data transmission request signal output by the data transceiver module 108. Under this configuration, the event triggering module 102 is set to monitor the status output bus of the data transceiver module 108 in real time. Once it captures a data transmission request signal representing the initiation of a single data transmission task, the event triggering module 102 immediately generates and sends a timing start signal to the timing module 104. This mechanism ensures that the timing start operation is synchronized with the initiation time of the single event, thereby enabling precise monitoring of the entire process from the issuance of the data transmission request to the completion of the data transmission.

[0043] In some embodiments, the first event signal may be a pulse signal or a REQ / ACK handshake signal.

[0044] Step 204: Determine whether a second event signal has been detected. If yes, proceed to step 210; otherwise, proceed to step 206.

[0045] In this embodiment, during the timing process (timing or countdown) executed by the timing module 104, the system synchronously starts dynamic monitoring of the second event signal to form a dual-event collaborative detection mechanism.

[0046] In some embodiments, the system can also perform dynamic programming on the event triggering module 102 according to different timeout detection application scenarios to customize the generation logic and recognition type of the second event signal, thereby being compatible with timeout detection requirements in multiple scenarios.

[0047] For example, in applications that perform timeout detection on random events within the chip, the second event signal can be specifically configured as a data reception request output by the data transceiver module 108. Under this configuration, the event triggering module 102 is set to monitor the status output bus of the data transceiver module 108 in real time during the timing process of the timing module 104. Once a data reception request indicative of the data reception task is detected, the event triggering module 102 immediately generates and sends a timing stop signal to the timing module 104. Through this dual-event collaborative detection mechanism of the first event signal (data reception completion signal) and the second event signal (data reception request signal), this embodiment achieves precise monitoring of the idle time between the end of the previous event and the generation of the next random event. This enables timely detection of system "freezing" or communication silence faults caused by missing random events, significantly improving the chip's fault self-healing capability and operational reliability in non-periodic business scenarios.

[0048] For example, in applications involving timeout detection of single events within a chip, the second event signal can be specifically configured as a data transmission completion signal output by the data transfer module 106. Under this configuration, the event triggering module 102 is set to monitor the status output bus of the data transfer module 106 in real time during the timing process of the timing module 104. Once a data transmission completion signal, representing the completion of data transfer, is detected, the event triggering module 102 immediately generates and sends a timing stop signal to the timing module 104. Through this dual-event collaborative detection mechanism of the first event signal (data transmission request signal) and the second event signal (data transmission completion signal), this embodiment achieves precise closed-loop monitoring of the entire processing time of a "single event," enabling the immediate detection of problems such as communication link blockage, hardware logic deadlock, or resource occupancy deadlock caused by single event processing timeouts, ensuring high-reliability operation of the chip under complex operating conditions.

[0049] In some embodiments, the second event signal may be a pulse signal or a REQ / ACK handshake signal.

[0050] Step 206: Determine whether the timing time of the timing module exceeds the timing threshold. If yes, proceed to step 208; otherwise, return to step 204.

[0051] After the timing module 104 is started, the system enters a preset effective time window, which is defined by a programmable timing threshold. For example, in an application scenario that performs timeout detection on random events inside the chip, the timing threshold of the timing module 104 is determined according to the preset interval period of the data transceiver module 108 acquiring two adjacent data reception requests (for example, the timing threshold can be set to 100ms); in an application scenario that performs timeout detection on a single event inside the chip, the timing threshold of the timing module 104 is determined according to the preset operation duration of a single data transfer operation.

[0052] In this embodiment, if the timing time of the timing module 104 has not yet reached the timing threshold, the process returns to step 204 to continue monitoring whether the second event signal is generated; if the timing time of the timing module 104 has reached the timing threshold but the second event signal has not been successfully captured and detected, step 208 is executed.

[0053] Step 208: The timing module generates a timeout interrupt signal.

[0054] In this embodiment, if the timing module 104 does not receive the timing stop signal from the event triggering module 102 when the timing time reaches the timing threshold (which can also be understood as the second event signal not being successfully detected), the timing module 104 outputs a timeout interrupt signal.

[0055] In some embodiments, the timing module 104 may output a timeout interrupt signal to the central processing unit 110 so that the central processing unit 110 can perform corresponding timeout exception handling.

[0056] Step 210: Send a timing stop signal to the timing module through the event triggering module to control the timing module to stop timing.

[0057] For example, if the generation of a second event signal is detected before the timing time of the timing module 104 reaches the timing threshold, the event triggering module 102 sends a timing stop signal to the timing module so that the timing module 104 stops timing immediately; at the same time, the timing module 104 resets the timing state (for example, resets the timing time to zero).

[0058] In summary, this embodiment utilizes a hardware detection link comprised of a programmable event triggering device and a timing module. This not only flexibly supports event timeout detection in various application scenarios but also ensures the accuracy of timeout detection and the stability of system operation. Furthermore, the timeout detection scheme in this embodiment eliminates the need for CPU polling operations, significantly reducing CPU load.

[0059] Chip Internal Random Event Timeout Detection Method Figure 3 , Figures 4A to 4BThis paper illustrates a specific implementation of the event timeout detection method of this disclosure in a random event timeout detection scenario within a chip. Specifically, Figure 3 A schematic diagram illustrating the processing flow of this implementation method is shown. Figure 4A and Figure 4B This is a schematic diagram of the hardware architecture of this implementation, used to illustrate the connection relationships and signal interaction paths between the internal functional modules.

[0060] like Figure 3 As shown, the event timeout detection method in this embodiment mainly includes: Step 302: After completing the data transfer operation of receiving data through the data transfer module, send a data reception completion signal to the event triggering module.

[0061] In this embodiment, the received data is acquired from an external device by the data transceiver module 108. The data transceiver module 108 may be a communication peripheral such as UART / SPI / I2C. After the data transceiver module 108 acquires the received data from the external device, it sends a data transfer signal to the data transfer module 106 to cause the data transfer module 106 to perform the corresponding data transfer operation. After the data transfer module 106 (e.g., DMA) completes the data transfer operation of the received data, it sends a data reception completion signal 402 to the event triggering module 102.

[0062] In some embodiments, the data reception completion signal 402 may be in pulse form or REQ+ACK handshake form.

[0063] Step 304: Send a timing start signal to the timing module through the event triggering module to trigger the timing module 104 to start timing.

[0064] Specifically, upon receiving the data reception completion signal 402, the event triggering module 102 sends a timing start signal 404 to the timing module 104. Upon receiving the timing start signal 404, the timing module 104 immediately starts the timing function, begins timing according to a preset timing threshold (e.g., 100ms), and simultaneously enables the timer interrupt function.

[0065] Step 306: Determine whether a data reception request signal output by the data transceiver module is detected. If yes, proceed to step 312; otherwise, proceed to step 308.

[0066] Specifically, during the timing process of the timing module, when the data transceiver module 108 receives the next data transmission from the external device, it generates a data reception request signal 406 (see reference). Figure 4A Conversely, if the data transceiver module 108 does not receive random data sent by the external device, it cannot generate a new data reception request signal 406 (see reference). Figure 4B ).

[0067] In some embodiments, the data receive request signal 406 may be in pulse form or REQ+ACK handshake form.

[0068] Step 308: Determine whether the timing time of the timing module exceeds the timing threshold. If yes, proceed to step 310; otherwise, return to step 306.

[0069] In this embodiment, the timing threshold of the timing module 104 is determined based on the preset interval period between two adjacent data reception requests obtained by the data transceiver module 108. For example, the timing threshold of the timing module 104 can be set to 100ms.

[0070] In this embodiment, if the timing module 104 has not reached the timing threshold, it returns to step 306 to continue monitoring whether the data receiving request signal 406 is generated; if the timing module 104 has reached the timing threshold but still has not successfully captured the data receiving request signal 406, it executes step 310.

[0071] Step 310: The timing module generates a timeout interrupt signal.

[0072] In this embodiment, if the timing module 104 does not detect the data reception request signal 406 when the timing time reaches the timing threshold (which can also be understood as not receiving the timing stop signal 408 issued by the event triggering module 102 within the timing threshold), then the timing module 104 generates and outputs a timeout interrupt signal 410.

[0073] In some embodiments, the timing module 104 may output a timeout interrupt signal 410 to the central processing unit 110 (see reference). Figure 4B ), so that the corresponding timeout exception handling can be performed through the central processing unit 110.

[0074] Step 312: Send a timing stop signal to the timing module through the event triggering module to trigger the timing module to stop timing, and send a data transfer signal to the data transfer module to trigger the data transfer module to perform data transfer operation.

[0075] For example, refer to Figure 4A After acquiring the data receiving request signal 406, the event triggering module 102 simultaneously selects the timing module 104 and the data transfer module 106 as the trigger receiving objects, and sends a timing stop signal 408 to the timing module 104 and a data transfer signal 409 to the data transfer module 106.

[0076] Upon receiving the timing stop signal 408, the timing module 104 immediately stops timing and resets the timing state (i.e., resets the timing time to zero) to prepare for the next round of timing.

[0077] After receiving the data transfer signal 409, the data transfer module 106 executes a new round of data transfer operations. After completing this round of data transfer operations, it can return to step 302, regenerate a new data reception completion signal 402, and thus start the next round of random event timeout detection process.

[0078] In summary, this embodiment achieves hardware-level timeout detection for random events within the chip through the coordinated operation of the event triggering module and the timing module. This mechanism constructs a hardware monitoring link completely independent of the central processing unit (CPU), ensuring that the CPU only intervenes when it is necessary to handle timeout exceptions, thereby significantly reducing CPU resource consumption and greatly improving the real-time performance and deterministic response of timeout detection.

[0079] Chip Internal Single Event Timeout Detection Method Figure 5 , Figures 6A to 6B This illustrates a specific implementation of the event timeout detection method of this disclosure in a single-event timeout detection scenario within a chip. Specifically, Figure 5 A schematic diagram illustrating the processing flow of this implementation method is shown. Figure 6A and Figure 6B This is a schematic diagram of the hardware architecture of this implementation, used to illustrate the connection relationships and signal interaction paths between the internal functional modules.

[0080] like Figure 5 As shown, the event timeout detection method in this embodiment mainly includes: Step 502: When sending data to an external device, the data transceiver module generates a data transmission request signal.

[0081] In some embodiments, the data transceiver module 108 may be a communication peripheral such as UART / SPI / I2C.

[0082] Specifically, when the data transceiver module 108 needs to send data to an external device, it generates a data transmission request signal 602.

[0083] In some embodiments, the data transmission request signal 602 may be in pulse form or REQ+ACK handshake form to adapt to the needs of different chip communication scenarios.

[0084] Step 504: Send a timing start signal to the timing module through the event triggering module to trigger the timing module 104 to start timing, and send a data transfer signal to the data transfer module to trigger the data transfer module to perform data transfer operation.

[0085] Specifically, after receiving the data transmission request signal 602, the event triggering module 102 simultaneously selects the timing module 104 and the data transfer module 106 as trigger receiving objects, sends a timing start signal 604 to the timing module 104, and sends a data transfer signal 605 to the data transfer module 106.

[0086] Upon receiving the timing start signal 604, the timing module 104 immediately starts the timing function, begins timing according to the preset timing threshold (e.g., 100ms), and simultaneously enables the timer interrupt function to prepare for timeout exception detection.

[0087] After receiving the data transfer signal 605, the data transfer module 106 (e.g., DMA) performs the corresponding data transfer operation according to the preset configuration parameters in the data transfer signal 605.

[0088] Step 506: Determine whether a data transmission completion signal output by the data transfer module has been detected. If yes, proceed to step 512; otherwise, proceed to step 508.

[0089] Specifically, during the timing process of the timing module, when the data transfer module 106 completes the data transfer operation, the trigger condition is met, that is, a data transmission completion signal 606 is generated (see reference). Figure 6A This signal is used to indicate the completion status of data transfer; conversely, if the data transfer module 106 has not completed the data transfer operation, a data transmission completion signal 606 cannot be generated (see reference). Figure 6B ).

[0090] In some embodiments, the data transmission completion signal 606 may be in pulse form or REQ+ACK handshake form.

[0091] Step 508: Determine whether the timing time of the timing module exceeds the timing threshold. If yes, proceed to step 510; otherwise, return to step 506.

[0092] In this embodiment, the timing threshold of the timing module 104 is determined based on the preset operation duration of a single data transfer operation.

[0093] In this embodiment, if the timing module 104 has not reached the timing threshold, the process returns to step 506 to continue monitoring whether the data transmission completion signal 606 is generated; if the timing module 104 has reached the timing threshold but the data transmission completion signal 606 is still not successfully detected, step 510 is executed.

[0094] Step 510: The timing module generates a timeout interrupt signal.

[0095] In this embodiment, if the timing module 104 does not detect the data transmission completion signal 606 when the timing time reaches the timing threshold (which can also be understood as not receiving the timing stop signal 608 issued by the event triggering module 102 within the timing threshold), then the timing module 104 generates and outputs a timeout interrupt signal 610.

[0096] In some embodiments, the timing module 104 may output a timeout interrupt signal 610 to the central processing unit 110 (see reference). Figure 6B ), so that the corresponding timeout exception handling can be performed through the central processing unit 110.

[0097] Step 512: Send a timing stop signal to the timing module through the event triggering module to trigger the timing module to stop timing.

[0098] For example, refer to Figure 6A After the event triggering module 102 acquires the data transmission completion signal 606, it can use the timing module 104 as the trigger receiving object and send the timing stop signal 608 to the timing module 104.

[0099] Upon receiving the timing stop signal 608, the timing module 104 immediately stops timing and resets the timing state (that is, resets the timing time to zero), thus ending the timeout detection process for this event.

[0100] In summary, this embodiment utilizes an event-triggered module to drive a timing module, forming a hardware protection mechanism for single-event timeouts. This mechanism constructs a detection link independent of CPU instruction flow through physical isolation, freeing the CPU from tedious status queries and allowing it to execute an exception recovery strategy only upon receiving a hardware interrupt signal. This effectively solves the pain points of poor real-time performance and high resource consumption in traditional solutions, significantly improving the overall operating efficiency and reliability of the system.

[0101] Event timeout detection device Figure 7 This is a simplified structural diagram of an event timeout detection device according to an exemplary embodiment of the present disclosure. As shown in the figure, the event timeout detection device 700 of this embodiment mainly includes a peripheral module 702, an event triggering module 704, a timing module 706, and a processor 708.

[0102] Peripheral module 702 is configured to generate a first event signal and a second event signal.

[0103] In some embodiments, peripheral module 702 includes a data transfer module and a data transceiver module.

[0104] In some embodiments, the first event signal is a data reception completion signal output by the data transfer module, and the second event signal is a data reception request signal output by the data transceiver module.

[0105] In some embodiments, the first event signal is a data transmission request signal output by the data transceiver module, and the second event signal is a data transmission completion signal output by the data transfer module.

[0106] The event triggering module 704 is connected to the peripheral module 702 and the timing module 706, and is configured to send a timing start signal to the timing module 706 based on a first event signal, and to send a timing stop signal to the timing module 706 based on a second event signal.

[0107] The timing module 706 is connected to the processor 708 and is configured to start the timing operation based on the timing start signal of the event trigger module 704 and stop the timing operation based on the timing stop signal of the event trigger module 704. If no timing stop signal is received within the timing threshold, a timeout interrupt signal is sent to the processor 708.

[0108] chip Another embodiment of this disclosure also provides a chip including an event timeout detection device 700 as described in the above embodiments, for performing timeout detection on single events or random events within the chip.

[0109] The chip disclosed herein integrates the event timeout detection device of the above embodiments, which enables hardware-level timeout detection of internal single events / random events, and is suitable for high-performance, low-power chip design scenarios such as embedded systems and system-on-a-chip (SoC).

[0110] electronic devices Reference Figure 8 The diagram shows a schematic representation of an electronic device according to an embodiment of the present disclosure. The specific embodiments of the present disclosure do not limit the specific implementation of the electronic device.

[0111] like Figure 8 As shown, the electronic device in this embodiment may include: a processor 802, a communications interface 804, a memory 806, and a communications bus 808.

[0112] The processor 802, communication interface 804, and memory 806 communicate with each other through the communication bus 808.

[0113] Communication interface 804 is used to communicate with other electronic devices or servers.

[0114] The processor 802 is used to execute program 810, specifically to execute the relevant steps in the above-described event timeout detection method embodiment.

[0115] Specifically, program 810 may include program code that includes computer operation instructions.

[0116] The processor 802 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0117] Memory 806 is used to store program 810. Memory 806 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0118] Program 810 may include multiple computer instructions. Specifically, program 810 may use multiple computer instructions to cause processor 802 to execute the operation corresponding to the event timeout detection method described in any of the foregoing multiple method embodiments.

[0119] The specific implementation of each step in program 810 can be found in the corresponding descriptions of the steps and modules in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0120] This disclosure also provides a computer storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in any of the foregoing method embodiments. The computer storage medium includes, but is not limited to, compact disc read-only memory (CD-ROM), random access memory (RAM), floppy disk, hard disk, or magneto-optical disk.

[0121] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to the event timeout detection method described in any of the above embodiments.

[0122] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.

[0123] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA)). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., Random Access Memory (RAM), Read-Only Memory (ROM), Flash Memory, etc.) capable of storing or receiving software or computer code, implementing the methods described herein when the software or computer code is accessed and executed by the computer, processor, or hardware. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for performing the methods shown herein.

[0124] Those skilled in the art will recognize that the modules and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments disclosed herein.

[0125] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.

Claims

1. An event timeout detection method, applied to a main device including an event triggering module and a timing module, the method comprising: Based on the first event signal, the event triggering module sends a timing start signal to the timing module to trigger the timing module to start timing; Detect the second event signal; If the second event signal is detected, the event triggering module sends a timing stop signal to the timing module to control the timing module to stop timing; If the timing module does not receive a timing stop signal within the timing threshold, it generates a timeout interrupt signal.

2. The method according to claim 1, wherein, The main device includes a data transfer module and a data transceiver module, and the main device communicates with external devices through the data transceiver module. The first event signal is the data reception completion signal output by the data transfer module; The second event signal is the data reception request signal output by the data transceiver module.

3. The method according to claim 2, wherein, The data reception completion signal and the data reception request signal are generated in the following manner: After completing the data transfer operation, the data transfer module generates a data reception completion signal; wherein the received data is obtained by the data transceiver module from the external device. During the timing process of the timing module, the data transceiver module generates the data receiving request signal based on the new data processing request obtained from the external device.

4. The method according to claim 3, wherein, The timing threshold of the timing module is determined based on the preset interval period for the data transceiver module to obtain two adjacent data reception requests.

5. The method according to claim 1, wherein, The main device includes a data transfer module and a data transceiver module, and the main device communicates with external devices through the data transceiver module. The first event signal is a data transmission request signal output by the data transceiver module; The second event signal is the data transmission completion signal output by the data transfer module.

6. The method according to claim 5, wherein, The data transmission request signal and the data transmission completion signal are generated in the following manner: When sending data to the external device, the data transceiver module generates the data sending request signal. During the timing process of the timing module, after the data transfer module completes the data transfer operation corresponding to the data transmission request, it generates the data transmission completion signal.

7. The method according to claim 6, wherein, The timing threshold of the timing module is determined based on the preset operation duration of a single data transfer operation.

8. The method according to claim 1, wherein, The first event signal and the second event signal are pulse signals or REQ / ACK handshake signals.

9. The method according to claim 1, further comprising: After the timing module receives the timing stop signal, it resets the timing state.

10. The method according to claim 1, wherein, The main device also includes a central processing unit; The method further includes: performing timeout exception handling based on the timeout interrupt signal by the central processing unit.

11. An event timeout detection device, comprising: Peripheral module, event triggering module, timing module, and processor; The peripheral module is configured to generate a first event signal and a second event signal; The event triggering module is connected to the peripheral module and the timing module, and is configured to send a timing start signal to the timing module based on the first event signal, and send a timing stop signal to the timing module based on the second event signal; The timing module is connected to the processor and is configured to start timing operation based on the timing start signal and stop timing operation based on the timing stop signal. If no timing stop signal is received within the timing threshold, a timeout interrupt signal is sent to the processor.

12. The event timeout detection device according to claim 11, wherein, The peripheral module includes a data transfer module and a data transceiver module; The first event signal is a data reception completion signal output by the data transfer module, and the second event signal is a data reception request signal output by the data transceiver module; or The first event signal is a data transmission request signal output by the data transceiver module, and the second event signal is a data transmission completion signal output by the data transfer module.

13. A chip, comprising the event timeout detection device as described in claim 11 or 12, for performing timeout detection on single events or random events within the chip via the event timeout detection device.

14. An electronic device, comprising: The processor, the communication interface, the memory, and the communication bus are provided, and the processor, the communication interface, and the memory communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform an operation corresponding to the event timeout detection method as described in any one of claims 1 to 10.

15. A computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the event timeout detection method as described in any one of claims 1 to 10.

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