A back contact crystalline silicon solar cell for space and a method for manufacturing the same

Abstract

This invention relates to a back-contact crystalline silicon solar cell for space applications and its fabrication method. The back-contact crystalline silicon solar cell comprises a p-type monocrystalline silicon substrate; the first crystalline silicon surface of the p-type monocrystalline silicon substrate is the light-facing side, and is sequentially disposed with a surface passivation layer, a first radiation-resistant layer with a silane-like structure, and a radiation-resistant hardening layer; the second crystalline silicon surface of the p-type monocrystalline silicon substrate is the back-facing side, and is sequentially disposed with a first intrinsic amorphous silicon passivation layer, a second radiation-resistant layer with a silane-like structure, a second intrinsic amorphous silicon passivation layer, a periodically spaced p-type hole collection layer and an n-type electron collection layer, a patterned transparent conductive oxide film, and a metal electrode. The back-contact crystalline silicon solar cell of this invention exhibits strong tolerance to extreme space environments, including resistance to ultraviolet radiation, high-energy electron and proton radiation, and high- and low-temperature cycling shock, and can provide low-cost, high-reliability solar cells for the energy systems of spacecraft, low-orbit communication satellites, and space stations.

Description

Technical Field

[0001] This invention belongs to the field of crystalline silicon solar cells, and specifically relates to a back-contact crystalline silicon solar cell for space use and its preparation method. Background Technology

[0002] In recent years, the rapid development of the commercial aerospace sector, especially the explosive growth of internet satellites and drones in space exploration and communication missions, has led to the development of solar cells, which are an important component of energy systems such as communication satellites, space stations, and spacecraft, and are the only way for energy systems to directly obtain energy.

[0003] Currently, approximately 80% of the energy supply for space satellites and space stations comes from III-V gallium arsenide multi-junction solar cells, which achieve photoelectric conversion efficiencies exceeding 30%. However, their high cost, ranging from approximately 200,000 to 1 million yuan per square meter, makes it difficult to meet the urgent needs of numerous satellite launch missions. SpaceX's 8,000 Starlink low-Earth orbit satellites utilize low-cost monocrystalline silicon PERC solar cells, with a spatial spectrum (AM0) conversion efficiency ≤21% (≤23.5%@AM1.5). Considering both cost reduction and multi-scenario applications, flexible crystalline silicon solar cells demonstrate superior advantages in terms of low cost and high efficiency. BC solar cells, fabricated by passivating the crystalline silicon surface with an amorphous silicon thin film and combining it with a back-side irregular interdigitated electrode configuration, have achieved a world record efficiency of 27.81%, representing the optimal cell structure for achieving high efficiency in monocrystalline silicon solar cells. However, compared to GaAs solar cells, crystalline silicon solar cells perform poorly in terms of radiation resistance. After being irradiated with high-energy particles, the conversion efficiency of p-type crystalline silicon cells with a thickness greater than 100 μm decreases by as much as about 35%. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a back-contact crystalline silicon solar cell for space use and a method for preparing the same, so as to obtain a high-performance, low-cost, radiation-resistant back-contact crystalline silicon solar cell for space use.

[0005] This invention provides a back-contact crystalline silicon solar cell for space use, comprising: a p-type monocrystalline silicon substrate; the first crystalline silicon surface of the p-type monocrystalline silicon substrate is the light-facing surface, on which a surface passivation layer, a first radiation-resistant layer with a silane-like structure, and a radiation-resistant reinforcement layer with optical anti-reflection function are sequentially disposed; the second crystalline silicon surface of the p-type monocrystalline silicon substrate is the back-facing surface, on which a first intrinsic amorphous silicon passivation layer, a second radiation-resistant layer with a silane-like structure, a second intrinsic amorphous silicon passivation layer, a periodically spaced p-type hole collection layer and an n-type electron collection layer, a patterned transparent conductive oxide thin film, and a metal electrode are sequentially disposed.

[0006] Preferably, the p-type single-crystal silicon substrate has a thickness of 20~100 μm; a resistivity of 5~50 Ω·cm; and an oxygen impurity concentration ≤5×10⁻⁶. 17 cm -3 Carbon impurity concentration ≤1×10 16 cm -3 Metal impurities ≤1×10 11 cm -3 Dislocation density ≤100cm -2 .

[0007] Preferably, the thickness of the surface passivation layer is 2~15 nm.

[0008] Preferably, the first and second radiation-resistant layers have a silane-like structure, simultaneously providing protection against ultraviolet radiation, high-energy electrons, and protons. The thickness is 2–15 nm, and the density is ≥2.35 g / cm³. 3 .

[0009] Furthermore, the first radiation-resistant layer contains a concentration of 1×10 17 ~ 1×10 21 cm -3 Gradient phosphorus doping helps improve carrier collection and radiation resistance efficiency.

[0010] Preferably, the thickness of the radiation-resistant reinforcement layer is 20~120 nm.

[0011] Preferably, the first intrinsic amorphous silicon passivation layer, the second radiation-resistant layer, and the second intrinsic amorphous silicon passivation layer form a sandwich structure, with the upper and lower intrinsic amorphous silicon passivation layers covering the second radiation-resistant layer.

[0012] Preferably, the thickness of the p-type hole collecting layer and the n-type electron collecting layer is 15~50 nm.

[0013] The present invention also provides a method for fabricating the above-mentioned back-contact crystalline silicon solar cell for space use, comprising the following steps:

[0014] S1. A clean p-type monocrystalline silicon substrate with a surface micro-light-trapping structure is formed by using a p-type monocrystalline silicon wafer as the substrate and pre-treating it.

[0015] S2. An amorphous silicon thin film is deposited on the first crystalline silicon surface of the pretreated p-type single-crystal silicon substrate to form a surface passivation layer; then a silicene-like thin film with a gradient concentration of phosphorus doped is deposited to form the first radiation-resistant layer SiEP; then an optical anti-reflection thin film is deposited to form a radiation-resistant hardening layer.

[0016] S3. A first intrinsic amorphous silicon passivation layer SP1, a silane-like thin film, and a second amorphous silicon passivation layer SP2 are sequentially deposited on the second crystalline silicon surface of a p-type single-crystal silicon substrate to form a sandwich structure SP1 / SiE / SP2 in which two intrinsic amorphous silicon passivation layers cover the second radiation-resistant layer SiE.

[0017] S4. A periodically spaced p-type hole collection layer and an n-type electron collection layer are prepared on an SP1 / SiE / SP2 sandwich structure.

[0018] S5. A transparent conductive oxide film is deposited on the p-type hole collection layer and the n-type electron collection layer, and then patterned.

[0019] S6. Prepare a metal electrode on a transparent conductive oxide film and perform a thermal curing treatment to obtain a battery cell;

[0020] S7. The solar cells are subjected to light injection treatment to obtain radiation-resistant back-contact crystalline silicon solar cells.

[0021] Preferably, the preprocessing in step S1 includes:

[0022] 1) Perform chemical polishing and cleaning on p-type monocrystalline silicon wafers to remove the slicing damage layer and surface contaminants;

[0023] 2) Place the p-type single crystal silicon wafer into a high-temperature diffusion furnace to perform thermal gettering to improve the quality of the crystal silicon wafer, reduce the content of metal impurities and defects, and obtain a diffused gettering silicon wafer;

[0024] 3) The surface oxide layer and diffusion layer of the diffusion-getter silicon wafer are removed by wet etching, and a surface light-trapping structure is made. Then, standard silicon wafer cleaning is performed to form a clean p-type single crystal silicon substrate with a surface micro-light-trapping structure.

[0025] Preferably, the deposition method described in steps S2 and S3 is chemical vapor deposition.

[0026] Preferably, the preparation method in step S4 specifically includes: depositing a p-type silicon thin film for collecting hole carriers; after removal, removing part of the p-type silicon thin film using a laser grooving method, depositing an n-type silicon thin film for collecting electrons again, and removing the n-type silicon thin film deposited on the p-type silicon thin film using a laser grooving method, so that a periodically arranged p-type hole collecting layer and n-type electron collecting layer are formed on the surface of the second crystalline silicon.

[0027] More preferably, the p-type silicon thin film and the n-type silicon thin film are doped with boron and phosphorus respectively, with a concentration of 1% to 10%.

[0028] Preferably, the deposition method described in step S5 is physical vapor deposition.

[0029] Preferably, the patterning process in step S5 specifically involves using a laser grooving method to remove excess thin film connecting the p-type hole collection layer and the n-type electron collection layer, thereby laterally isolating carrier transport between the p-type and n-type silicon thin films.

[0030] Preferably, the preparation method in step S6 is screen printing or electroplating.

[0031] This invention constructs a shield to protect the active layer of crystalline silicon by using a first radiation-resistant layer SiEP with a gradient phosphorus-doped silylene-like structure on the surface of the first crystalline silicon and a second radiation-resistant layer SiE with a passivation layer and a silylene-like structure on the surface of the second crystalline silicon, forming an SP1 / SiE / SP2 sandwich structure. This mitigates the increase in defect state density after irradiation and significantly reduces the degradation rate of the conversion efficiency of the back-contact crystalline silicon solar cell.

[0032] Beneficial effects

[0033] The back-contact crystalline silicon solar cell of this invention has strong tolerance to extreme space environments, including resistance to ultraviolet radiation, high-energy electron and proton irradiation, and high and low temperature cycling shock, and can provide low-cost and high-reliability solar cells for the energy systems of spacecraft, low-orbit communication satellites, and space stations. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the space-use back-contact crystalline silicon solar cell of the present invention.

[0035] Figure 2 This is the Raman spectrum of the silicene-like thin film prepared in Example 1 of this invention.

[0036] Reference numerals: 101-p-type monocrystalline silicon substrate, 102-surface passivation layer, 103-first radiation-resistant layer, 104-radiation-resistant reinforcement layer, 105-first intrinsic amorphous silicon passivation layer, 106-second radiation-resistant layer, 107-second intrinsic amorphous silicon passivation layer, 108-p-type hole collection layer, 109-n-type electron collection layer, 110-transparent conductive oxide thin film, 111-metal electrode. Detailed Implementation

[0037] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the designs related to the present invention and are not drawn according to the actual number, shape and size in the actual implementation. In the actual implementation, the shape, number and proportion of each membrane layer can be arbitrarily changed, and the membrane layer layout may also be more complex.

[0039] like Figure 1 As shown, the radiation-resistant back-contact crystalline silicon solar cell structure designed in this invention includes: a p-type monocrystalline silicon substrate 101; a surface passivation layer 102; a first radiation-resistant layer 103 with a silane-like structure; and a radiation-resistant reinforcement layer 104 with optical anti-reflection properties. The second crystalline silicon surface of the p-type monocrystalline silicon substrate 101 is a backlight surface, and is sequentially provided with a first intrinsic amorphous silicon passivation layer 105, a second radiation-resistant layer 106 with a silane-like structure, a second intrinsic amorphous silicon passivation layer 107, a p-type hole collection layer 108 and an n-type electron collection layer 109 arranged in a periodic pattern. A dense transparent conductive oxide film 110 is deposited on the surface of both the p-type hole collection layer 108 and the n-type electron collection layer 109. The transparent conductive oxide film 110 has a metal electrode 111 on its surface for collecting electrons and holes.

[0040] Phosphorus is gradually added from the surface passivation layer 102 outwards within the first radiation-resistant layer 103, which helps to form the silicene microstructure.

[0041] A sandwich structure is formed on the second crystalline silicon surface, with an intrinsic amorphous surface passivation layer covering the second radiation-resistant layer. This structure helps to reduce the structural damage to the silicene-like thin film and the crystalline silicon interface caused by laser during the fabrication of patterned p and n-type contact layers.

[0042] The core radiation-resistant silane-like thin film of this invention is fabricated using plasma-enhanced chemical vapor deposition (PECVD) equipment. Specifically, a silane-like radiation-resistant layer is grown on the surface of the intrinsic passivation layer using a plasma-enhanced chemical vapor deposition process.

[0043] As an example, chemical vapor deposition processes are performed at temperatures ranging from 200 to 400°C, with reactant gases including SiH4, H2, and PH3, and using RF or VHF power supplies with feed densities of 50 to 200 mW / cm². 2 The power.

[0044] By adjusting other deposition parameters, such as deposition pressure and reactant gas ratio, thin films with silicene-like microstructures can be grown.

[0045] By adjusting the phosphorus doping element, the growth of silylene structures on the surface passivation layer and the realization of field effects can be promoted.

[0046] Example 1

[0047] This embodiment provides a method such as Figure 1 The space-use back-contact crystalline silicon solar cell shown is fabricated using the following steps:

[0048] S1. Preparation of p-type single-crystal silicon substrate with surface micro-light-trapping structure

[0049] 1) A p-type single-crystal silicon wafer with a thickness of 60 μm and a resistivity of 30 Ω·cm was used as the substrate. Chemical polishing and cleaning were performed to remove the slicing damage layer and surface contaminants.

[0050] 2) The polished and cleaned p-type single crystal silicon wafers are placed in a high-temperature diffusion furnace and thermally gettered at 600~900 ℃ to reduce the influence of metal impurity content and obtain diffusion-gettered silicon wafers.

[0051] 3) Using HF solution and alkaline solution, the surface oxide layer and diffusion layer of the diffusion-getter silicon wafer are removed, and a surface light-trapping structure is fabricated. Then, the silicon wafer is cleaned according to RCA standards to obtain a clean p-type single crystal silicon wafer substrate with a surface micro-light-trapping structure.

[0052] S2. The texturized and cleaned p-type single-crystal silicon wafer substrate is introduced into a vacuum chemical vapor deposition equipment, and an amorphous silicon thin film is deposited on the surface of the first crystalline silicon at a substrate temperature of 170~200 ℃ to form a surface passivation layer 102.

[0053] Then, it was moved into another vacuum chamber for the deposition of a silicene-like thin film at a substrate temperature of 300 °C, with a feed power of 100 mW / cm². 2 The deposition pressure is 100 Pa, the ratio of silane to hydrogen is 1:10, and the ratio of phosphine to silane gradually increases, ranging from 1:1000 to 1:100, forming a first radiation-resistant layer 103 with a gradient concentration of phosphorus doped.

[0054] Subsequently, an oxygen-doped silicon nitride thin film is deposited to form a radiation-resistant hardening layer 104; as the thickness increases, the refractive index decreases in a gradient manner, and the thin film has both radiation-resistant hardening effect and optical anti-reflection effect;

[0055] S3. Prepare a sandwich structure SP1 / SiE / SP2 on the surface of the second crystalline silicon, consisting of two intrinsic amorphous silicon passivation layers covering the second radiation-resistant layer 106, including: depositing a first intrinsic amorphous silicon passivation layer 105 (SP1), a silane-like thin film (without phosphorus doping), and a second intrinsic amorphous silicon passivation layer 107 (SP2), wherein the deposition method of the silane-like thin film is the same as in step S2, but without adding phosphine;

[0056] S4. Periodically arranged p-type and n-type silicon thin films are prepared on the SP1 / SiE / SP2 sandwich structure. The deposition conditions are the same as those for the passivation layer, but boron doping and phosphorus doping are added respectively, with a concentration of 1% to 10%. This includes: depositing a p-type boron-doped silicon thin film to collect hole carriers; after removal, a portion of the p-type boron-doped silicon thin film is removed using a low-damage laser grooving method, and then the film is reintroduced into a vacuum chamber to deposit an n-type phosphorus-doped silicon thin film to collect electrons. The n-type phosphorus-doped silicon thin film deposited on the p-type boron-doped silicon thin film is removed using a laser grooving method, so that a periodically spaced p-type hole collection layer 108 and an n-type electron collection layer 109 are formed on the surface of the second silicon crystal.

[0057] S5. The passivated silicon wafer is introduced into the PVD equipment, and a transparent conductive oxide film 110 (TCO) with a dense structure is deposited on the p-type hole collection layer and the n-type electron collection layer. The TCO film connecting the p-type boron-doped silicon film and the n-type phosphorus-doped silicon film is removed again by laser grooving to laterally isolate the carrier transport between the p-type and n-type silicon films.

[0058] S6. Using screen printing or electroplating equipment, metal electrodes 111 are prepared to contact the TCO film on the p-type boron-doped silicon thin film and the n-type phosphorus-doped silicon thin film, respectively, for collecting holes and electrons, and then subjected to thermal curing treatment to obtain a battery cell;

[0059] S7. The solar cells are subjected to light injection treatment at 180 °C for 2 min using a light injection device to complete the fabrication of a space-use back-contact crystalline silicon solar cell.

[0060] As an example, phosphorus-doped silicene-like films (n-quasi-SiE:P, or SiEP for short) with a thickness of 2–15 nm and a density ≥2.35 g·cm³ were deposited by PECVD chemical vapor deposition. -3 ,like Figure 2 As shown, in the Raman spectrum at 570 cm⁻¹ -1 The film exhibits typical characteristic peaks of silicene microstructure, indicating that the Si-Si bond strength of the silicene microstructure is relatively strong and not easily broken; moreover, the intensity of the characteristic peaks is stronger than that of i-type silicene films (intrinsic, i-quasi-SiE) and p-type silicene films (boron-doped, p-quasi-SiE:B).

Claims

1. A space-use back-contact crystalline silicon solar cell, characterized in that, The back-contact crystalline silicon solar cell includes: a p-type monocrystalline silicon substrate; the first crystalline silicon surface of the p-type monocrystalline silicon substrate is the light-facing surface, and is sequentially provided with a surface passivation layer, a first radiation-resistant layer with a silane-like structure, and a radiation-resistant reinforcement layer; the second crystalline silicon surface of the p-type monocrystalline silicon substrate is the back-facing surface, and is sequentially provided with a first intrinsic amorphous silicon passivation layer, a second radiation-resistant layer with a silane-like structure, a second intrinsic amorphous silicon passivation layer, a periodically spaced p-type hole collection layer and an n-type electron collection layer, a patterned transparent conductive oxide thin film, and a metal electrode.

2. The space-use back-contact crystalline silicon solar cell according to claim 1, characterized in that, The p-type single-crystal silicon substrate has a thickness of 20~100 μm; a resistivity of 5~50 Ω·cm; and an oxygen impurity concentration ≤5×10⁻⁶. 17 cm -3 Carbon impurity concentration ≤1×10 16 cm -3 Metal impurities ≤1×10 11 cm -3 Dislocation density ≤100 cm -2 .

3. The space-use back-contact crystalline silicon solar cell according to claim 1, characterized in that, The thickness of the surface passivation layer is 2~15 nm; the thickness of the radiation-resistant hardening layer is 20~120 nm; and the thickness of the p-type hole collection layer and the n-type electron collection layer is 15~50 nm.

4. The space-use back-contact crystalline silicon solar cell according to claim 1, characterized in that, The thickness of the first and second radiation-resistant layers is 2~15 nm, and the density is ≥2.35 g / cm³. 3 .

5. The space-use back-contact crystalline silicon solar cell according to claim 4, characterized in that, The first radiation-resistant layer contains a concentration of 1×10 17 ~ 1×10 21 cm -3 Gradient phosphorus doping.

6. A method for fabricating a space-use back-contact crystalline silicon solar cell as described in claim 1, comprising the following steps: S1. Pre-treat the p-type monocrystalline silicon wafer to form a p-type monocrystalline silicon substrate with a surface micro-light-trapping structure; S2. An amorphous silicon thin film is deposited on the first crystalline silicon surface of the pretreated p-type single-crystal silicon substrate to form a surface passivation layer; subsequently, a silicene-like thin film with a gradient concentration of phosphorus doping is deposited to form the first radiation-resistant layer SiEP. Then, an optical antireflective film is deposited to form a radiation-resistant hardening layer; S3. A first intrinsic amorphous silicon passivation layer SP1, a silane-like thin film, and a second amorphous silicon passivation layer SP2 are sequentially deposited on the second crystalline silicon surface of a p-type single-crystal silicon substrate to form a sandwich structure SP1 / SiE / SP2 in which two intrinsic amorphous silicon passivation layers cover the second radiation-resistant layer SiE. S4. A periodically spaced p-type hole collection layer and an n-type electron collection layer are prepared on an SP1 / SiE / SP2 sandwich structure. S5. A transparent conductive oxide thin film is deposited on the p-type hole collection layer and the n-type electron collection layer, and then patterned. S6. Prepare a metal electrode on a transparent conductive oxide film and perform a thermosetting treatment to obtain a battery cell; S7. The solar cells are subjected to light injection treatment to obtain radiation-resistant back-contact crystalline silicon solar cells.

7. The preparation method according to claim 6, characterized in that, The preprocessing in step S1 includes: 1) Perform chemical polishing and cleaning on p-type monocrystalline silicon wafers to remove the slicing damage layer and surface contaminants; 2) Place the p-type single crystal silicon wafer into a high-temperature diffusion furnace to perform thermal gettering to improve the quality of the crystal silicon wafer, reduce the content of metal impurities and defects, and obtain a diffused gettering silicon wafer; 3) The surface oxide layer and diffusion layer of the diffusion-getter silicon wafer are removed by wet etching, and a surface light-trapping structure is made. Then, standard silicon wafer cleaning is performed to form a clean p-type single crystal silicon substrate with a surface micro-light-trapping structure.

8. The preparation method according to claim 6, characterized in that, The deposition method described in steps S2 and S3 is chemical vapor deposition; the deposition method described in step S5 is physical vapor deposition.

9. The preparation method according to claim 6, characterized in that, The preparation method described in step S4 specifically includes: depositing a p-type silicon thin film for collecting hole carriers; after removal, removing part of the p-type silicon thin film using a laser grooving method, depositing an n-type silicon thin film for collecting electrons again, and removing the n-type silicon thin film deposited on the p-type silicon thin film using a laser grooving method, so that a periodically spaced p-type hole collecting layer and an n-type electron collecting layer are formed on the surface of the second crystalline silicon.

10. The preparation method according to claim 6, characterized in that, The preparation method described in step S6 is screen printing or electroplating.

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