Power grid distribution in extended reality (XR) devices

Abstract

An apparatus includes a plurality of core devices, each configured to operate at a plurality of voltage levels. The apparatus also includes a power management integrated circuit (PMIC) including a plurality of power supplies, each power supply corresponding to one of the voltage levels. A first power supply, corresponding to a first voltage level, is selectively coupled to a first core device configured to operate at the first voltage level. A second power supply, corresponding to a second voltage level, is selectively coupled to a first core device configured to operate at the second voltage level.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 545,813, filed December 19, 2023, entitled “POWER GRID ALLOCATION INEXTENDED REALITY (XR) DEVICES”, the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to power control, and more specifically to a dynamic power grid for power-optimized and area-constrained wearable devices, such as augmented reality (AR) glasses. Background Technology

[0004] Extended Reality (XR) is a family of immersive technologies that encompass Augmented Reality (AR) and Virtual Reality (VR), which combine real and virtual environments. AR merges the real world with virtual objects to support authentic, intelligent, and personalized experiences. Regular AR applications provide a real-time view of the real-world environment, whose elements can be enhanced by computer-generated sensory input such as video, sound, graphics, or GPS data. With such applications, the view of reality can be modified by computing devices to enhance the user's perception of reality and provide more information about the user's environment. Virtual Reality (VR) simulates the physical presence in the real or imagined world and enables users to interact with that world. Realizing XR requires the next level of artificial intelligence (AI) and connectivity within the thermal and power envelopes of wearable devices such as glasses. Summary of the Invention

[0005] In various aspects of this disclosure, an apparatus includes a plurality of core devices, each core device configured to operate at a plurality of voltage levels. The apparatus also includes a power management integrated circuit (PMIC) having a plurality of power supplies, each power supply corresponding to one of the voltage levels. A first power supply, corresponding to a first voltage level, is selectively coupled to a first core device configured to operate at the first voltage level. A second power supply, corresponding to a second voltage level, is selectively coupled to the first core device configured to operate at the second voltage level.

[0006] Other aspects of this disclosure relate to a method. The method includes receiving a current specification for a first core device, a voltage specification for the first core device, a first output voltage of a first power supply, a second output voltage of a second power supply, and current ratings of the first and second power supplies as inputs. The method further includes controlling a switch based on the inputs, the switch selectively coupling the first core device to the first and second power supplies. The method also includes controlling the first and second output voltages based on the inputs.

[0007] Several other aspects of this disclosure relate to a method. The method includes performing a task on a device having a shared power supply for multiple power rails. The method further includes determining whether current load information for the task is stored in a database. The method further includes, in response to determining that the current load information for the task is not stored in the database, detecting a task-specific peak current level for each power rail in the power rails, storing the task-specific peak current level for each power rail in the power rails as current load information in the database, and assigning the shared power supply to a default power rail. Furthermore, the method includes, in response to determining that the current load information for the task is stored in the database, determining whether any power rail in the power rails exceeds a limit of the shared power supply used for the task. The method includes, in response to at least one power rail in the power rails exceeding the limit of the shared power supply, allocating the shared power supply to one power rail in the power rails based on machine learning.

[0008] This has provided a broad overview of the features and technical advantages of this disclosure in order to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for implementing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0009] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description, the drawings, and the claims.

[0010] Figure 1 An example implementation of a System-on-Chip (SoC) is illustrated.

[0011] Figure 2 This is a block diagram illustrating example content generation and decoding systems for implementing extended reality (XR) or virtual reality (VR) applications according to various aspects of this disclosure.

[0012] Figure 3 This is a block diagram illustrating various aspects of augmented reality or virtual reality subsystems according to this disclosure.

[0013] Figure 4 This is a diagram illustrating the location of components in a wearable device having the shape and size of eyeglasses according to various aspects of this disclosure.

[0014] Figure 5A , Figure 5B and Figure 5C These are illustrations of neural networks according to various aspects of this disclosure.

[0015] Figure 5D This is a diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0016] Figure 6 This is a block diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0017] Figure 7 This is a block diagram illustrating exemplary software architectures that enable modularization of artificial intelligence (AI) functions according to various aspects of this disclosure.

[0018] Figure 8 This is an illustration of an augmented reality printed circuit board (PCB) according to various aspects of this disclosure.

[0019] Figure 9 This is an illustration illustrating the limitations of augmented reality printed circuit boards (PCBs) according to various aspects of this disclosure.

[0020] Figure 10 This is a diagram illustrating an augmented reality power grid.

[0021] Figure 11A This is a diagram illustrating an augmented reality power grid with additional phases.

[0022] Figure 11B This is a diagram illustrating a dynamic power grid according to various aspects of this disclosure.

[0023] Figure 12A This is a diagram illustrating an augmented reality power grid with additional phases.

[0024] Figure 12B This is a diagram illustrating a dynamic power grid with a power multiplexer according to various aspects of this disclosure.

[0025] Figure 13 This is a diagram illustrating a dynamic power grid with a power multiplexer having machine learning control according to various aspects of this disclosure.

[0026] Figure 14 This is a diagram illustrating various aspects of a dynamic power grid for switching between power sources under overload conditions, according to the present disclosure.

[0027] Figure 15 This is a diagram illustrating various aspects of a dynamic power grid for switching between power sources to reduce power consumption, according to the present disclosure.

[0028] Figure 16 This is a diagram illustrating various aspects of a dynamic power grid for switching between power sources at a power failure core, according to the present disclosure.

[0029] Figure 17 This is a diagram illustrating various aspects of a dynamic power grid for switching between power sources to reduce power consumption, according to the present disclosure.

[0030] Figure 18 This is a diagram illustrating a conventional power grid design.

[0031] Figure 19 This is a diagram illustrating a conventional power scheme with limit management.

[0032] Figure 20 This is a table illustrating voltage level thresholds.

[0033] Figure 21 This is a diagram illustrating a first improvement to a power grid according to various aspects of this disclosure.

[0034] Figure 22 This is a diagram illustrating a second improved power grid according to various aspects of this disclosure.

[0035] Figure 23 This is a table illustrating various improvements to the use of the power grid based on this disclosure.

[0036] Figure 24 This is a diagram illustrating various aspects of a smart power switch according to this disclosure.

[0037] Figure 25 This is a diagram illustrating various aspects of a smart power switch grid according to this disclosure.

[0038] Figure 26 This is a circuit diagram illustrating a printed circuit board (PCB) having a power controller within a main power management integrated circuit (PMIC) according to various aspects of this disclosure.

[0039] Figure 27This is a circuit diagram illustrating a PCB with a power controller external to a PMIC according to various aspects of this disclosure.

[0040] Figure 28 This is a flowchart illustrating example processes for a power distribution pipeline according to various aspects of this disclosure.

[0041] Figure 29 This is a flowchart illustrating various aspects of dynamic power control methods according to this disclosure. Detailed Implementation

[0042] Various aspects of the systems, apparatuses, computer program products, and methods will be described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the disclosed systems, apparatuses, computer program products, and methods, whether implemented independently of or in combination with other aspects of this disclosure. For example, an apparatus or method may be implemented using any number of the aspects set forth. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using additional structures, functionalities, or structures and functionalities that complement or supplement the various aspects of the set forth disclosure. Any aspect of the disclosure may be embodied by one or more elements of the claims.

[0043] While various aspects are described, many variations and substitutions of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of the aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or objective. Rather, the aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the description below. The detailed description and drawings are merely illustrative and not limiting of this disclosure, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0044] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in detail and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0045] For example, an element, any part of an element, or any combination of elements can be implemented as a “processing system” including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors in the processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc. The term “application” can refer to software. As described, one or more technologies can refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application may be stored on memory (e.g., on-chip memory of a processor, system memory, or any other memory). The described hardware, such as a processor, may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more of the described technologies. As an example, the hardware may access and execute code accessed from memory to perform one or more of the described technologies. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0046] Therefore, in one or more of the described examples, the described functionality can be implemented using hardware, software, or any combination thereof. If implemented in software, the functionality can be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium accessible to a computer. By way of example, and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic disk storage devices, other magnetic storage devices, combinations of computer-readable media of the foregoing types, or any other medium capable of storing computer-executable code in the form of computer-accessible instructions or data structures.

[0047] Generally, this invention describes techniques for integrating subsystems or modules located on physically separate printed circuit boards (PCBs). For example, augmented reality or virtual reality (AR / VR) devices may have modules that are physically far apart. However, this disclosure is equally applicable to any type of system having spaced-apart but electrically connected modules or PCBs (e.g., using flexible cables, flexible PCBs, coaxial cables, rigid PCBs, etc.). In some aspects, these solutions integrate at least one slave subsystem with the master subsystem by implementing all control and status monitoring functions between at least one slave subsystem and the master subsystem. For example, certain bidirectional functions may be implemented between the master and slave subsystems, such as power-on triggers, reset triggers, power-off triggers, fault propagation, and fail-safe reset triggers.

[0048] As used, the term "decoder" may generally refer to encoders and / or decoders. For example, a reference to "content decoder" may include a reference to a content encoder and / or content decoder. Similarly, as used, the term "decode" may generally refer to encoding and / or decoding. As used, the terms "encode" and "compress" may be used interchangeably. Similarly, the terms "decode" and "decompress" may be used interchangeably.

[0049] As used, instances of the term "content" may refer to the terms "video," "graphic content," "image," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. For example, a reference to "content decoder" may include a reference to "video decoder," "graphic content decoder," or "image decoder," and a reference to "video decoder," "graphic content decoder," or "image decoder" may include a reference to "content decoder." As another example, a reference to a processing unit providing content to a content decoder may include a reference to that processing unit providing graphical content to a video encoder. In some examples, the term "graphic content" may refer to content produced by one or more processes in a graphics processing pipeline. In some examples, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, the term "graphic content" may refer to content produced by a graphics processing unit.

[0050] Instances of the term "content" can refer to graphical content or display content. In some examples, the term "graphical content" can refer to content generated by a processing unit configured to perform graphics processing. For example, the term "graphical content" can refer to content generated by one or more processes in a graphics processing pipeline. In some examples, the term "graphical content" can refer to content generated by a graphics processing unit. In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. In some examples, the term "display content" can refer to content generated by a display processing unit. Graphical content can be processed to become display content. For example, a graphics processing unit can output graphical content (such as frames) to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques on that display processing unit to generate display content. For example, a display processing unit can be configured to perform compositing on one or more rendering layers to generate frames. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers into a single frame. The display processing unit can be configured to perform scaling (e.g., zooming in or out) on a frame. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form the frame (e.g., the frame comprises two or more layers, and the frame comprising two or more layers can be subsequently blended).

[0051] As referenced, a first component (e.g., a processing unit) may provide content, such as graphical content, to a second component (e.g., a content decoder). In some examples, the first component may provide content to the second component by storing the content in memory accessible to the second component. In such examples, the second component may be configured to read the content stored in memory by the first component. In other examples, the first component may provide content to the second component without any intermediate components (e.g., no memory or another component). In such examples, the first component may be described as providing content directly to the second component. For example, the first component may output content to the second component, and the second component may be configured to store the content received from the first component in memory such as a buffer.

[0052] For mobile devices such as mobile phones, a single printed circuit board (PCB) can support multiple components, including a CPU, GPU, DSP, etc. For augmented reality (AR) or virtual reality (VR) devices, due to the form factor of AR or VR devices, these components can reside on different PCBs. For example, an AR or VR device can be in the form of glasses. In an example implementation, the main SoC (also called the main processor) and the main power management integrated circuit (PMIC) can reside on a first PCB in one arm of the glasses. The camera and sensor coprocessor, along with its associated PMIC, can reside on a second PCB near the bridge of the glasses. The connectivity processor and its associated PMIC can reside on a third PCB in the other arm of the glasses.

[0053] To achieve wider market adoption, augmented reality (AR) glasses should be lightweight and have a small form factor (e.g., a sleek form factor). In fact, original equipment manufacturers (OEMs) can specify maximum size limits to achieve a sleek form factor. However, a small form factor limits the number of chips, chip package size, battery size, and battery capacity. The printed circuit board (PCB) inside the arm of the AR glasses determines the overall product size. The package size of the main system-on-chip (SoC) and power management integrated circuit (PMIC) determines the overall PCB size on each arm of the AR glasses. To achieve size targets, only one PMIC with associated passive devices can be placed on the PCB due to Y-size limits. Although primarily AR glasses have been discussed, this disclosure applies to any type of wearable or audible device, such as smartwatches, fitness trackers, or earbuds.

[0054] For next-generation augmented reality chips, SoC feature sets are increasing. However, PCB size specifications are very tight. In fact, SoC package sizes will decrease over time, forcing PMIC sizes to shrink. As feature sets increase, the power consumption of each core device and its associated power rails will increase accordingly, which in turn requires additional power supplies or regulators. To accommodate more regulators, either multiple PMICs must be added or a larger single PMIC must be introduced. Both solutions increase the Y-dimensionality of the PCB, which is detrimental to achieving smooth glass.

[0055] Another solution is to throttle the core device to limit peak current, rather than adding a PMIC. However, this solution negatively impacts the user experience. Lower power consumption would improve the user experience by allowing for a smaller battery capacity, resulting in a smaller size. Another option for achieving lower power consumption with a small battery is to split each rail into multiple rails, which again increases regulator requirements and PCB area. The goal is to deliver the specified peak current at low power for full performance without increasing the number of regulators and PCB area.

[0056] According to various aspects of this disclosure, during peak current loads on a particular rail or from a particular core device, current capacity from underutilized power sources is used instead of adding more power. In some aspects, power distribution is achieved using multiplexers (MUX). By using a power MUX, the load can draw current from different regulators based on which regulator can supply the full current specified by the load.

[0057] According to various aspects of this disclosure, machine learning facilitates MUX switching. Since there may be many regulators underloaded at any point, the machine learning module determines which regulator is best suited to deliver current at a given point in time. The machine learning module can accept multiple inputs and select the regulator used to deliver a specified peak current.

[0058] According to various aspects of this disclosure, full performance is achieved by reducing the number of power supply phases. In existing systems, when peak current exceeds the power supply limit, either additional power is provided or performance is throttled to keep the peak current within the limit. Instead of throttling the core, the technique of this disclosure intelligently powers the core to achieve full performance without the need for additional regulators. Using the proposed technique, unused power from various power sources will be used to power the core to achieve full performance.

[0059] According to another aspect of this disclosure, the improved power grid reduces the total number of power sources. The improved power grid includes one or more power sources and one or more core devices, each power source selectively coupled to each core device. Each power source operates at a defined voltage level, such that the one or more power sources can supply current to the one or more core devices according to the voltage and current requirements of the core devices. Therefore, when compared to a conventional power grid, the improved power grid allows for a reduction in the number of power sources.

[0060] According to various aspects of this disclosure, a power model is employed as part of machine learning for controlling MUX switching. In a shared-rail system, each core can specify a different operating voltage. If a core on a power rail specifies a higher voltage, all cores on the same rail will operate at a higher voltage, thus affecting power consumption. If a core moves from a higher voltage supply to a lower voltage supply, improved power efficiency can be achieved. Based on the voltage requirements of each core, the core power supply can be moved to an underloaded supply or a supply with a lower voltage to reduce the impact of days used (DoU). Various aspects of this disclosure use a power MUX to dynamically switch cores to a lower voltage supply to achieve lower power consumption.

[0061] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques for dynamic power management can be used in streamlined form factor AR and VR designs, or any wearable or audio device design. Advantages of the proposed solution include the elimination of additional power phases for powering cores with higher feature sets. Therefore, the PCB area does not increase even with increased capacity. Furthermore, full core performance is achieved without using extreme management or adding additional phases, thus preventing negative impacts on the user experience. Additionally, the power improvements enable smaller batteries.

[0062] Figure 1 An example implementation of a System-on-Chip (SoC) 100 on a single printed circuit board (PCB) is illustrated. The host SoC 100 includes processing blocks tailored for specific functions, such as a connectivity block 110. The connectivity block 110 may include fifth-generation (5G) New Radio (NR) connectivity, fourth-generation Long Term Evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, and Bluetooth. ® Connectivity, Secure Digital (SD) connectivity, etc.

[0063] In this configuration, the SoC 100 includes various processing units that support multi-threaded operation. Figure 1 As shown in the configuration, SoC 100 includes a multi-core central processing unit (CPU) 102, a graphics processing unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processing unit (NPU) 108. SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120, and a memory 118, which may include a global positioning system. The multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, extended reality (XR) games, artificial intelligence networks, etc. Each processor core of the multi-core CPU 102 can be a Reduced Instruction Set Computing (RISC) machine (e.g., a RISC-V (RISC 5) machine, an Advanced RISC machine (ARM), a microprocessor, or some other type of processor). The NPU 108 may be based on the ARM instruction set.

[0064] Figure 2This is a block diagram illustrating an example Extended Reality (XR) or Virtual Reality (VR) system 200 configured to implement Extended Reality (XR) or Virtual Reality (VR) applications according to various aspects of this disclosure. System 200 includes a source device 202 and a destination device 204. According to the described techniques, source device 202 may be configured to encode graphical content generated by processing unit 206 using content encoder 208 before transmission to destination device 204. Content encoder 208 may be configured to output a bitstream having a bit rate. Processing unit 206 may be configured to control and / or influence the bit rate of content encoder 208 based on how processing unit 206 generates graphical content.

[0065] Source device 202 may include one or more components (or circuitry) for performing the various functions described herein. Destination device 204 may include one or more components (or circuitry) for performing the various functions described herein. In some examples, one or more components of source device 202 may be components of a system-on-a-chip (SoC). Similarly, in some examples, one or more components of destination device 204 may be components of a SoC.

[0066] Source device 202 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, source device 202 may include processing unit 206, content encoder 208, system memory 210, and communication interface 212. Processing unit 206 may include internal memory 209. Processing unit 206 may be configured to perform graphics processing, such as in graphics processing pipeline 207-1. Content encoder 208 may include internal memory 211.

[0067] Memory such as system memory 210 external to processing unit 206 and content encoder 208 may be accessible to processing unit 206 and content encoder 208. For example, processing unit 206 and content encoder 208 may be configured to read from and / or write to external memory such as system memory 210. Processing unit 206 and content encoder 208 may be communicatively coupled to system memory 210 via a bus. In some examples, processing unit 206 and content encoder 208 may be communicatively coupled to each other via this bus or a different connection.

[0068] Content encoder 208 can be configured to receive graphic content from any source such as system memory 210 and / or processing unit 206. System memory 210 can be configured to store graphic content generated by processing unit 206. For example, processing unit 206 can be configured to store graphic content in system memory 210. Content encoder 208 can be configured to receive graphic content in the form of pixel data (e.g., from system memory 210 and / or processing unit 206). Alternatively, content encoder 208 can be configured to receive pixel data of graphic content generated by processing unit 206. For example, content encoder 208 can be configured to receive the value of each component (e.g., each color component) of one or more pixels of graphic content. As an example, a pixel in the red, green, and blue (RGB) color space may include a first value for the red component, a second value for the green component, and a third value for the blue component.

[0069] Internal memory 209, system memory 210, and / or internal memory 211 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 209, system memory 210, and / or internal memory 211 may include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0070] According to some examples, internal memory 209, system memory 210, and / or internal memory 211 may be non-transitory storage media. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 209, system memory 210, and / or internal memory 211 are inmovable or that their contents are static. As an example, system memory 210 may be removed from source device 202 and moved to another device. As another example, system memory 210 may not be removable from source device 202.

[0071] Processing unit 206 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 206 may be integrated into the motherboard of source device 202. In some examples, processing unit 206 may reside on a graphics card mounted in a port on the motherboard of source device 202, or may otherwise be incorporated into a peripheral device configured to interoperate with source device 202.

[0072] Processing unit 206 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 206 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 209) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0073] Content encoder 208 can be any processing unit configured to perform content encoding. In some examples, content encoder 208 may be integrated into the motherboard of source device 202. Content encoder 208 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, content encoder 208 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 211) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered as one or more processors.

[0074] Communication interface 212 may include receiver 214 and transmitter 216. Receiver 214 may be configured to perform any of the receiving functions described relative to source device 202. For example, receiver 214 may be configured to receive information from destination device 204, which may include a request for content. In some examples, in response to receiving a request for content, source device 202 may be configured to perform one or more of the described techniques, such as generating or otherwise producing graphical content for delivery to destination device 204. Transmitter 216 may be configured to perform any of the transmitting functions described herein relative to source device 202. For example, transmitter 216 may be configured to transmit encoded content to destination device 204, such as encoded graphical content generated by processing unit 206 and content encoder 208 (e.g., the graphical content is generated by processing unit 206, and content encoder 208 receives the graphical content as input to generate or otherwise produce the encoded graphical content). Receiver 214 and transmitter 216 may be combined to form transceiver 218. In such examples, transceiver 218 can be configured to perform any of the receive and / or transmit functions described relative to source device 202.

[0075] Destination device 204 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, destination device 204 may include processing unit 220, content decoder 222, system memory 224, communication interface 226, and one or more displays 231. Reference to display 231 may refer to one or more displays 231. For example, display 231 may include a single display or multiple displays. Display 231 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation on the first display and the second display. In other examples, the first display and the second display may receive the same frames for presentation on the first display and the second display.

[0076] Processing unit 220 may include internal memory 221. Processing unit 220 may be configured to perform graphics processing, such as in graphics processing pipeline 207-2. Content decoder 222 may include internal memory 223. In some examples, destination device 204 may include a display processor, such as display processor 227, to perform one or more display processing techniques on one or more frames generated by processing unit 220 before being rendered by one or more displays 231. Display processor 227 may be configured to perform display processing. For example, display processor 227 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 220. One or more displays 231 may be configured to display content generated using decoded content. For example, display processor 227 may be configured to process one or more frames generated by processing unit 220, wherein the one or more frames are generated by processing unit 220 using decoded content derived from encoded content received from source device 202. Subsequently, display processor 227 may be configured to perform display processing on one or more frames generated by processing unit 220. One or more displays 231 may be configured to display or otherwise present frames processed by display processor 227. In some examples, one or more display devices may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0077] Memory (such as system memory 224) external to processing unit 220 and content decoder 222 may be accessible to processing unit 220 and content decoder 222. For example, processing unit 220 and content decoder 222 may be configured to read from and / or write to external memory (such as system memory 224). Processing unit 220 and content decoder 222 may be communicatively coupled to system memory 224 via a bus. In some examples, processing unit 220 and content decoder 222 may be communicatively coupled to each other via this bus or different connections.

[0078] Content decoder 222 can be configured to receive graphic content from any source, such as system memory 224 and / or communication interface 226. System memory 224 can be configured to store received encoded graphic content, such as encoded graphic content received from source device 202. Content decoder 222 can be configured to receive encoded graphic content in the form of encoded pixel data (e.g., from system memory 224 and / or communication interface 226). Content decoder 222 can be configured to decode the encoded graphic content.

[0079] Internal memory 221, system memory 224, and / or internal memory 223 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 221, system memory 224, and / or internal memory 223 may include random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0080] According to some examples, internal memory 221, system memory 224, and / or internal memory 223 may be non-transitory storage media. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 221, system memory 224, and / or internal memory 223 are inmovable or that their contents are static. As an example, system memory 224 may be removed from destination device 204 and moved to another device. As another example, system memory 224 may not be removable from destination device 204.

[0081] Processing unit 220 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 220 may be integrated into the motherboard of destination device 204. In some examples, processing unit 220 may reside on a graphics card mounted in a port on the motherboard of destination device 204, or may otherwise be incorporated into a peripheral device configured to interoperate with destination device 204.

[0082] Processing unit 220 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 220 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 221) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0083] Content decoder 222 can be any processing unit configured to perform content decoding. In some examples, content decoder 222 may be integrated into the motherboard of destination device 204. Content decoder 222 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, content decoder 222 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 223) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0084] Communication interface 226 may include receiver 228 and transmitter 230. Receiver 228 may be configured to perform any of the receiving functions described herein for destination device 204. For example, receiver 228 may be configured to receive information from source device 202, which may include encoded content, such as encoded graphical content generated or otherwise produced by processing unit 206 and content encoder 208 of source device 202 (e.g., the graphical content is generated by processing unit 206, and content encoder 208 receives the graphical content as input to generate or otherwise produce the encoded graphical content). As another example, receiver 228 may be configured to receive location information from source device 202, which may be encoded or unencoded (e.g., unencoded). In some examples, destination device 204 may be configured to decode the encoded graphical content received from source device 202 according to the techniques described herein. For example, content decoder 222 may be configured to decode the encoded graphical content to generate or otherwise produce decoded graphical content. Processing unit 220 may be configured to use the decoded graphical content to generate or otherwise produce one or more frames for rendering on one or more displays 231. Transmitter 230 may be configured to perform any of the transmission functions described herein for destination device 204. For example, transmitter 230 may be configured to send information to source device 202, which may include a request for content. Receiver 228 and transmitter 230 may be combined to form transceiver 232. In such an example, transceiver 232 may be configured to perform any of the receiving and / or transmitting functions described herein for destination device 204.

[0085] The content encoder 208 and content decoder 222 of system 200 represent examples of computing components (e.g., processing units) that can be configured to perform one or more techniques for encoding and decoding content, respectively, according to various examples described in this disclosure. In some examples, the content encoder 208 and content decoder 222 may be configured to operate according to a content decoding standard, such as a video decoding standard, a display streaming compression standard, or an image compression standard.

[0086] like Figure 2 As shown, source device 202 can be configured to generate encoded content. Therefore, source device 202 can be referred to as a content encoding device or content encoding apparatus. Destination device 204 can be configured to decode the encoded content generated by source device 202. Therefore, destination device 204 can be referred to as a content decoding device or content decoding apparatus. In some examples, source device 202 and destination device 204 can be separate devices, as shown. In other examples, source device 202 and destination device 204 can be on the same computing device, or can be part of the same computing device. In any example, the graphics processing pipeline can be distributed between the two devices. For example, a single graphics processing pipeline can include multiple graphics processes. Graphics processing pipeline 207-1 can include one or more of the multiple graphics processes. Similarly, graphics processing pipeline 207-2 can include one or more of the multiple graphics processes. In this respect, graphics processing pipeline 207-1, cascaded with graphics processing pipeline 207-2 or otherwise configured as graphics processing pipeline 207-2, can produce a complete graphics processing pipeline. Alternatively, graphics processing pipeline 207-1 can be a partial graphics processing pipeline, and graphics processing pipeline 207-2 can be a partial graphics processing pipeline; when combined, they produce a distributed graphics processing pipeline.

[0087] In some examples, the graphics processing performed in graphics processing pipeline 207-1 may not be performed in graphics processing pipeline 207-2 or may be repeated in other ways. For example, graphics processing pipeline 207-1 may include: receiving first position information corresponding to a first orientation of the device. Graphics processing pipeline 207-1 may also include: generating first graphic content based on the first position information. Additionally, graphics processing pipeline 207-1 may include: generating motion information for distorting the first graphic content. Graphics processing pipeline 207-1 may also include: encoding the first graphic content. Furthermore, graphics processing pipeline 207-1 may include: providing the motion information and the encoded first graphic content. Graphics processing pipeline 207-2 may include: providing first position information corresponding to a first orientation of the device. Graphics processing pipeline 207-2 may also include: receiving the encoded first graphic content generated based on the first position information. In addition, graphics processing pipeline 207-2 may include: receiving motion information. The graphics processing pipeline 207-2 may further include: decoding the encoded first graphics content to generate decoded first graphics content. Additionally, the graphics processing pipeline 207-2 may include: distorting the decoded first graphics content based on the motion information. By distributing the graphics processing pipeline between the source device 202 and the destination device 204, the destination device may be able to render graphics content that it would otherwise be unable to render and therefore unable to present in some examples. Other example benefits are described throughout this disclosure.

[0088] As described, devices such as source device 202 and / or destination device 204 can refer to any device, apparatus, or system configured to perform one or more of the described technologies. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), end product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch, augmented reality device, or virtual reality device), non-wearable device, augmented reality device, virtual reality device, display (e.g., display device), television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein.

[0089] Source device 202 may be configured to communicate with destination device 204. For example, destination device 204 may be configured to receive encoded content from source device 202. In some examples, the communication coupling between source device 202 and destination device 204 is shown as link 234. Link 234 may include any type of medium or device capable of moving encoded content from source device 202 to destination device 204.

[0090] exist Figure 2 In one example, link 234 may include a communication medium enabling source device 202 to transmit encoded content to destination device 204 in real time. The encoded content may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 204. The communication medium may include any wireless or wired communication medium, such as radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, wide area network, or global network (such as the Internet). The communication medium may include a router, switch, base station, or any other equipment that may be useful in facilitating communication from source device 202 to destination device 204. In other examples, link 234 may be a point-to-point connection between source device 202 and destination device 204, such as a wired or wireless display link connection (e.g., a High Definition Multimedia Interface (HDMI) link, a DisplayPort link, a Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) link, or another link through which encoded content can traverse from source device 202 to destination device 204).

[0091] In another example, link 234 may include a storage medium configured to store encoded content generated by source device 202. In this example, destination device 204 may be configured to access the storage medium. The storage medium may include various locally accessible data storage media, such as Blu-ray discs, DVDs, CD-ROMs, flash memory, or other suitable digital storage media for storing encoded content.

[0092] In another example, link 234 may include a server or another intermediate storage device configured to store encoded content generated by source device 202. In this example, destination device 204 may be configured to access the encoded content stored on the server or other intermediate storage device. The server may be a type of server capable of storing encoded content and sending that encoded content to destination device 204.

[0093] The described devices, such as source device 202 and destination device 204, can be configured to communicate with each other. Communication may include sending and / or receiving information. Information may be carried in one or more messages. As an example, a first device communicating with a second device can be described as communicatively coupled to or otherwise communicatively coupled to the second device. For example, a client device and a server may be communicatively coupled. As another example, a server may be communicatively coupled to multiple client devices. As another example, any device described as configured to perform one or more technologies of this disclosure may be communicatively coupled to one or more other devices configured to perform one or more technologies of this disclosure. In some examples, when communicatively coupled, the two devices may actively send or receive information, or may be configured to send or receive information. If not communicatively coupled, any two devices may be configured to communicatively couple with each other, such as according to one or more communication protocols conforming to one or more communication standards. The reference to "any two devices" does not mean that only two devices may be configured to be communicatively coupled with each other; rather, any two devices include more than two devices. For example, a first device may be communicatively coupled with a second device, and a first device may be communicatively coupled with a third device. In this example, the first device could be a server.

[0094] refer to Figure 2Source device 202 can be described as communicatively coupled to destination device 204. In some examples, the term "communically coupled" can refer to a communication connection, which can be direct or indirect. In some examples, link 234 can represent the communication coupling between source device 202 and destination device 204. The communication connection can be wired and / or wireless. A wired connection can refer to a conductive path, trace, or physical medium (excluding wireless physical media) through which information can travel. A conductive path can refer to any conductor of any length, such as a conductive pad, conductive via, conductive plane, conductive trace, or any conductive medium. A direct communication connection can refer to a connection in which no intermediate component resides between the two communicatively coupled components. An indirect communication connection can refer to a connection in which at least one intermediate component resides between the two communicatively coupled components. The two communicatively coupled devices can communicate with each other through one or more different types of networks (e.g., wireless networks and / or wired networks) according to one or more communication protocols. In some examples, the two communicatively coupled devices can be associated with each other through an association process. In other examples, the two communicatively coupled devices can communicate with each other without participating in an association process. For example, a device such as source device 202 is configured to unicast, broadcast, multicast, or otherwise send information (e.g., encoded content) to one or more other devices (e.g., one or more destination devices, including destination device 204). Destination device 204 in this example can be described as communicatively coupled to each of the one or more other devices. In some examples, the communication connection enables the sending and / or receiving of information. For example, according to the techniques of this disclosure, a first device communicatively coupled to a second device can be configured to send information to and / or receive information from the second device. Similarly, according to the techniques of this disclosure, the second device in this example can be configured to send information to and / or receive information from the first device. In some examples, the term "communicatively coupled" can refer to a temporary, intermittent, or permanent communication connection.

[0095] Any of the described devices, such as source device 202 and destination device 204, may be configured to operate according to one or more communication protocols. For example, source device 202 may be configured to communicate with destination device 204 using one or more communication protocols (e.g., receiving information from and / or sending information to destination device 204). In such an example, source device 202 may be described as communicating with destination device 204 via a connection. The connection may adhere to or otherwise conform to a communication protocol. Similarly, destination device 204 may be configured to communicate with source device 202 using one or more communication protocols (e.g., receiving information from and / or sending information to source device 202). In such an example, destination device 204 may be described as communicating with source device 202 via a connection. The connection may adhere to or otherwise conform to a communication protocol.

[0096] The term "communication protocol" can refer to any communication protocol, such as a communication protocol that conforms to a communication standard. As used herein, the term "communication standard" can include any communication standard, such as wireless communication standards and / or wired communication standards. Wireless communication standards can correspond to wireless networks. As an example, a communication standard can include any wireless communication standard corresponding to a Wireless Personal Area Network (WPAN) standard, such as Bluetooth (e.g., IEEE 802.15) or Bluetooth Low Energy (BLE) (e.g., IEEE 802.15.4). As another example, a communication standard can include any wireless communication standard corresponding to a Wireless Local Area Network (WLAN) standard, such as Wi-Fi (e.g., any 802.11 standard, such as 802.11a, 802.11b, 802.11c, 802.11n, or 802.11ax). As yet another example, a communication standard can include any wireless communication standard corresponding to a Wireless Wide Area Network (WWAN) standard, such as 3G, 4G, 4G LTE, 5G, or 6G.

[0097] refer to Figure 2Content encoder 208 can be configured to encode graphical content. In some examples, content encoder 208 can be configured to encode graphical content into one or more video frames of extended reality (XR) or virtual reality (VR) content. When content encoder 208 encodes content, it can generate a bitstream. The bitstream can have a bit rate, such as bits / time units, where the time unit is any time unit, such as seconds or minutes. The bitstream can include a sequence of bits that forms a decoded representation of the graphical content and associated data. To generate the bitstream, content encoder 208 can be configured to perform encoding operations on pixel data, such as pixel data corresponding to a shadow texture atlas. For example, when content encoder 208 performs encoding operations on image data (e.g., one or more blocks of a shadow texture atlas) provided as input, it can generate a series of decoded images and associated data. The associated data can include a set of decoding parameters, such as quantization parameters (QP).

[0098] like Figure 1 As shown, a single printed circuit board (PCB) can support multiple components of the SoC 100, including the CPU 102, GPU 104, DSP 106, etc. For AR or VR devices, these components can be located on different PCBs. Figure 3 This is a block diagram illustrating an augmented reality or virtual reality subsystem according to various aspects of this disclosure. For example... Figure 3 As seen in the example, destination device 204 can be in the form of glasses, and source device 202 can be in the form of a mobile device. If destination device 204 has a glasses form factor, various components can be distributed across multiple PCBs 302, 304, 306 in a multi-PCB architecture. For example, the main SoC or primary SoC 308 and main power management integrated circuit (PMIC) 310 can reside on the first PCB 302, the camera and sensor coprocessor 312 and its associated PMIC 314 can reside on the second PCB 304, and the connectivity processor 316 and its associated PMIC 318 can reside on the third PCB 306. Due to the individual locations of PCBs 302, 304, 306, the length of connectors between PCBs 302, 304, 306 may exceed design specifications. Furthermore, connectors can be arranged in a multi-point configuration, which also hinders performance due to stubs and reflections. Flexible PCBs can also be used between PCBs 302, 304, 306, which may further affect signal integrity.

[0099] Figure 4 This is an illustration of the placement of components in a device having the external dimensions of eyeglasses according to various aspects of this disclosure. For example... Figure 4As seen in the example, the main SoC 308 and main power management IC (PMIC) 310 may reside on a first PCB 302 (also known as the CCA circuit card assembly) in one arm of the glasses, the camera and sensor coprocessor 312 and its associated PMIC 314 may reside on a second PCB 304 on the glasses bridge, and the connectivity processor 316 and its associated PMIC 318 may reside on a third PCB 306 on the other arm of the glasses. The locations of the battery and speaker are also... Figure 4 As shown in the diagram, a board-to-board (B2B) flexible printed circuit (FPC) connector 402 couples the first PCB 302, the second PCB 304, and the third PCB 306 across the glasses' hinge 404 (only one is marked). Throughout this disclosure, the augmented reality chip may be referred to as "Aurora".

[0100] The small form factor of the device necessitates a small PCB, resulting in limited PCB area availability. Signal integrity may be compromised as signals travel across the hinges. Furthermore, long paths (e.g., 20-25 cm from one arm of the eyeglass to the other) and paths on flexible cables with high insertion loss can lead to signal integrity issues for high-speed signals such as System Power Management Interface (SPMI) protocol signals. The small form factor of the eyeglasses dictates small board-to-board connectors. This small size imposes strict constraints on the amount of wire that can cross the hinges. For example, the number of signals that can be transmitted across the hinges may be limited. Additionally, the small volume of the eyeglass frame constrains trace thickness, thus limiting the sharing of power rails across subsystems.

[0101] According to various aspects of this disclosure, machine learning techniques can be used for dynamic power grids. In some specific implementations, neural networks may be employed. The connections between the layers of a neural network may be fully connected or locally connected. Figure 5A An example of a fully connected neural network 502 is illustrated. In the fully connected neural network 502, neurons in the first layer can transmit their outputs to each neuron in the second layer, so that each neuron in the second layer will receive inputs from each neuron in the first layer. Figure 5B An example of a locally connected neural network 504 is illustrated. In the locally connected neural network 504, neurons in a first layer can connect to a finite number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 504 can be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strength can have different values ​​(e.g., 510, 512, 514, and 516). The connectivity pattern of locally connected layers can produce spatially different receptive fields in higher layers because neurons in higher layers in a given region can receive inputs that are tuned to the characteristics of a restricted portion of the total input to the network through training.

[0102] An example of a locally connected neural network is a convolutional neural network. Figure 5C An example of a convolutional neural network 506 is illustrated. Convolutional neural network 506 can be configured such that the connection strength associated with the input for each neuron in the second layer is shared (e.g., 508). Convolutional neural networks may be well-suited for problems where the spatial location of the input is meaningful.

[0103] One type of convolutional neural network is the deep convolutional network (DCN). Figure 5D A detailed example of a DCN 500 designed to recognize visual features based on an image 526 input from an image capture device 530 (such as an in-vehicle camera) is illustrated. The DCN 500 in this example can be trained to identify traffic signs and the numbers provided on them. Of course, the DCN 500 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0104] Supervised learning can be used to train the DCN 500. During training, an image (such as image 526 of a speed limit sign) can be presented to the DCN 500, and the forward pass can then be computed to produce output 522. The DCN 500 may include a feature extraction part and a classification part. Upon receiving image 526, convolutional layer 532 may apply a convolutional kernel (not shown) to image 526 to generate a first set of feature maps 518. As an example, the convolutional kernel used for convolutional layer 532 may be a 5×5 kernel that generates 28×28 feature maps. In this example, since four different feature maps are generated in the first set of feature maps 518, four different convolutional kernels are applied to image 526 at convolutional layer 532. Convolutional kernels may also be referred to as filters or convolutional filters.

[0105] The first set of feature maps 518 can be subsampled by a max-pooling layer (not shown) to generate a second set of feature maps 520. The max-pooling layer reduces the size of the first set of feature maps 518. That is, the size of the second set of feature maps 520 (e.g., 14×14) is smaller than the size of the first set of feature maps 518 (e.g., 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 520 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0106] exist Figure 5DIn the example, a second set of feature maps 520 is convolved to generate a first feature vector 524. Furthermore, the first feature vector 524 is further convolved to generate a second feature vector 528. Each feature of the second feature vector 528 may include a number corresponding to a possible feature of image 526, such as "sign", "60", and "100". A softmax function (not shown) converts the numbers in the second feature vector 528 into probabilities. Thus, the output 522 of DCN 500 can be the probability that image 526 includes one or more features.

[0107] In this example, the probabilities for "sign" and "60" in output 522 are higher than the probabilities for other numbers in output 522 (such as "30", "40", "50", "70", "80", "90", and "100"). Before training, output 522 generated by DCN 500 may be incorrect. Therefore, the error between output 522 and the target output can be calculated. The target output is the baseline ground truth (e.g., "sign" and "60") of image 526. The weights of DCN 500 can then be adjusted so that output 522 of DCN 500 is more closely aligned with the target output.

[0108] To adjust the weights, the learning algorithm computes the gradient vector of the weights. The gradient indicates by how much the error will increase or decrease as the weights are adjusted. At the top layers, the gradient corresponds directly to the values ​​of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient depends on the values ​​of the weights and the error gradient computed in the higher layers. The weights can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves "passing backward" through the neural network.

[0109] In practice, the error gradient of the weights can be calculated using a small number of examples to make the calculated gradient approximate the true error gradient. This approximation method is called stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, a new image can be presented to the DCN 500, and the forward pass through the DCN 500 can produce an output that can be considered an inference or prediction of the DCN 500.

[0110] Deep Belief Networks (DBNs) are probabilistic models that include multiple layers of hidden nodes. DBNs can be used to extract hierarchical representations of training datasets. DBNs are obtained by stacking layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that learns a probability distribution from a set of inputs. Because RBMs can learn a probability distribution without information about the class each input should be classified into, they are often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained unsupervised and used as a feature extractor, while the top RBM can be trained supervisedly (on the joint distribution of inputs from the previous layer and the target class) and used as a classifier.

[0111] Deep convolutional networks (DCNs) are convolutional networks configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning, where both the input and output targets are known for many paradigms and are used to modify the network's weights using gradient descent.

[0112] DCNs can be feedforward networks. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational cost of a DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0113] The processing at each layer of a convolutional network can be thought of as a spatially invariant template or base projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then a convolutional network trained on that input can be thought of as three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The output of the convolutional connections can be thought of as forming feature maps in subsequent layers, where each element of the feature map (e.g., 520) receives input from a range of neurons in the previous layer (e.g., feature map 518) and from each of the multiple channels. The values ​​in the feature maps can be further processed using non-linear methods (e.g., rectified, max(0,x)). Values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and provides additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied through lateral inhibition between neurons in the feature maps.

[0114] The performance of deep learning architectures can increase as more labeled data points become available or as computational power increases. Modern deep neural networks are typically trained with computational resources thousands of times greater than those available to researchers just fifteen years ago. New architectures and training paradigms can further improve the performance of deep learning. Corrected linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce overfitting and thus enable larger models to generalize better. Encapsulation techniques can extract data from a given receptive field and further improve overall performance.

[0115] Figure 6 This is a block diagram illustrating a Deep Convolutional Network (DCN) 650. The DCN 650 can include multiple layers of different types based on connectivity and weight sharing. Figure 6 As shown, the DCN 650 includes convolutional blocks 654A and 654B. Each of the convolutional blocks 654A and 654B can be configured using a convolutional layer (CONV) 656, a normalization layer (LNorm) 658, and a max pooling layer (MAX POOL) 660. Although only two of the convolutional blocks 654A and 654B are shown, this disclosure is not limited thereto, and any number of convolutional blocks 654A and 654B can be included in the DCN 650 according to design preferences.

[0116] Convolutional layer 656 may include one or more convolutional filters that can be applied to the input data to generate feature maps. Normalization layer 658 may normalize the output of the convolutional filters. For example, normalization layer 658 may provide whitening or lateral suppression. Max pooling layer 660 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0117] For example, the parallel filter bank of a deep convolutional network can be loaded onto the CPU 102 or GPU 104 of the SoC 100 (e.g., Figure 1 To achieve high performance and low power consumption. In an alternative implementation, a parallel filter bank may be loaded onto the DSP 106 or ISP 116 of the SoC 100. In addition, the DCN 650 can access other processing blocks that may exist on the SoC 100 (e.g., sensor processor 114 and navigation module 120, respectively, dedicated to sensors and navigation).

[0118] The DCN 650 may also include one or more fully connected layers 662 (FC1 and FC2). The DCN 650 may also include logistic regression (LR) layers 664. Weights (not shown) to be updated are present between each of the layers 656, 658, 660, 662, and 664 of the DCN 650. The output of each layer (e.g., 656, 658, 660, 662, and 664) can be used as input to the next layer in the DCN 650 (e.g., 656, 658, 660, 662, and 664) to learn hierarchical feature representations from the input data 652 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block in convolutional block 654A. The output of the DCN 650 is a classification score 666 of the input data 652. The classification score 666 may be a set of probabilities, where each probability is the probability that the input data includes a feature from the feature set.

[0119] Figure 7 This is a block diagram illustrating an exemplary software architecture 700 that enables modularization of artificial intelligence (AI) functionality. According to various aspects of this disclosure, architecture 700 can be used to design various processing blocks of a SoC 720 (e.g., CPU 722, DSP 724, GPU 726, and / or NPU 728) to support power multiplexing control performed by an AI application 702. Architecture 700 can, for example, be included in computing devices such as smartphones or AR glasses.

[0120] AI application 702 can be configured to invoke functions defined in user space 704, which may, for example, provide the detection and recognition of a scene indicating the current location of a computing device (including architecture 700). AI application 702 may, for example, configure microphones and cameras differently depending on whether the recognized scene is an office, lecture hall, restaurant, or outdoor environment (such as a lake). AI application 702 may make requests for compiled code associated with libraries defined in AI Function Application Programming Interface (API) 706. This request may ultimately rely on the output of a deep neural network configured to provide inferred responses based on, for example, video and location data.

[0121] The runtime engine 708 (which may be compiled code of the runtime framework) can be further accessed by the AI ​​application 702. The AI ​​application 702 can cause the runtime engine 708 to request inference, for example, at specific time intervals or when triggered by an event detected by the user interface of the AI ​​application 702. When the runtime engine 708 provides an inference response, it can then signal to the operating system (OS) space 710 running on the SoC 720, such as the kernel 712. In some examples, the kernel 712 may be a LINUX kernel. The operating system can then enable sequential relaxation of quantization to be performed on the CPU 722, DSP 724, GPU 726, NPU 428, or some combination thereof. The CPU 722 can be directly accessed by the operating system, while other processing blocks can be accessed through drivers such as drivers 714, 716, or 718 for the DSP 724, GPU 726, or NPU 728, respectively. In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 722, DSP 724 and GPU 726, or on NPU 728.

[0122] To achieve wider market adoption, augmented reality (AR) glasses should be lightweight and have a small form factor (e.g., a streamlined form factor). In fact, original equipment manufacturers (OEMs) can specify maximum size limits to achieve a streamlined form factor. However, a streamlined form factor limits the number of chips, chip package size, battery size, and battery capacity. The printed circuit board (PCB) inside the side arms determines the overall product size. The package size of the main system-on-chip (SoC) and power management integrated circuit (PMIC) determines the overall PCB size on each arm. To achieve size targets, due to Y-size limits, only one PMIC with associated passive devices can be placed on the PCB. Furthermore, lower power consumption improves the user experience by allowing for a lower battery capacity and a smaller battery as a result.

[0123] For next-generation augmented reality chips, SoC feature sets are increasing. However, PCB size specifications are very tight. In fact, SoC package sizes will decrease over time, forcing PMIC sizes to shrink. As feature sets increase, the power consumption of each core device and its associated power rails will increase accordingly, which in turn requires additional power supplies or regulators. To accommodate more regulators, either multiple PMICs are added or a larger single PMIC is introduced. Both solutions increase the Y-axis dimension of the PCB, which is detrimental to smooth glass.

[0124] Figure 8 This is an illustration of an augmented reality printed circuit board (PCB) according to various aspects of this disclosure. Figure 8In the example, an augmented reality PMIC 802 (e.g., Aurora PMIC) and an augmented reality SoC 804 (e.g., Aurora SoC) are provided on PCB 806.

[0125] Figure 9 This is an illustration illustrating the limitations of an augmented reality printed circuit board (PCB) according to various aspects of this disclosure. For example... Figure 9 As seen in the example, due to the limited space on the PCB, an additional PMIC (PMIC2) cannot be placed on PCB 806.

[0126] Instead of adding a PMIC, core throttling can be used to limit peak current. However, core throttling impacts user experience. Another option for achieving lower power in a small battery is to split each rail into multiple rails, which again increases regulator requirements and PCB area. The desired outcome is to provide the peak current required for full performance at low power without increasing the number of regulators or PCB area.

[0127] Figure 10 This is a diagram illustrating an augmented reality power grid. Figure 10 In the example, the augmented reality power grid 1002 has some power supplies near their current limits (e.g., switch-mode power supplies (SMPS) or low-dropout (LDO) regulators (not shown)). The multimedia core device draws 4.5 amps (A) from a second power supply S2, which has a 4.5A limit. The neural signal processor (NSP) draws 4.2A, near the 4.5A limit of the third power supply S3. The crashtable memory rail (MXC) draws 3.8A from a sixth power supply S6, which is near its 4.5A limit. Other power supplies are underutilized. The graphics core draws 1.8A from a first power supply S1, which has a 4.5A limit. The central processing unit (CPU) core draws 2.3A from a fourth power supply S4, which has a 4.5A limit. The always-on memory rail (MXA) draws 1.2A from a fifth power supply S5, which has a 4.5A limit. The core logic rail (CX) draws 2.4A from a seventh power supply S7, which has a 4.5A limit.

[0128] Although the term “core” is used primarily throughout the description, the term “track” can be used interchangeably if the meaning of the sentence remains unchanged.

[0129] Augmented reality (AR) chips will see generational upgrades in cores such as graphics cores, multimedia cores, NSP cores, and static random access memory (SRAM). New cores with higher performance require higher peak current and therefore may specify multiple SMPS phases (or phases of another type of power supply). More SMPS phases result in more PMICs or a single, larger PMIC, leading to a larger PCB area. In one example, the AR grid 1004 includes seven power supplies (e.g., buck regulators) in a first PMIC (PMIC_A) and three power supplies in a second PMIC (PMIC_B). In this example, each power supply has a 4.5A limit. The fourth power supply S4 and the fifth power supply S5 in the first PMIC (PMIC_A), as well as the second power supply S2 and the third power supply S3, are two-phase power supplies providing 7A and 6A to the NSP core device and the multimedia core device, respectively. In the second PMIC (PMIC_B), the first power supply S1 and the second power supply S2 are two-phase SMPSs providing 6A to the MXC. The first power supply S1 of the first PMIC (PMIC_A) and the third power supply S3 of the second PMIC (PMIC_B) provide 2.5A to the graphics core and CX rail, respectively. The sixth power supply S6 and the seventh power supply S7 provide 4A and 2A to the CPU core and MXA rail, respectively. However, as stated above, the additional phases and extra PMICs increase the PCB size, making it difficult to achieve a sleek form factor for wearable devices (e.g., AR glasses). Although some peak current values ​​are provided in this example, this disclosure is not limited thereto.

[0130] According to various aspects of this disclosure, during peak current loads on a particular rail or from a particular core device, instead of adding more power (e.g., such as... Figure 11A Instead of using the SMPS phase shown, it uses the current capacity from an underutilized power source, such as Figure 11B As shown. Figure 11A This is a diagram illustrating an augmented reality power grid with additional phases. Figure 11B This is a diagram illustrating a dynamic power grid according to various aspects of this disclosure. Figure 11A In the example, power supplies S2 and S3 represent two phases providing 6A to the camera core and display core of the multimedia track. The graphics core and CX track each receive 2.5A from the first power supply S1 and the fourth power supply S4, respectively.

[0131] exist Figure 11B The system provides a power multiplexer (MUX) 1102 to select a power source (e.g., an SMPS phase or LDO regulator) to power a specific core / rail when the total peak current across all cores / rails exceeds its rated capacity. Figure 11BIn the example, the power MUX 1102 selectively receives power as input from all three power supplies S1, S2, and S3. The output of the power MUX 1102 is coupled to the camera core. Figure 11B In the example, the graphics core and CX track receive 2.5A from the first power supply S1 and the third power supply S3, respectively. The display core receives 4A from the second power supply S2. The camera core selectively receives a combination of 2.5A from the third power supply S3, 2.5A from the first power supply S1, and / or 2A from the second power supply S2.

[0132] In some scenarios, underutilized power supplies may exist. Based on utilization, the power MUX 1102 intelligently selects the correct power inputs S1, S2, and / or S3. Therefore, the power multiplexer control decision is based on a machine learning process that accepts multiple inputs, such as: the current load current of all power supplies, the current operating voltage of all power supplies, the specified core / rail voltage, and a usage days (DoU) (or power) model. The final power supply selection via the power multiplexer ensures that load current specifications are met and power is optimized. Because the MUX selection is based on a set of inputs, a machine learning model can be employed.

[0133] The advantages of the proposed solution include eliminating the need for additional power phases to power cores with higher feature sets. Therefore, the PCB area does not increase even with increased capacity. Furthermore, full core performance is achieved without using limit management or adding additional phases, preventing negative impacts on user experience. Additionally, power improvements enable smaller batteries. In shared-rail systems, power multiplexing allows for lower power consumption by switching cores to lower voltage supplies. Minimum point sleep current (RBSC) can be reduced by moving cores that remain on during system-on-chip (SoC) sleep to off power supplies.

[0134] According to various aspects of this disclosure, a MUX is used for power distribution. Traditionally, additional power phases are added to meet load current requirements if the capacity of a single phase is insufficient. Figure 12A This is a diagram illustrating an augmented reality power grid with additional phases. Figure 12A In the example, the first power supply SMPS1 is limited to 5A and provides 3A to the first power domain (power domain A), which includes cores A, B, and C. The second power supply SMPS2 and the third power supply SMPS3 include additional SMPS phases, each limited to 5A. The second power supply SMPS2 and the third power supply SMPS3 provide 7A to the second power domain (power domain B), which includes cores X, Y, and Z. Although not shown, Figure 12A In this case, a limit management scheme can be adopted instead of using an additional phase to solve the current overload of the second power supply SMPS2 and the third power supply SMPS3.

[0135] By using a power MUX, a load can draw current from different regulators based on which regulator can supply the full current specified by the load. Figure 12B This is a diagram illustrating a dynamic power grid with a power multiplexer according to various aspects of this disclosure. Figure 12B In the example, a power multiplexer (MUX) (also known as a power switch) 1202 is provided. The power MUX 1202 receives input from a first power supply SMPS1 and a second power supply SMPS2. The second power domain (power domain B) requires a current of 7A, which exceeds the 5A limit of the second power supply SMPS2. The core X of the second power domain (power domain B) receives power via the power MUX 1202. The power MUX 1202 switches between the first power supply SMPS1 and the second power supply SMPS2 based on the peak current load. These aspects employ the power MUX 1202 to deliver the peak current requirement of the load by utilizing the underloaded SMPSs and delivering the peak current requirement without adding an additional phase.

[0136] According to various aspects of this disclosure, machine learning facilitates MUX switching. Since there may be many regulators underloaded at any given time, the machine learning module determines which regulator is best suited to deliver current at a given time. The machine learning module accepts multiple inputs and outputs, which the regulator uses to deliver the required peak current.

[0137] Figure 13 This is a diagram illustrating a dynamic power grid with machine learning control according to various aspects of this disclosure. Figure 13 In this example, the power multiplexer (MUX) 1302 receives control signals from the machine learning module 1304. The machine learning module 1304 controls the selection of the MUX based on various inputs. Exemplary inputs to the machine learning module 1304 include the current voltage and current load of each regulator, core / rail current requirements, and a power model (e.g., a DoU model) used to estimate power consumption or advantage. The power model estimates the power consumed based on the current usage. The power MUX 1302 receives power from the power supply (e.g., an SMPS or LDO regulator (not shown)) in the PMIC 1306. In this example, the power MUX 1302 provides power to the first core (core A). The cores (core A, core B, core C, and core D), along with the machine learning module 1304 and the power MUX 1302, all reside in the SoC 1308 (e.g., an augmented reality SoC).

[0138] Constraints on the machine learning module 1304 may include meeting peak current requirements. Furthermore, the impact of the DoU or power model should be minimized. In some examples, the machine learning module 1304 outputs a MUX selection signal.

[0139] According to various aspects of this disclosure, full performance is achieved using a limited number of power phases. In existing systems, when peak current exceeds the power supply limit, either additional power is provided or performance is throttled to keep the peak current within the limit. Instead of throttling the core, the technology of this disclosure intelligently powers the core to achieve full performance without the need for additional regulators. With the proposed technology, unused power is utilized to power the core to achieve full performance.

[0140] Figure 14 This is a diagram illustrating a dynamic power grid for switching between power sources under overload conditions, according to various aspects of this disclosure. Figure 14 In the example, the three power supplies SMPS1, SMPS2, and SMPS3 each have a 5A current limit. The camera core draws 2A, the video core draws 3A, and the display core draws 1A. Because the total current specified by the cores exceeds the 5A limit of the first power supply SMPS1, the camera core switches to either the second power supply SMPS2 or the third power supply SMPS3. The second power supply SMPS2 is supplying 3A to the other rails, while the third power supply SMPS3 is supplying 2.5A to the other rails. Therefore, both the second power supply SMPS2 and the third power supply SMPS3 are underutilized.

[0141] According to various aspects of this disclosure, a power model is employed as part of a machine learning model. In a shared-rail system, each core can be assigned a different operating voltage. If a core on a power rail assigns a higher voltage, all cores on the same rail will operate at a higher voltage, thus impacting power consumption. Improved power efficiency can be achieved if a core device is moved from a higher voltage supply to a lower voltage supply. Depending on the voltage requirements of each core, the core power supply can be moved to an underloaded supply or a supply with a lower voltage to reduce the impact of power consumption (DoU). Various aspects of this disclosure use a power MUX to dynamically switch cores to a lower voltage supply for lower power consumption.

[0142] Figure 15 This is a diagram illustrating a dynamic power grid for switching between power sources to reduce power consumption, according to various aspects of this disclosure. Figure 15 In the example, the multimedia rail requires 0.8V, which is the agreed voltage for the associated power supply based on the maximum specifications of all individual cores on the multimedia power rail. Figure 15In the example, the camera core operates at 0.8V, while the video core and display core operate at 0.75V and 0.65V, respectively. By moving the camera core to a different power supply operating at 0.8V, the voltage used for the first power supply SMPS1 can be reduced to 0.75V. Figure 15 In the example, the second power supply SMPS2 and the third power supply SMPS3 operate at 0.8V and 0.9V, respectively. Therefore, both the second power supply SMPS2 and the third power supply SMPS3 are candidates for powering the camera rail.

[0143] According to another aspect of this disclosure, minimum point sleep current (RBSC) savings can be achieved by moving cores that do not require power to a power-off state. In shared-rail systems, even if one of these cores is de-energized, leakage current will exist because the primary rail is kept at a minimum voltage to retain data (e.g., reserve voltage). Switching the faulty rail to a power-off state can provide RBSC savings.

[0144] Figure 16 This is a diagram illustrating a dynamic power grid for switching between power sources at a power failure core, according to various aspects of this disclosure. Figure 16 In the example, the CX rail operates at 0.5V, which is a convention voltage for the first power supply SMPS1 based on the maximum specified voltage of all cores associated with the CX rail. If the video core and display core enter sleep mode and therefore operate at 0V in their lowest point sleep (RBS) mode, the camera core can be moved to another power supply operating at 0.5V or higher. Therefore, the first power supply SMPS1 can be turned off to conserve RBS current.

[0145] Now about Figure 11B Describe example operation. In this example, the multimedia peak current exceeds the 4.5A limit. That is, when the camera core (drawing 2A) operates concurrently with the display core (drawing 4A), the multimedia core requires 6A. The second power supply S2 has a capacity of 4.5A. Instead of introducing an additional phase to meet the current specifications, a power MUX 1102 is added, which accepts inputs from the power supplies S1, S2, and S3 already available in the PMIC. When multimedia-intensive usage is triggered, if the estimated load current exceeds the 4.5A power supply limit, the machine learning module (e.g., Figure 13As shown in 1304, the input to the camera core is switched from the second power supply S2 to either the first power supply S1 or the third power supply S3. Both the first power supply S1 and the third power supply S3 have sufficient capacity to meet the 2A current requirement from the camera core. Depending on the current operating conditions and the voltages of the first and third power supplies S1 and S3, the machine learning module switches to one of them. Assume that the first power supply S1 operates at 0.7V, the third power supply S3 operates at 0.9V, and the camera core requires 0.65V. Under these assumptions, the machine learning module switches the camera core power source to the first power supply S1 because it provides the required current at the lowest required voltage. Full performance of the multimedia core is achieved without any throttling of the core.

[0146] Now about Figure 11B Describe another example operation. In this example, power consumption is optimized. Figure 11B In the example, it can be assumed that there is no peak current load on any power supply due to the specific use case. It is also assumed that the camera core requires 0.9V to operate, and the display rail only requires 0.75V. The second power supply S2 operates at 0.9V, and therefore, the display core's power consumption increases the overall SoC's power consumption. If the first power supply S1 or the third power supply S3 operates at 0.9V or higher, the camera core can switch to either the first power supply S1 or the third power supply S3. The second power supply voltage can then be reduced to 0.75V, which is the voltage required by the display core. Therefore, the display core's power consumption is optimal. The camera core's power consumption is continuously monitored, and the core switches between power supplies S1, S2, or S3 depending on which supply provides the best power benefit.

[0147] Now about Figure 17 Describe another example operation. In this example, Lowest Point Sleep Current (RBSC) is optimized. In a system where multiple cores are powered by a single rail, the entire rail remains on even if one core needs to be on in RBS state. This affects RBSC because the core that can remain off leaks current. In such cases, if a power MUX is used to move the core that can remain off to a power source that is off, the leakage effect will be reduced.

[0148] Figure 17 This is a diagram illustrating a dynamic power grid for switching between power sources to reduce power consumption, according to various aspects of this disclosure. Figure 17 In this example, cores B and C share the same rail. Cores A and B can be shut down in RBS mode, while core C needs to remain on. Since core C is on, core B will also remain on, thus increasing leakage. By using the power MUX 1702 to move core B to the first power supply S1 in shutdown mode, the RBSC is reduced.

[0149] Figure 18 This is a diagram illustrating a conventional power grid design. The power grid 1800 can be installed on a PCB (such as regarding...). Figure 8 , Figure 9 Implemented on the PCB shown in the example. Figure 18 As shown, the power grid 1800 may include a set of power supplies 1814, 1816, 1818, 1820, 1822, 1824, 1826 and 1828. Each power supply may be an SMPS, such as a step-down converter (e.g., a buck regulator). Figure 18 The power supplies illustrated can each provide up to 4.5 amps (A) of current. The power grid 1800 may also include a set of core devices 1802, 1804, 1806, and 1808 on the SoC 1809. Figure 18 In the example illustrated, core device 1802 is an application processor core (APC), core device 1804 is a graphics core, core device 1806 is an NSP, and core device 1808 is a multimedia core. In some respects, the APC can resemble a CPU. Each power supply pair provides power to one of the four core devices 1802, 1804, 1806, and 1808. Specifically, each pair of core devices provides power to PCB power planes 1810a, 1810b, 1810c, or 1810d. Since each power supply can provide up to 4.5 amps of current, and there are two power supplies coupled to each core device, each core device in the power grid 1800 can draw up to 9 amps of current. The voltage of each power supply is set based on the frequency requirements of the associated core device.

[0150] Each PCB power plane 1810a to 1810d includes a set of packaged interconnects 1812, such as ball grid array (BGA) package balls. The packaged interconnects 1812 couple the PCB power plane to a core device. For example, power supplies 1822 and 1824 provide power to PCB power plane 1810c. The packaged interconnects 1812 couple PCB power plane 1810c to a core device 1806. Power supplies 1822 and 1824 provide power to core device 1806 via PCB power plane 1810c and packaged interconnects 1812. Although... Figure 18 Examples illustrated include APC, graphics core, NSP, and multimedia core, but a core can include other computing engines, such as Figure 1 those exemplified in .

[0151] like Figure 18As shown, each core device receives power via a set of two power supplies. In some examples, each core device may be powered by a multiphase power supply. In other examples, some core devices may be powered by a single-phase power supply; for example, some core devices may draw power from only one power supply. Regardless of the number of power supplies, each power supply on grid 1800 is dedicated to one core device. Furthermore, grid 1800 may include any number of PMICs. Figure 18 The example power grid 1800 illustrated includes two PMICs, with four power supplies coupled to PMIC_A and four power supplies coupled to PMIC_B.

[0152] Figure 19 This is a diagram illustrating a conventional power scheme with limit management. Figure 19 The power grid 1900 illustrated in the example is similar to Figure 18 The grid 1800 illustrated in the example differs from grid 1900 in that grid 1900 includes only seven power sources. Specifically, core device 1808 is powered by only one power source 1828. The other core devices 1802, 1804, and 1806 are each powered by two power sources.

[0153] Such as about Figure 10 As discussed, it is difficult to achieve a streamlined form factor while maintaining multiple power supplies for each core device. Therefore, conventional power supplies (such as the Power Supply 1900) conserve PCB area by limiting the number of available power supplies. Due to the limited number of power supplies, the core device 1808 is left with only one power supply, thus limiting the available power to 4.5 amps. In scenarios where the core device 1808 can draw more than 4.5 amps of current, the core device 1808 is throttled, thereby reducing both the power consumption and performance of the core device 1808.

[0154] The Grid 1800 and Grid 1900 have several drawbacks. First, the grid typically underutilizes power. The power ratio per core device is based on peak current scenarios. However, some power may remain unused during active operation of the device. Second, each power supply occupies PCB area. Increasing the number of power supplies increases the amount of PCB area by increasing the PMIC count or PMIC size. Third, core devices with limited power supplies are occasionally throttled to reduce power extraction, thus impacting device performance.

[0155] Figure 20 This is a table illustrating voltage level thresholds. Each core device power rail can have multiple voltage levels based on the operating voltage frequency of the power rail. Voltage levels are also referred to as voltage angles. The power grid can implement multiple voltage levels to reduce the overall power consumption of the devices. For example, a power rail can be set to a lower voltage level to reduce the power consumption of the power rail.

[0156] exist Figure 20In the example illustrated, the core logic rail (CX) voltage can operate at one of eight operating voltage levels or at a holding voltage level. A higher core frequency specifies a higher voltage level. For example, a 1 GHz frequency specifies that the core logic rail operates at a boosted voltage level. Figure 20 The “Function” column in the table illustrated lists different exemplary naming conventions for each voltage threshold. Figure 20 The “SS”, “TT” and “FFG” columns illustrate the core logic rail voltage process corners. Figure 20 The naming convention for process corners illustrated in the examples typically uses two-letter indicators, where the first letter refers to an n-channel metal-oxide-semiconductor (NMOS) corner and the second letter refers to a p-channel metal-oxide-semiconductor (PMOS) corner. For example, a core voltage rail operating at the Turbo_L1 voltage level can operate at a slow-slow (SS) process corner or 0.904 volts. The core voltage rail can also additionally operate at a typical-typical (TT) process corner or a fast-fast global (FFG) process corner.

[0157] In practice, each core device can operate at different voltage levels based on an operating frequency specified for the usage scenario. In AR grid design, where power consumption is particularly important, each core device can be designed to operate at one of several active low voltage levels (such as LowSVS, Static Voltage Scaling (SVS), or SVS_L1).

[0158] Figure 21 This is a diagram illustrating a first improvement to the power grid 2100 according to various aspects of this disclosure. For example... Figure 21 As illustrated, the improved power grid 2100 may include four power sources 2114, 2116, 2118, and 2120. Each power source 2114 to 2118 is coupled to power rail 2130. For example, power source 2114 is coupled to power rail 2130. The other power sources 2116, 2118, and 2120 are also coupled to... Figure 21 Power rails not illustrated, each power source coupled to a separate power rail. The improved power grid 2100 may have multiple packaged interconnects 2112. The packaged interconnects 2112 may be grouped into groups of four, but any other number is also envisioned. Figure 21 In the example, each core device 2102, 2104, 2106, 2108 has four sets of packaged interconnects 2132, 2134 or sixteen packaged interconnects 2112 per core device. Each power rail can be coupled to a dedicated set of packaged interconnects 2132, 2134 for each core device 2102 to 2108. For example, power rail 2130 can be coupled to the respective sets of packaged interconnects 2134 for APC 2102, graphics core 2104, NSP 2106, and multimedia core 2108, such as... Figure 21 As illustrated in the example. In some aspects, each power source in the improved power grid 2100 can be housed in a PMIC (such as...). Figure 21 The improved power grid 2100 may include multiple PMICs, each including one or more power sources.

[0159] Each power supply can operate at different voltage levels. The available voltage levels can be predetermined. For example, a power supply can be configured to operate at... Figure 20 Operate at the voltage levels illustrated in the example. Figure 21 In the example illustrated, power supply 2114 operates at the nominal voltage level. Although specific voltage levels for each of the remaining power supplies 2116, 2118, and 2120 are not illustrated, Figure 21 The example illustrated has one power supply operating at a holding voltage level, one power supply operating at an SVS voltage level, and one power supply operating at an SVS_L1 voltage level.

[0160] As discussed, Figure 21 Each power supply in the configuration powers a power rail coupled to each core device. Since each power supply is coupled to each core device via a power rail, each power supply 2114, 2116, 2118, and 2120 can supply current to each core device 2102, 2104, 2106, and 2108. For example, power supply 2118 is coupled to each core device 2102, 2104, 2106, and 2108, although in... Figure 21 It is not explicitly shown in the text.

[0161] Each set of package interconnects 2132, 2134 is coupled to a core device, allowing each power supply to selectively provide current to one or more core devices. For example, power supplies 2114, 2116, 2118, 2120 coupled to APC 2102 are each selectively coupled to APC 2102, such that any one of power supplies 2114, 2116, 2118, 2120, or no power supply at all, can provide current to APC 2102. To facilitate power selection, switches (not illustrated) can be implemented to selectively couple each power supply to each core device. The switches can be located in different locations. In some respects, the switches can be located within the PMIC. For example, a switch located within the PMIC can toggle the connection between power supply 2118 and graphics core 2104. In other respects, the switches can be located on a PCB outside the PMIC.

[0162] Because each power source is selectively coupled to each core device via a switch, each core device can receive current from multiple power sources. For example, if each power source 2114, 2116, 2118, 2120 provides up to 4.5 amps of current, then each core device 2102, 2104, 2106, 2108 can receive up to 18 amps of current.

[0163] Each power supply can operate at any voltage level. In some respects, each power supply 2114, 2116, 2118, and 2120 can operate at different voltage levels. For example, power supply 2114 can operate at the nominal voltage level, power supply 2116 can operate at the SVS_L1 voltage level, power supply 2118 can operate at the holding voltage level, and power supply 2120 can operate at the SVS voltage level. In other respects, some power supplies can operate at the same voltage level. For example, power supplies 2116 and 2118 can both operate at the nominal voltage level.

[0164] although Figure 21 The example illustrated shows four power supplies, but the improved grid 2100 may have more or fewer than four power supplies. In some aspects, more than one power supply may be coupled to each power rail. For example, a second power supply in addition to power supply 2114 may be coupled to power rail 2130. In one specific implementation, the improved grid 2100 has six power supplies, each coupled to one of the six sets of packaged interconnects 2132 per core device.

[0165] Figure 22 This is a diagram illustrating a second improved power grid 2200 according to various aspects of the present disclosure. The second improved power grid 2200 is similar to the first improved power grid 2100, except that the multimedia core 2108 in the second improved power grid 2200 is coupled to three sets of packaged interconnects 2132, 2234 in the first improved power grid 2100 instead of four sets of packaged interconnects 2132, 2134. Specifically, the multimedia core 2108 is coupled to two sets of packaged interconnects 2132, each set comprising four packaged interconnects, and one set of packaged interconnects 2234 comprising eight packaged interconnects. Figure 22 As illustrated, in some aspects, each set of packaged interconnects 2132, 2234 may include more or fewer than four packaged interconnects. Additionally, the improved power grid 2200 may include core devices not coupled to each power source. Figure 22 As shown, only three power supplies are coupled to the multimedia core 2108. That is, the nominal power supply 2114, the SVS power supply 2120, and the holding power supply 2118 are coupled to the multimedia core 2108. The number of power supplies coupled to each core device and the number of package interconnects 2132 may depend on the number of voltage levels at which the core devices operate. Figure 21In the example, the multimedia core 2108 rail operates at only three different voltage levels, and therefore, the package interconnects for the multimedia core 2108 are divided into three groups 2132, 2234.

[0166] although Figure 21 and Figure 22 The improved power grids 2100 and 2200, illustrated respectively, have a specific number of packaged interconnects, packaged interconnect groups, core equipment, rails, and power supplies, but Figure 21 and Figure 22 This is merely an example. According to some aspects of this disclosure, the improved power grid may have different numbers of packaged interconnects, packaged interconnect groups, core devices, rails, and power supplies. For example, the SoC may have thousands of packaged interconnects, with each group of packaged interconnects 2132 comprising hundreds of packaged interconnects. In some aspects, one core device may be coupled to more packaged interconnects and / or more groups of packaged interconnects than another core device. Additionally, as an alternative to or supplement to the illustrated core devices, the improved power grid may include other core devices. For example, the improved power grid may include a DSP or NPU, such as... Figure 1 those exemplified in .

[0167] In conventional power grids (such as Figure 18 , Figure 19 In those examples, the number of core equipment rails can equal the number of power sources required. In improved power grids (such as...), Figure 21 and Figure 22 In the examples (those shown), the number of power supplies may correspond to the number of specified voltage levels. For instance, if an AR SoC specifies four voltage levels, then the AR SoC may have only four power supplies, instead of the seven or more power supplies that an AR SoC might need when using a conventional power grid.

[0168] Figure 23 This is a table illustrating various improvements to the use of the power grid based on this disclosure. Figure 23 The vertical columns in the diagram illustrate three example use cases for the improved power grid. Each use case involves four core devices: APC, GPU, Multimedia (MM), and NSP. Each core device in each use case operates at a power level such as SVS, SVS_L1, or Nominal (NOM). Each core device is specified with a different current, such as two amps, three amps, or four amps. Figure 23 The horizontal rows in the diagram show four power supplies: S1, S2, S3, and S4. Each power supply can provide up to 4.5 amps of current. Example power levels are depicted for each power supply in each use case. The last row maps the power supplies to the core device for each use case.

[0169] In the first usage scenario, the APC is specified with a nominal voltage level of 4 amps, the GPU with an SVS_L1 voltage level of 2 amps, the multimedia core with an SVS voltage level of 3 amps, and the NSP with an SVS voltage level of 3 amps. In this example, power supply S1 is set to the SVS voltage level, power supply S2 is set to the SVS voltage level, power supply S3 is set to the SVS_L1 voltage level, and power supply S4 is set to the nominal voltage level. Power supplies S1 and S2 supply current to the multimedia core and NSP. Power supply S3 supplies current to the GPU. Power supply S4 supplies current to the APC.

[0170] In the second use case, the APC is specified with an SVS voltage level and 3 amps, the GPU with a nominal voltage level and 3 amps, the multimedia core with a nominal voltage level and 4 amps, and the NSP with an SVS voltage level and 3 amps. In this example, power supplies S1, S2, S3, and S4 are set to their nominal voltage levels. Power supply S1 supplies current to the APC, power supply S2 supplies current to the NSP, and power supplies S3 and S4 supply current to the GPU and multimedia core.

[0171] In the third use case, the APC is specified with an SVS voltage level of 3 amps, the GPU with an SVS voltage level of 2 amps, the multimedia core with an SVS voltage level of 4 amps, and the NSP with an SVS voltage level of 3 amps. In this example, power supplies S1, S2, and S3 are all set to the SVS voltage level. Power supply S4 is off. Power supply S1 supplies current to the APC, while power supplies S2 and S3 supply current to the multimedia core, GPU, and NSP.

[0172] Figure 24 This is a diagram illustrating various aspects of intelligent power switches according to this disclosure. Figure 24 In the example illustrated, package 2430 includes four dedicated sets of package interconnects (e.g., package balls) 2432a, 2432b, 2432c, and 2432d. Each set of package interconnects 2432a, 2432b, 2432c, and 2432d is coupled to power supplies S1, S2, S3, and S4 (connections not shown), which operate at specified voltage levels. The first set of package interconnects 2432a receives power at the nominal voltage level. The second set of package interconnects 2432b receives power at the SVS_L1 voltage level. The third set of package interconnects 2432c receives power at the SVS voltage level. The fourth set of package interconnects 2432d receives power at the holding voltage level. Each set of package interconnects 2432a, 2432b, 2432c, and 2432d is coupled to a power switch 2438 via a die bump 2436.

[0173] A power switch 2438, comprising four terminals 2444 (only one terminal is labeled), is an electrical component capable of connecting or disconnecting a circuit. The power switch 2438 can be an analog power switch or a digital power switch. The power switch 2438 can be actuated by one or more devices, such as an artificial intelligence (AI) core 2440. Figure 24 As illustrated, the power switch 2438 can selectively couple one or more sets of packaged interconnects 2432a, 2432b, 2432c and / or 2432d to one or more core devices, such as the APC 2402.

[0174] AI core 2440 can control power switch 2438 via one or more select lines SEL_0, SEL_1, SEL_2, and SEL_N. AI core 2440 can receive one or more inputs, such as core device current requirements, core device voltage requirements, output voltages of all power supplies, and rated current and load of all power supplies. Using one or more inputs, AI core 2440 can determine whether each terminal 2444 of power switch 2438 should be closed or open for each core device. AI core 2440 can also use one or more inputs to determine the output voltage for each power supply. AI core 2440 can switch power switch 2438 between each power supply and core device based on one or more determinations. In some aspects, AI core 2440 can switch power switch 2438 such that one or more power supplies meet the voltage and current requirements of one or more core devices. AI core 2440 can also switch power switch 2438 to ensure low power consumption across all core devices relative to each power supply. To switch power switch 2438, AI core 2440 can connect or disconnect one or more terminals 2444 of the four terminals within power switch 2438.

[0175] To make a determination, the AI ​​Core 2440 can implement one or more machine learning models, such as those related to... Figures 5A to 5D , Figure 6 and Figure 7 The neural network described. For example, an AI model implemented in AI Core 2440 can receive core device current requirements, core device voltage requirements, the output voltages of all power supplies, and the rated current and load of all power supplies as inputs. The AI ​​model can then determine a power mapping based on one or more inputs, which indicates the voltage level for one or more power supplies and one or more core devices to be powered by those power supplies. Using the power mapping, the device implementing AI Core 2440 can adjust the voltage level for one or more power supplies and one or more power connections between the core devices and the power supplies. For example, AI Core 2440 can use one or more selection outputs to switch power switch 2438.

[0176] like Figure 24 As illustrated, the SoC die 2434 may include an APC 2402, an AI core 2440, and a power switch 2438. The PMIC 2442 may include a set of power supplies (S1, S2, S3, S4), and the PMIC 2442 receives voltage commands from the AI ​​core 2440. The PMIC 2442 may adjust the voltage levels of one or more switch-mode power supplies (SMPS) S1, S2, S3, S4 based on the voltage commands received from the AI ​​core 2440.

[0177] Figure 25 This is a diagram illustrating various aspects of a smart power switch grid according to this disclosure. (Source: [Original Source Name]) Figure 24 Elements with the same reference numerals are identical and will not be described again. Figure 25 In the example, the SoC die 2434 includes a multimedia power rail comprising a first power switch 2538a, a second power switch 2538b, and a third power switch 2538c. Each power switch 2538a to 2538c has four terminals 2444 (only one terminal is labeled). Each power switch 2538a to 2538c is coupled to a core device. The first power switch 2538a is coupled to a camera core 2502a, the second power switch 2538b is coupled to a display core 2502b, and the third power switch 2538c is coupled to a video core 2502c. Figure 25 As illustrated, each set of package interconnects 2432a, 2432b, 2432c, and 2432d can be selectively coupled to each core device 2502a, 2502b, and 2502c. The AI ​​core 2440 can be coupled via select lines SEL_0, SEL_1, and SEL_2 (in... Figure 25 In the example, SEL_N is not used to switch the connection between each set of package interconnects 2432a, 2432b, 2432c, and 2432d and each core device 2502a, 2502b, and 2502c. The AI ​​core 2440 can also change the voltage of each power supply S1, S2, S3, and S4 coupled to each set of dedicated package interconnects 2432a, 2432b, 2432c, and 2432d.

[0178] Figure 26 This is a circuit diagram illustrating a printed circuit board (PCB) with a power controller within a main power management integrated circuit (PMIC) according to various aspects of this disclosure. Figure 26As illustrated, PCB 2600 includes PMIC 2602, control logic unit 2604, power controller 2606, first power supply 2610, second power supply 2612, third power supply 2614, first power rail 2618, and second power rail 2620. Power controller 2606 can be a high-capacity, low-impedance switch. The switch can be a single-input dual-output switch at the output of second power supply 2612. A 2:1 analog multiplexer can also be added to the feedback path of second power supply 2612. Control logic unit 2604 can receive inputs, such as voltage or current indications, via a system power management interface (SPMI). Control logic unit 2604 can also receive inputs from first power supply 2610, second power supply 2612, and / or third power supply 2614. Based on the inputs, control logic unit 2604 can switch power controller 2606 such that second power supply 2612 supplies power to first power rail 2618, second power rail 2620, both power rails, or does not supply power to any power rail. The first power rail 2618 may be coupled to a first load (such as a multimedia core), and the second power rail 2620 may be connected to a second load (such as a memory controller).

[0179] Unlike mobile or computing platforms, in AR glasses, many use cases specify core operation at low voltage angles, which translate to small peak currents suitable for the capacity of a single buck converter (e.g., a single power supply) (e.g., 4.5A). Only a few use cases and / or high-temperature conditions specify core operation at maximum voltage angles, which push peak currents beyond the limits of a single buck converter. Buck converter allocation typically supports the worst-case peak current. Therefore, some core rails eventually require buck converters in groups (e.g., multiphase operation). Aspects of this disclosure reduce buck converter count bloat by intelligently and dynamically assigning additional buck converter phases to the load only when needed. Additional buck converter phases can be shared between two or more rails (e.g., loads). According to these aspects, when any core (e.g., an NSP or multimedia core) specifies an additional buck converter, a second buck converter phase is assigned only to the rail that requires the additional buck converter. Therefore, the second buck converter phase is shared between the two rails. Instead of two additional buck converters required for two rails, only one additional buck converter is needed for both rails together. These aspects save PMIC die area, and therefore PCB area, which is crucial for AR glasses to achieve the desired form factor. These aspects also save costs.

[0180] Sharing of a buck converter between two rails can be achieved by implementing a low-impedance switch within the PMIC. When both rails require a second buck converter, the peak current of one rail can be throttled. Without the proposed solution and without a second buck converter allocation, the rails would be throttled more frequently. Therefore, aspects of this disclosure reduce the need for throttling, which can lead to a poor user experience due to throttling critical rails running algorithms (such as sensing) at the core of the system, such as multimedia or NSP cores. This solution reduces the buck converter count and thus reduces PCB area, resulting in a streamlined form factor design.

[0181] like Figure 26 As illustrated, the second power supply 2612 may be shared between the first power rail 2618 and the second power rail 2620. A switch within the power controller 2606 receives instructions from the control logic unit 2604 to selectively couple either the first power rail 2618 or the second power rail 2620 to the second power supply 2612. Software within the control logic unit 2604 or another device on the PCB determines the load that should receive power from the second power supply 2612 based on factors such as the current task of the core. The software may be a command-mode feature, for example, to shut down a phase in a multiphase configuration. The same software may disconnect the power supply from one core (e.g., a grouped configuration or load) and assign that power supply to another core (e.g., a grouped configuration or load). Figure 26 An additional phase is shown. The same solution can be extended to any number of additional phases for any number of rails and step-down transformers as needed.

[0182] Figure 27 This is a circuit diagram of a PCB 2700 having a power controller external to the PMIC, illustrating various aspects of this disclosure. Figure 27 As illustrated, in some aspects, the power controller 2706 may be located external to the PMIC 2602. In these aspects, the power controller 2706 may receive inputs from PMIC general purpose inputs and outputs (GPIOs) and / or SoC GPIOs.

[0183] According to another aspect of this disclosure, intelligent allocation of additional buck converter phases can be controlled via machine learning. When usage conditions result in an increased rail voltage angle, the machine learning module in the processor can map the voltage angle to a peak current and commands for changing the buck converter output voltage. The machine learning module can also transmit commands to the PMIC via the SPMI for grouping the shared buck converter with the primary phase buck converter. The machine learning module can have rail priorities for additional phase allocation. For example, when the perception algorithm is running, if both the computer vision accelerator process under the multimedia power rail and the NSP core under the NSP power rail require additional buck converters, the machine learning module can choose to first run the computer vision accelerator by allocating the additional phase to the multimedia power rail, and then the perception pipeline uses the NSP, during which time the machine learning module assigns the second phase buck converter to the NSP power rail.

[0184] Additionally, machine learning can be incorporated to learn patterns in rail current voting relative to voltage angles. In these respects, the core is not throttled until the learning occurs. As the machine learning module learns the peak current drawn for different usage scenarios, it can begin dynamically assigning additional phases of the buck converter, as described above.

[0185] Peak current can be measured in various ways. Estimated peak currents for known usage scenarios can be stored in a database. Dynamic usage scenarios with peak currents not yet characterized can be processed by a machine learning module based on input from current sensors, such as a digital power meter (DPM) in the processor or an embedded power meter (EPM) in the PMIC that measures current. Then, if the peak current learned for a specific usage scenario exceeds the peak limit of a single buck converter, the machine learning module assigns a shared buck converter.

[0186] Figure 28This is a flowchart illustrating an example process 2800 for a power distribution pipeline according to various aspects of this disclosure. At block 2802, a specific use case (e.g., a task) begins. For example, a perception algorithm may be run. At block 2804, a machine learning module determines whether load current information for the relevant rails for that use case is stored in a database. If so, at block 2806, the machine learning module determines whether the load current of any rail exceeds the assigned buck limit for that use case. For example, if the assigned buck has a 4.5A limit, but the perception algorithm requires 6A, the load current exceeds the buck limit for that use case. If the buck limit is exceeded, at block 2808, the machine learning module arbitrates between rails sharing an additional buck. For example, if the multimedia rail and the NSP rail share an additional buck, based on information from the database, the machine learning module may first assign the shared buck to the multimedia rail for computer vision processing, and then, at block 2810, reassign the shared buck to the NSP rail. After completing the buck converter assignment for this usage scenario, process 2800 returns to block 2802 to await the next usage scenario. Similarly, if the load current of each rail does not exceed the assigned buck converter limit (2806: No), process 2800 returns to block 2802.

[0187] If the load current information is not in the database for this use case (2804: No), the process proceeds to box 2812. At box 2812, the machine learning module captures the load current of the relevant rail for the new use case. The machine learning module may receive data from a current sensor in the PMIC or SoC (such as from a DPM or EPM). The machine learning module then updates the database with the peak current information of the relevant rail for the new use case. At box 2814, the machine learning module assigns the buck converter to the default load and, if necessary, throttles another load until the database is updated. If the machine learning module cannot assign the shared power to a priority rail, it may be necessary to throttle another load until the database is updated. The machine learning module may then need to throttle one or more rails until the database is updated so that the rail does not exceed the voltage or current specification. After the database is updated, process 2800 returns to box 2802 to await the next use case.

[0188] Figure 29This is a flowchart illustrating a dynamic power control method according to various aspects of the present disclosure. Method 2900 may be executed by one or more processors, such as a CPU (e.g., 102), a GPU (e.g., 104), and / or other processing units, such as a DSP 106, an NPU 108, an AI core 2440, or a power switch (e.g., 2538a, 2538b, 2538c). In some aspects, method 2900 may include receiving a current specification for a first core device, a voltage specification for the first core device, a first output voltage of a first power supply, a second output voltage of a second power supply, and current ratings of the first and second power supplies as inputs (block 2902). For example, the processing unit may implement a sensor (such as a DPM or EPM) to generate various portions of the inputs. The various portions of the inputs (such as the current specification, voltage specification, and current ratings) may additionally or alternatively be predefined.

[0189] In some aspects, method 2900 may further include: controlling a switch based on an input, the switch selectively coupling a first core device to a first power supply and a second power supply (block 2904). For example, the processing unit may control the switch based on the first power supply and / or the second power supply meeting current specifications and voltage specifications for the first core device, while minimizing power consumption of the first power supply and / or the second power supply. In still other aspects, method 2900 may include: controlling a first output voltage and a second output voltage based on an input (block 2906). For example, the processing unit may change the output voltage of the power supply such that the power supply meets the voltage specifications of the core device.

[0190] Example

[0191] Aspect 1: An apparatus comprising: a plurality of core devices, each core device configured to operate at a plurality of voltage levels; and a power management integrated circuit (PMIC) including a plurality of power supplies, each power supply corresponding to one of the plurality of voltage levels, a first power supply corresponding to a first voltage level among the plurality of power supplies being selectively coupled to a first core device among the plurality of core devices configured to operate at the first voltage level, and a second power supply corresponding to a second voltage level among the plurality of power supplies being selectively coupled to the first core device among the plurality of core devices configured to operate at the second voltage level.

[0192] Aspect 2: The apparatus according to aspect 1 further includes multiple sets of packaged interconnects coupled to each core device, each set of packaged interconnects being coupled to one of the plurality of power supplies.

[0193] Aspect 3: The apparatus according to aspect 1 or 2 further includes a switch that selectively couples the first core device to the first power supply and the second power supply, the switch being located on the PMIC.

[0194] Aspect 4: The apparatus according to any one of Aspect 1 or 2, the apparatus further comprising a switch for selectively coupling the first core device to the first power supply and the second power supply, the switch being located outside the PMIC.

[0195] Aspect 5: The apparatus according to any one of the preceding aspects further includes a switch for selectively coupling the first core device to the first power supply and the second power supply, the switch being located on a die including the plurality of core devices.

[0196] Aspect 6: The apparatus according to any one of the preceding aspects, the apparatus further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch being located on a printed circuit board (PCB) coupled to the PMIC and a die including the plurality of core devices.

[0197] Aspect 7: The apparatus according to any one of the preceding aspects, the apparatus further comprising an artificial intelligence (AI) core coupled to a switch and the PMIC, the switch selectively coupling the first core device to the first power supply and the second power supply, the AI ​​core being configured to control the switch and the PMIC based on receiving current specifications for the first core device, voltage specifications for the first core device, output voltages of the first power supply and the second power supply, and current ratings of the first power supply and the second power supply.

[0198] Aspect 8: The apparatus according to aspects 1 to 3 or 5 to 7, the apparatus further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling component being located on the PMIC.

[0199] Aspect 9: The apparatus according to aspects 1, 2 or 4 to 7, the apparatus further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling component being located outside the PMIC.

[0200] Aspect 10: The apparatus according to any one of the preceding aspects, the apparatus further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling component being located on a die including the plurality of core devices.

[0201] Aspect 11: The apparatus according to any one of the preceding aspects, the apparatus further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the component being located on a printed circuit board (PCB) coupled to the PMIC and a die including the plurality of core devices.

[0202] Aspect 12: The apparatus according to any one of the preceding aspects, the apparatus further comprising an artificial intelligence (AI) core coupled to a switching component and the PMIC, the switching component selectively coupling the first core device to the first power supply and the second power supply, the AI ​​core being configured to control the switching component and the PMIC based on receiving current specifications for the first core device, voltage specifications for the first core device, output voltages of the first power supply and the second power supply, and current ratings of the first power supply and the second power supply.

[0203] Aspect 13: A method comprising: receiving a current specification for a first core device, a voltage specification for the first core device, a first output voltage of a first power supply and a second output voltage of a second power supply, and current ratings of the first power supply and the second power supply as inputs; controlling a switch based on the inputs, the switch selectively coupling the first core device to the first power supply and the second power supply; and controlling the first output voltage and the second output voltage based on the inputs.

[0204] Aspect 14: The method according to aspect 13, the method further comprising: controlling the switch based on the first power supply and / or the second power supply meeting the current specifications for the first core device and the voltage specifications for the first core device, while minimizing the power consumption of the first power supply and / or the second power supply.

[0205] Aspect 15: A method comprising: performing a task on a device having a shared power supply for a plurality of power rails; determining whether current load information of the task is stored in a database; in response to determining that the current load information of the task is not stored in the database, detecting a task-specific peak current level for each of the plurality of power rails, storing the task-specific peak current level for each of the plurality of power rails as current load information in the database, and assigning the shared power supply to a default power rail; in response to determining that the current load information of the task is stored in the database, determining whether any power rail in the plurality of power rails exceeds a limit of the shared power supply for the task; and in response that at least one power rail in the plurality of power rails exceeds the limit of the shared power supply, allocating the shared power supply to one of the plurality of power rails based on machine learning.

[0206] Aspect 16: According to the method of aspect 15, the method further includes: in response to determining that the current load information of the task is not stored in the database, throttling the second power rail until machine learning based on the database is completed.

[0207] Aspect 17: The method according to aspect 15 or 16, wherein the detection of the task-specific peak current level for each of the plurality of power rails is performed via a digital power meter (DPM) or an embedded power meter (EPM).

[0208] Aspect 18: The method according to aspects 15 to 17, wherein the allocation of the shared power to one of the plurality of power rails is based on arbitration among the plurality of power rails, and the shared power is assigned to the selected power rail based on task-based priority.

[0209] Aspect 19: The method according to aspects 15 to 18, wherein the allocation of the shared power source to one of the plurality of power rails is based on arbitration among the plurality of power rails, and the shared power source is assigned to the selected power rail based on database indications.

[0210] Aspect 20: The method according to aspects 15 to 19, wherein the database indication includes the mission-specific peak current level associated with any number of the plurality of power rails.

[0211] According to this disclosure, unless otherwise specified in the context, the term "or" may be interpreted as "and / or". Additionally, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not for others; features not using such language may be interpreted as having such implied meaning unless otherwise specified in the context.

[0212] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, then the functionality, processing unit, technique, or other module described herein may be stored on or transmitted on a computer-readable medium as one or more instructions or code. A computer-readable medium may include computer data storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, such as disks and discs as used herein, including compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks and Blu-ray discs, wherein disks often magnetically reproduce data, while discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0213] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein can refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be fully implemented in one or more circuit or logic elements.

[0214] The techniques disclosed herein can be implemented in a wide variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or IC sets (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but implementation by different hardware units is not necessarily required. Rather, as described above, various units can be combined in any hardware unit or provided by a collection of interoperable hardware units, including one or more processors as described above, along with suitable software and / or firmware.

[0215] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. An apparatus, the apparatus comprising: Multiple core devices, each configured to operate at multiple voltage levels; and A power management integrated circuit (PMIC) includes a plurality of power supplies, each power supply corresponding to one of the plurality of voltage levels, wherein a first power supply corresponding to a first voltage level is selectively coupled to a first core device among the plurality of core devices configured to operate at the first voltage level, and a second power supply corresponding to a second voltage level is selectively coupled to the first core device among the plurality of core devices configured to operate at the second voltage level.

2. The apparatus of claim 1, further comprising a plurality of packaged interconnects coupled to each core device, each packaged interconnect being coupled to one of the plurality of power supplies.

3. The apparatus of claim 1, further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch being located on the PMIC.

4. The apparatus of claim 1, further comprising a switch for selectively coupling the first core device to the first power supply and the second power supply, the switch being located outside the PMIC.

5. The apparatus of claim 1, further comprising a switch for selectively coupling the first core device to the first power supply and the second power supply, the switch being located on a die including the plurality of core devices.

6. The apparatus of claim 1, further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch being located on a printed circuit board (PCB) coupled to the PMIC and a die including the plurality of core devices.

7. The apparatus of claim 1, further comprising an artificial intelligence (AI) core coupled to a switch and the PMIC, the switch selectively coupling the first core device to the first power supply and the second power supply, the AI ​​core being configured to control the switch and the PMIC based on received current specifications for the first core device, voltage specifications for the first core device, output voltages of the first power supply and the second power supply, and current ratings of the first power supply and the second power supply.

8. The apparatus of claim 1, further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling component being located on the PMIC.

9. The apparatus of claim 1, further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling component being located outside the PMIC.

10. The apparatus of claim 1, further comprising means for selectively coupling the first core device to the first power supply and the second power supply, the selective coupling means being located on a die including the plurality of core devices.

11. The apparatus of claim 1, further comprising a component for selectively coupling the first core device to the first power supply and the second power supply, the component being located on a printed circuit board (PCB) coupled to the PMIC and a die including the plurality of core devices.

12. The apparatus of claim 1, further comprising an artificial intelligence (AI) core coupled to a switching component and the PMIC, the switching component selectively coupling the first core device to the first power supply and the second power supply, the AI ​​core being configured to control the switching component and the PMIC based on received current specifications for the first core device, voltage specifications for the first core device, output voltages of the first power supply and the second power supply, and current ratings of the first power supply and the second power supply.

13. A method, the method comprising: The device receives the current specification for the first core device, the voltage specification for the first core device, the first output voltage of the first power supply and the second output voltage of the second power supply, and the current rating of the first power supply and the second power supply as inputs. The input is used to control a switch that selectively couples the first core device to the first power supply and the second power supply. as well as The first output voltage and the second output voltage are controlled based on the input.

14. The method according to claim 13, further comprising: The switch is controlled based on the first power supply and / or the second power supply meeting the current specifications and voltage specifications for the first core device, while minimizing the power consumption of the first power supply and / or the second power supply.

15. A method, the method comprising: Perform tasks on devices with a shared power supply for multiple power rails; Determine whether the current load information for the task is stored in the database; In response to determining that the current load information of the task is not stored in the database, the task-specific peak current level for each of the plurality of power rails is detected, the task-specific peak current level for each of the plurality of power rails is stored as current load information in the database, and the shared power supply is assigned to the default power rail. In response to determining that the current load information for the task is stored in the database, it is determined whether any of the plurality of power rails exceeds the limit of the shared power supply used for the task; as well as In response to at least one of the power rails exceeding the limit of the shared power supply, the shared power supply is allocated to one of the power rails based on machine learning.

16. The method according to claim 15, further comprising: In response to the determination that the current load information for the task is not stored in the database, the second power rail is throttled until machine learning based on the database is completed.

17. The method of claim 15, wherein detecting the task-specific peak current level for each of the plurality of power rails is performed via a digital power meter (DPM) or an embedded power meter (EPM).

18. The method of claim 15, wherein allocating the shared power to one of the plurality of power rails is based on arbitration among the plurality of power rails, and the shared power is assigned to the selected power rail based on task-based priority.

19. The method of claim 15, wherein allocating the shared power source to one of the plurality of power rails is based on arbitration among the plurality of power rails, and the shared power source is assigned to the selected power rail based on a database indication.

20. The method of claim 19, wherein the database indication includes the mission-specific peak current level associated with any number of the plurality of power rails.

Images