Parameter synchronization method and device of inverter parallel system, electronic equipment, storage medium and program product

Abstract

Embodiments of the present application provide a parameter synchronization method and device for an inverter parallel system, electronic equipment, a storage medium and a program product. The method comprises: obtaining a system parameter set to be synchronized by a master inverter; encapsulating the system parameter set into a broadcast data frame according to a preset memory mapping rule, and sending the broadcast data frame to multiple slave inverters through a system communication bus; receiving feedback information sent by the multiple slave inverters, and determining a synchronization result of the multiple slave inverters according to the feedback information; and performing a retransmission and / or protection operation according to the synchronization result, so that the broadcast communication realizes one-time issuance and full-machine reception, and the synchronization time consumption no longer increases linearly with the number of slave inverters. In combination with a closed-loop feedback mechanism, the master inverter can accurately grasp the synchronization state of each slave inverter, the problem of inconsistent master-slave parameters caused by communication packet loss and data distortion is solved, and the risk of inverter circulating current, protection shutdown and equipment damage is reduced.

Description

Technical Field

[0001] This application relates to the field of energy storage technology, and in particular to a parameter synchronization method, device, electronic equipment, storage medium and program product for an inverter parallel system. Background Technology

[0002] An inverter is a converter that converts direct current (DC) to alternating current (AC). In a photovoltaic energy storage system, multiple inverters can be connected in parallel to achieve efficient energy conversion and storage. Multiple inverters need to maintain consistent parameters; otherwise, problems such as device overload damage and current sharing failure may occur, affecting the stability of the energy storage system.

[0003] In the existing technology, the parameter synchronization method of inverter parallel system mainly adopts master-slave polling unidirectional synchronization. By designating one inverter as the master, the master sends parameters to the slave, and the slave receives and synchronizes the parameters.

[0004] However, the parameter synchronization method in the existing technology is an open-loop control method. The host cannot confirm whether the slave has successfully received and parsed the parameters. If packet loss or interference occurs during the communication process, it can easily lead to equipment damage. Summary of the Invention

[0005] This application provides a parameter synchronization method, apparatus, electronic device, storage medium, and program product for an inverter parallel system, in order to reduce the risk of equipment damage that may occur in the prior art.

[0006] In a first aspect, embodiments of this application provide a parameter synchronization method for an inverter parallel system, comprising:

[0007] Obtain the set of system parameters to be synchronized by the host inverter;

[0008] The system parameter set is encapsulated into broadcast data frames according to the preset memory mapping rules and sent to multiple slave inverters through the system communication bus;

[0009] Receive feedback information sent by the multiple slave inverters, and determine the synchronization result of the multiple slave inverters based on the feedback information;

[0010] Perform retransmission and / or protection operations based on the synchronization results.

[0011] In one possible implementation, encapsulating the system parameter set into a broadcast data frame according to a preset memory mapping rule includes: dividing a shared memory mapping region with the same address range in the memory of the master inverter and multiple slave inverters; dividing the shared memory mapping region into multiple sub-segments according to parameter types, wherein the multiple sub-segments correspond to fixed memory offset addresses; querying the corresponding memory offset address according to the parameter type in the system parameter set, writing the parameter value to the corresponding memory offset address; calculating the data content verification value, and generating a broadcast data frame.

[0012] In one possible implementation, receiving feedback information sent by the multiple slave inverters and determining the synchronization result of the multiple slave inverters based on the feedback information includes: collecting feedback frames returned by the multiple slave inverters within a preset feedback receiving window; parsing the receiving status identifier in the feedback frame; establishing a slave inverter synchronization status table based on the receiving status identifier, and recording the synchronization result.

[0013] In one possible implementation, the step of performing retransmission and / or protection operations based on the synchronization result includes: traversing the slave inverter synchronization status table to identify slave inverters that have failed to synchronize and / or have no feedback; generating a directed retransmission data frame based on the slave inverter that has failed to synchronize and / or has no feedback, and sending the directed retransmission data frame to the corresponding slave inverter; receiving a retransmission feedback frame sent by the slave inverter, and updating the synchronization result of the slave inverter in the slave inverter synchronization status table; calculating the number of consecutive retransmissions for multiple slave inverters, and triggering a hierarchical protection mechanism when the number of consecutive retransmissions exceeds a preset threshold.

[0014] In one possible implementation, before triggering the hierarchical protection mechanism, the method further includes: calculating the system synchronization reliability index based on the synchronization results and historical synchronization success rate of each slave inverter in the slave inverter synchronization status table; in response to the system synchronization reliability index being lower than a preset safety threshold, activating the system safety mode; and in the system safety mode, limiting the output power of the slave inverter and increasing the synchronization frequency to a preset emergency synchronization cycle.

[0015] In one possible implementation, after performing retransmission and / or protection operations based on the synchronization result, the method further includes: collecting multi-dimensional datasets of multiple slave inverters during historical synchronization; creating a synchronization prediction model based on the multi-dimensional datasets of the multiple slave inverters to identify synchronization failure modes under various operating conditions; and, in response to the triggering of parameter synchronization, pre-evaluating the synchronization success rate based on the synchronization prediction model, adjusting the communication parameters within the synchronization cycle based on the pre-evaluation results, and switching the synchronization mode to improve the synchronization success rate.

[0016] Secondly, embodiments of this application provide a parameter synchronization device for an inverter parallel system, comprising:

[0017] The acquisition module is used to acquire the set of system parameters to be synchronized by the host inverter;

[0018] The encapsulation module is used to encapsulate the system parameter set into broadcast data frames according to preset memory mapping rules, and send them to multiple slave inverters through the system communication bus;

[0019] A receiving module is used to receive feedback information sent by the multiple slave inverters and determine the synchronization result of the multiple slave inverters based on the feedback information;

[0020] An execution module is used to perform retransmission and / or protection operations based on the synchronization results.

[0021] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0022] The memory stores computer-executed instructions;

[0023] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0024] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0025] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0026] The parameter synchronization method, device, electronic device, storage medium, and program product for inverter parallel systems provided in this application obtain the set of system parameters to be synchronized from the master inverter, encapsulate them into broadcast data frames according to preset memory mapping rules, and send them to the slave inverters via the system communication bus. After receiving feedback information from each slave inverter, the synchronization result is determined, and retransmission and / or protection operations are performed based on the result. Through broadcast communication, a single transmission is received by all devices, and the synchronization time no longer increases linearly with the number of slave inverters. Combined with a closed-loop feedback mechanism, the master inverter can accurately grasp the synchronization status of each slave inverter, solving the problem of inconsistent master and slave parameters caused by communication packet loss and data distortion, and reducing the risk of inverter circulating current, protection shutdown, and equipment damage. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] Figure 1 A schematic diagram illustrating a scenario for the parameter synchronization method of the inverter parallel system provided in this application;

[0029] Figure 2 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 1 ;

[0030] Figure 3 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 2 ;

[0031] Figure 4 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 3 ;

[0032] Figure 5 A schematic diagram of the parameter synchronization device for the inverter parallel system provided in this application;

[0033] Figure 6 A schematic diagram of the structure of the electronic device provided in this application.

[0034] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0036] An inverter is a converter that transforms direct current (DC) into alternating current (AC). In photovoltaic (PV) energy storage systems, multiple inverters operating in parallel can achieve efficient energy conversion and storage. These inverters need to maintain consistent parameters; otherwise, problems such as device overload damage and current sharing failure can easily occur, affecting the stability of the energy storage system. In existing technologies, parameter synchronization in inverter parallel systems mainly employs master-slave polling unidirectional synchronization. One inverter is designated as the master, sending parameters to the slave, which then receives and synchronizes the parameters. However, this existing parameter synchronization method is an open-loop control method. The master cannot confirm whether the slave has successfully received and parsed the parameters. If packet loss or interference occurs during communication, it can easily lead to equipment damage.

[0037] To address the aforementioned technical issues, this application proposes the following technical concept: Considering the pre-created memory mapping rules, the set of system parameters to be synchronized by the master inverter is encapsulated into a broadcast data frame and sent to multiple slave inverters via the system communication bus. The master inverter performs retransmission and / or protection operations based on the synchronization results of the slave inverters.

[0038] Figure 1 A schematic diagram illustrating a scenario for the parameter synchronization method of the inverter parallel system provided in this application, such as... Figure 1 As shown, the specific application scenario of this application includes a master inverter 101 and multiple slave inverters 102.

[0039] Specifically, the master inverter 101 encapsulates the set of system parameters to be synchronized into broadcast data frames according to the preset memory mapping rules, and sends them to multiple slave inverters 102 through the system communication bus. The master inverter 101 receives the feedback information sent by the multiple slave inverters 102, determines the synchronization result according to the feedback information, and performs retransmission and / or protection operations according to the synchronization result.

[0040] Figure 2 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 1 ,like Figure 2 As shown, the method includes:

[0041] S201: Obtain the set of system parameters to be synchronized by the host inverter.

[0042] Specifically, during the operation of the inverter parallel system, the main inverter, as the core control unit, monitors the system operating status, load changes, grid commands and internal protection logic in real time. When it is detected that the operating parameters of all parallel units need to be updated, the main inverter collects the set of system parameters to be synchronized.

[0043] In this embodiment, scenarios for updating the operating parameters of all parallel units include, but are not limited to, sudden changes in load power, grid voltage fluctuations, and receiving new power dispatch instructions.

[0044] In this embodiment, the system parameter set includes, but is not limited to, voltage amplitude, output frequency, voltage phase, active power command, reactive power command, overvoltage protection threshold, undervoltage protection threshold, overcurrent protection threshold, and system control command.

[0045] S202: According to the preset memory mapping rules, the system parameter set is encapsulated into a broadcast data frame and sent to multiple slave inverters through the system communication bus.

[0046] Specifically, the master inverter obtains the set of system parameters to be synchronized, fills the parameter values ​​into the specified data fields according to the predefined memory mapping rules that are consistent between the master inverter and all slave inverters, encapsulates them into broadcast data frames, and sends them to all slave inverters at once through the system communication bus.

[0047] S203: Receive feedback information from multiple slave inverters and determine the synchronization result of multiple slave inverters based on the feedback information.

[0048] Specifically, after the broadcast data frame is sent, the master inverter monitors the feedback information returned by each slave inverter on the communication bus. The master inverter parses the feedback information and determines whether each slave inverter has successfully and correctly received and applied the synchronization parameters.

[0049] S204: Perform retransmission and / or protection operations based on the synchronization results.

[0050] Specifically, after the master inverter completes the determination of the synchronization results of all slave inverters, it performs differentiated operations according to the slave inverter synchronization status table: no intervention is performed on slave inverters that have successfully synchronized; for slave inverters that have failed to synchronize or have no feedback, a retransmission and protection mechanism is initiated.

[0051] As can be seen from the above embodiments, by obtaining the set of system parameters to be synchronized from the master inverter, encapsulating them into broadcast data frames according to preset memory mapping rules, and sending them to the slave inverters via the system communication bus; after receiving feedback information from each slave inverter, determining the synchronization result, and performing retransmission and / or protection operations based on the result, the master inverter achieves one-time transmission and full reception through broadcast communication, and the synchronization time no longer increases linearly with the number of slave inverters; combined with the closed-loop feedback mechanism, the master inverter can accurately grasp the synchronization status of each slave inverter, solving the problem of inconsistent master and slave parameters caused by communication packet loss and data distortion, and reducing the risk of inverter circulating current, protection shutdown and equipment damage.

[0052] In one embodiment of this application, step S202 includes:

[0053] S2021: Divide the memory of the master inverter and multiple slave inverters into a shared memory mapping region with the same address range.

[0054] Specifically, during the system initialization phase, the microcontrollers of both the master inverter and each slave inverter reserve memory spaces with identical address ranges and fixed lengths as dedicated shared areas for parameter synchronization.

[0055] In this embodiment, the address range, size, and functional division of the shared memory mapping region are fixed during system design and uniformly programmed and implemented in the firmware of all inverters.

[0056] S2022: Divide the shared memory mapping region into multiple sub-segments according to parameter type, with each sub-segment corresponding to a fixed memory offset address.

[0057] Specifically, the shared memory mapping region is subdivided into multiple fixed-length sub-segments based on the function, attributes, and update frequency of the parameters, with each sub-segment corresponding to a starting memory offset address.

[0058] In this embodiment, the offset address of each sub-segment is bound to the parameter type it carries.

[0059] In this embodiment, the types of sub-segments include, but are not limited to, real-time operating parameter segments, power command segments, protection threshold segments, and control command segments.

[0060] S2023: Based on the parameter type in the system parameter set, query the corresponding memory offset address and write the parameter value to the corresponding memory offset address.

[0061] Specifically, the host inverter obtains the set of system parameters to be synchronized, iterates through each parameter in the set, queries the defined fixed offset address mapping table according to the type, obtains the memory offset address corresponding to the parameter, and writes the specific parameter value into the data buffer corresponding to the memory offset address.

[0062] S2024: Calculate the data content verification value and generate a broadcast data frame.

[0063] Specifically, after filling all the parameters to be synchronized into the corresponding memory offset address, the host inverter calculates the contents of the data buffer, generates a check value for integrity verification, and encapsulates the check value and the data content to be synchronized into a broadcast data frame according to the protocol format of the communication bus.

[0064] In this embodiment, a cyclic redundancy check algorithm is used to calculate a 32-bit check value.

[0065] In this embodiment, the header of the generated broadcast data frame includes a broadcast identifier, which is used to instruct the slave inverter on the bus to receive the broadcast data frame.

[0066] As can be seen from the above embodiments, by dividing the shared mapping area with the same address range in the memory of the master inverter and all slave inverters, and dividing it into multiple segments with fixed offset addresses according to parameter type, writing the parameter value to the corresponding address, calculating the check code and generating a broadcast frame, the standardized storage of synchronization parameters is realized. The address mapping rules of the master inverter and slave inverters are completely consistent. After receiving the data, the slave inverter can directly write it to the corresponding memory without dynamic addressing, which simplifies the data parsing process and reduces the data frame length and communication bus load.

[0067] In one embodiment of this application, step S203 includes:

[0068] S2031: Collect feedback frames returned by multiple slave inverters within a preset feedback receiving window.

[0069] Specifically, while the host inverter sends out broadcast data frames, it starts a timer inside the host inverter to define a preset duration for receiving feedback, i.e., the feedback receiving window.

[0070] Specifically, during the feedback receiving window, the master inverter continuously monitors the bus and collects feedback frames sent by all slave inverters.

[0071] In this embodiment, the duration of the feedback receiving window is preset according to the baud rate of the communication bus, the data frame length, and the system real-time requirements.

[0072] S2032: Parse the reception status identifier in the feedback frame.

[0073] Specifically, after receiving the feedback frame returned by each slave inverter, the master inverter parses it according to the set frame format and extracts the reception status identifier.

[0074] In this embodiment, the received status identifier is a predefined code used to indicate the synchronization result of the slave inverter with the broadcast parameters.

[0075] S2033: Based on the received status identifier, establish a synchronization status table for the slave inverter and record the synchronization results.

[0076] Specifically, the master inverter sets up a dynamically updated slave inverter synchronization status table in memory. After the feedback receiving window is closed, the master inverter updates the corresponding slave inverter record in the status table one by one according to the parsed feedback information.

[0077] The slave inverter synchronization status table records, but is not limited to, the slave inverter address, synchronization result, number of consecutive retransmissions, and last synchronization time.

[0078] Specifically, for a slave inverter that receives a successful synchronization feedback, the synchronization result is marked as "synchronization successful", and the number of consecutive retransmissions is reset to zero.

[0079] Specifically, for a slave inverter that receives a synchronization failure feedback, the synchronization result is marked as "synchronization failure", and the number of consecutive retransmissions is incremented by 1.

[0080] Specifically, for slave inverters that do not receive any feedback within the feedback receiving window, the synchronization result is marked as "no feedback", and the number of consecutive retransmissions is incremented by 1.

[0081] As can be seen from the above embodiments, by collecting the feedback frames returned by each slave inverter through a feedback receiving window of a preset duration, parsing the receiving status identifier, establishing a slave inverter synchronization status table and recording the synchronization result of each slave inverter, the master inverter can achieve quantitative control over the synchronization status of all slave inverters in the system, transforming the traditional unidirectional synchronization into closed-loop visibility, and solving the defect of existing solutions that cannot confirm whether the slave inverter has correctly received and applied the parameters.

[0082] In one embodiment of this application, step S204 includes:

[0083] S2041: Traverse the slave inverter synchronization status table to identify slave inverters that have failed to synchronize and / or have no feedback.

[0084] Specifically, after the master inverter completes the determination of the synchronization results of all slave inverters, it performs differentiated operations according to the established slave inverter synchronization status table.

[0085] Specifically, no intervention is performed on slave inverters that successfully synchronize; for slave inverters that fail to synchronize or do not provide feedback, a retransmission and protection mechanism is activated.

[0086] S2042: Based on the slave inverter that failed to synchronize and / or had no feedback, generate a directed retransmission data frame and send the directed retransmission data frame to the corresponding slave inverter.

[0087] Specifically, for each identified abnormal slave inverter, the master inverter no longer uses the broadcast method, but instead generates a targeted retransmission data frame.

[0088] In this embodiment, the destination address of the retransmitted data frame points to the faulty slave inverter, and the data within the frame is the same as the parameters broadcast.

[0089] In this embodiment, the directional data frames use the point-to-point communication mode in the communication protocol, and the master inverter sends the directional retransmission frames one by one to the corresponding failed / no feedback slave inverters.

[0090] For example, the point-to-point communication mode is: the CAN bus uses a frame ID that includes the address of the failed / no feedback slave inverter.

[0091] S2043: Receive the retransmission feedback frame sent by the slave inverter and update the synchronization result of the slave inverter in the slave inverter synchronization status table.

[0092] Specifically, after the master inverter sends a directed retransmission frame, it opens a feedback receiving window for the corresponding slave inverter and waits for the slave inverter to return a retransmission feedback frame. After receiving the feedback, the master inverter parses the returned result and updates the corresponding slave status item in the slave inverter's synchronization status table with the updated result.

[0093] S2044: Calculate the number of consecutive retransmissions of multiple slave inverters, and trigger the hierarchical protection mechanism when the number of consecutive retransmissions exceeds a preset threshold.

[0094] Specifically, the master inverter sets a continuous retransmission failure counter for each slave inverter. When the status is updated, if the slave inverter is still in failure status, the corresponding continuous retransmission failure counter is incremented by 1; if the slave inverter is in success status, the counter is cleared to zero.

[0095] Specifically, the master inverter continuously monitors the counter value of each slave inverter. When the number of consecutive retransmissions of any slave inverter exceeds the preset retransmission threshold, it is determined that the slave inverter has a communication failure and triggers the hierarchical protection mechanism.

[0096] In this embodiment, the hierarchical protection mechanism includes, but is not limited to: issuing a communication abnormality alarm for the slave inverter to the host computer or user interface, limiting the maximum allowable output power of the slave inverter through control commands, and controlling the parallel relay of the slave inverter to disconnect.

[0097] As can be seen from the above embodiments, by traversing the slave inverter synchronization status table, slave inverters that have failed to synchronize or have no feedback are identified, and a directed retransmission data frame is generated and sent separately. After receiving retransmission feedback, the status table is updated. At the same time, the number of consecutive retransmissions is counted. When the number of consecutive retransmissions exceeds a preset threshold, hierarchical protection is triggered. For occasional communication interference, automatic retransmission can be performed to avoid synchronization failure caused by a single abnormality. For slave inverters that have continuously failed, hierarchical protection is activated to prevent equipment damage caused by inconsistent parameters.

[0098] Figure 3 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 2 ,like Figure 3As shown, before step S2044, the following steps are also included:

[0099] S301: Calculate the system synchronization reliability index based on the synchronization results of each slave inverter in the slave inverter synchronization status table and the historical synchronization success rate.

[0100] Specifically, the master inverter periodically calculates the historical synchronization success rate of each slave inverter and calculates the system synchronization reliability index based on the system's average success rate.

[0101] S302: In response to the system synchronization reliability index falling below the preset safety threshold, the system safety mode is activated.

[0102] Specifically, the calculated system synchronization reliability index is compared with a preset security threshold. When the reliability index is lower than the security threshold, it indicates that there is an interference source in the communication environment, and the system security mode is activated.

[0103] S303: In system safety mode, limit the output power of the slave inverter and increase the synchronization frequency to the preset emergency synchronization cycle.

[0104] Specifically, after the system safety mode is activated, the master inverter sends a power limiting command to the slave inverters, limiting the output power of all slave inverters to the safe power of the parallel system and increasing the parameter synchronization period.

[0105] For example, the safe power of the parallel system is 50% of the rated power of the parallel system.

[0106] As can be seen from the above embodiments, by calculating the system synchronization reliability index using the slave inverter synchronization status table and historical success rate, and starting the system safety mode when the index is lower than the safety threshold, the output power of the slave inverter is limited and the synchronization frequency is increased to the emergency synchronization cycle in the safety mode. This achieves a quantitative assessment of the overall system synchronization health. Before the frequent synchronization failures of individual slave inverters affect the overall stability, derating and enhanced synchronization measures are taken in advance, thereby improving the safety of the parallel system in scenarios where communication quality deteriorates or interference intensifies.

[0107] Figure 4 Flowchart of the parameter synchronization method for the inverter parallel system provided in this application Figure 3 ,like Figure 4 As shown, after step S204, the following steps are also included:

[0108] S401: Collect multi-dimensional datasets from multiple slave inverters during historical synchronization.

[0109] Specifically, after each synchronization process is completed, the host inverter automatically collects and stores multi-dimensional synchronization data to form a historical dataset.

[0110] In this embodiment, the multi-dimensional dataset includes, but is not limited to, synchronization trigger time, synchronization trigger type, system operating condition type, communication bus load rate, synchronization results of each slave inverter, number of consecutive retransmissions of each slave inverter, ambient temperature and grid voltage fluctuation values.

[0111] S402: Create a synchronization prediction model based on the multi-dimensional dataset of multiple slave inverters to identify synchronization failure modes under various operating conditions.

[0112] Specifically, the main inverter uses a lightweight decision tree algorithm to train a synchronization prediction model offline based on accumulated historical multi-dimensional datasets, and uses the trained synchronization prediction model to identify synchronization failure modes under various operating conditions.

[0113] S403: In response to the triggering of parameter synchronization, the synchronization success rate is pre-evaluated according to the synchronization prediction model, and the communication parameters within the synchronization period are adjusted according to the pre-evaluation results. The synchronization mode is also switched to improve the synchronization success rate.

[0114] For example, when the host receives a parameter synchronization trigger command, it collects the current system operating condition data and communication status data, inputs them into the synchronization prediction model, and obtains the pre-evaluation success rate of this synchronization.

[0115] If the pre-assessment success rate is ≥99%, the regular synchronization mode will be maintained: the synchronization period is 10ms, and a 32-bit cyclic redundancy check algorithm will be used.

[0116] If the pre-assessed success rate is less than 99% (95% ≤ pre-assessed success rate), the communication parameters will be adjusted to shorten the synchronization period to 8ms and increase the number of data frame retransmissions to 2.

[0117] If the pre-assessment success rate is less than 95%, switch to enhanced synchronization mode: shorten the synchronization period to 5ms, use a 64-bit cyclic redundancy check algorithm to improve data verification reliability, and reduce the maximum load rate of the communication bus.

[0118] As can be seen from the above embodiments, by collecting multi-dimensional datasets from historical synchronization processes, a synchronization prediction model is created to identify synchronization failure modes under various working conditions. When parameter synchronization is triggered, the model is used to pre-evaluate the synchronization success rate, and the communication parameters and synchronization mode within the synchronization cycle are dynamically adjusted based on the evaluation results. This enables the system to pre-select appropriate communication strategies based on different working conditions such as load mutations, electromagnetic interference, and communication congestion, thereby improving the synchronization success rate and the system's adaptability to complex field environments.

[0119] Figure 5 A schematic diagram of the parameter synchronization device for the inverter parallel system provided in this application is shown below. Figure 5As shown, the parameter synchronization device 50 of the inverter parallel system provided in this embodiment includes: an acquisition module 501, an encapsulation module 502, a receiving module 503, and an execution module 504.

[0120] The acquisition module 501 is used to acquire the set of system parameters to be synchronized by the host inverter.

[0121] The encapsulation module 502 is used to encapsulate the system parameter set into broadcast data frames according to the preset memory mapping rules, and send them to multiple slave inverters through the system communication bus.

[0122] The receiving module 503 is used to receive feedback information sent by multiple slave inverters and determine the synchronization result of multiple slave inverters based on the feedback information.

[0123] Execution module 504 is used to perform retransmission and / or protection operations based on the synchronization results.

[0124] In one embodiment of this application, the encapsulation module 502 includes:

[0125] The first partitioning unit is used to partition a shared memory mapping region with the same address range in the memory of the master inverter and multiple slave inverters.

[0126] The second partitioning unit is used to divide the shared memory mapping region into multiple sub-segments according to the parameter type, and the multiple sub-segments correspond to fixed memory offset addresses.

[0127] The query unit is used to query the corresponding memory offset address based on the parameter type in the system parameter set, and write the parameter value to the corresponding memory offset address.

[0128] The first calculation unit is used to calculate the data content verification value and generate broadcast data frames.

[0129] In one embodiment of this application, the receiving module 503 includes: a collection unit, used to collect feedback frames returned by multiple slave inverters within a feedback receiving window of a preset duration.

[0130] The parsing unit is used to parse the receive status identifier in the feedback frame.

[0131] The recording unit is used to establish a synchronization status table for the slave inverter based on the received status identifier and to record the synchronization results.

[0132] In one embodiment of this application, the execution module 504 includes:

[0133] The identification unit is used to traverse the slave inverter synchronization status table to identify slave inverters that have failed to synchronize and / or have no feedback.

[0134] The generation unit is used to generate a directed retransmission data frame based on the slave inverter that has failed to synchronize and / or has no feedback, and to send the directed retransmission data frame to the corresponding slave inverter.

[0135] The update unit is used to receive the retransmission feedback frame sent by the slave inverter and update the synchronization result of the slave inverter in the slave inverter synchronization status table.

[0136] The second calculation unit is used to calculate the number of consecutive retransmissions of multiple slave inverters. When the number of consecutive retransmissions exceeds a preset threshold, a hierarchical protection mechanism is triggered.

[0137] In one embodiment of this application, the execution module 504 further includes:

[0138] The third calculation unit is used to calculate the system synchronization reliability index based on the synchronization results of each slave inverter in the slave inverter synchronization status table and the historical synchronization success rate.

[0139] The startup unit is used to initiate the system security mode in response to the system synchronization reliability index falling below a preset security threshold.

[0140] The boosting unit is used to limit the output power of the slave inverter and boost the synchronization frequency to a preset emergency synchronization cycle in the system safety mode.

[0141] In one embodiment of this application, the parameter synchronization device 50 of the inverter parallel system further includes:

[0142] The data acquisition module is used to collect multi-dimensional datasets from multiple slave inverters during the historical synchronization process.

[0143] The identification module is used to create a synchronization prediction model based on a multi-dimensional dataset of multiple slave inverters and to identify synchronization failure modes under various operating conditions.

[0144] The evaluation module is used to respond to the parameter synchronization trigger, pre-evaluate the synchronization success rate based on the synchronization prediction model, adjust the communication parameters within the synchronization period based on the pre-evaluation results, and switch the synchronization mode to improve the synchronization success rate.

[0145] The parameter synchronization device for the inverter parallel system provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0146] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Figure 6As shown, the electronic device 60 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the electronic device 60 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0147] In the specific implementation process, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the parameter synchronization method of the inverter parallel system described above.

[0148] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0149] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0150] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0151] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0152] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the parameter synchronization method of the inverter parallel system described above.

[0153] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the parameter synchronization method of the inverter parallel system described above.

[0154] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0155] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0156] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0157] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0158] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0159] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0160] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0161] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A parameter synchronization method for an inverter parallel system, characterized in that, include: Obtain the set of system parameters to be synchronized by the host inverter; The system parameter set is encapsulated into broadcast data frames according to the preset memory mapping rules and sent to multiple slave inverters through the system communication bus; Receive feedback information sent by the multiple slave inverters, and determine the synchronization result of the multiple slave inverters based on the feedback information; Perform retransmission and / or protection operations based on the synchronization results.

2. The method according to claim 1, characterized in that, The step of encapsulating the system parameter set into broadcast data frames according to preset memory mapping rules includes: In the memory of the master inverter and multiple slave inverters, a shared memory mapping area with the same address range is divided. The shared memory mapping region is divided into multiple sub-segments according to parameter type, and the multiple sub-segments correspond to fixed memory offset addresses; Based on the parameter type in the system parameter set, query the corresponding memory offset address and write the parameter value to the corresponding memory offset address; Calculate the data content verification value and generate a broadcast data frame.

3. The method according to claim 1, characterized in that, The step of receiving feedback information sent by the multiple slave inverters and determining the synchronization result of the multiple slave inverters based on the feedback information includes: Based on a preset feedback receiving window, collect feedback frames returned by multiple slave inverters within the window; Parse the reception status identifier in the feedback frame; Based on the received status identifier, a slave inverter synchronization status table is established, and the synchronization results are recorded.

4. The method according to claim 1, characterized in that, The step of performing retransmission and / or protection operations based on the synchronization result includes: Traverse the slave inverter synchronization status table to identify slave inverters that have failed to synchronize and / or have no feedback. Based on the slave inverter that failed to synchronize and / or had no feedback, a directed retransmission data frame is generated and sent to the corresponding slave inverter. Receive the retransmission feedback frame sent by the slave inverter and update the synchronization result of the slave inverter in the slave inverter synchronization status table; The number of consecutive retransmissions from multiple slave inverters is calculated, and a hierarchical protection mechanism is triggered when the number of consecutive retransmissions exceeds a preset threshold.

5. The method according to claim 4, characterized in that, Before triggering the graded protection mechanism, the following are also included: The system synchronization reliability index is calculated based on the synchronization results and historical synchronization success rate of each slave inverter in the slave inverter synchronization status table. In response to the system synchronization reliability index falling below a preset safety threshold, the system safety mode is activated. In the system safety mode, the output power of the slave inverter is limited, and the synchronization frequency is increased to the preset emergency synchronization cycle.

6. The method according to any one of claims 1 to 5, characterized in that, After performing retransmission and / or protection operations based on the synchronization result, the method further includes: Collect multi-dimensional datasets from multiple slave inverters during historical synchronization; A synchronization prediction model is created based on the multi-dimensional dataset of the multiple slave inverters to identify synchronization failure modes under various operating conditions. In response to the triggering of parameter synchronization, the synchronization success rate is pre-evaluated according to the synchronization prediction model, and the communication parameters within the synchronization period are adjusted according to the pre-evaluation results, and the synchronization mode is switched to improve the synchronization success rate.

7. A parameter synchronization device for an inverter parallel system, characterized in that, include: The acquisition module is used to acquire the set of system parameters to be synchronized by the host inverter; The encapsulation module is used to encapsulate the system parameter set into broadcast data frames according to preset memory mapping rules, and send them to multiple slave inverters through the system communication bus; A receiving module is used to receive feedback information sent by the multiple slave inverters and determine the synchronization result of the multiple slave inverters based on the feedback information; An execution module is used to perform retransmission and / or protection operations based on the synchronization results.

8. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the parameter synchronization method for the inverter parallel system as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the parameter synchronization method for an inverter parallel system as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the parameter synchronization method for the inverter parallel system according to any one of claims 1 to 6.

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