logical channel priority

Abstract

Various aspects of the present disclosure relate to logical channel prioritization. In one aspect, a UE determines a first latency status of data of a first LCH. In turn, the UE prioritizes transmission of the data of the first LCH based on the first latency status of the data of the first LCH.

Description

Technical Field

[0001] This disclosure relates to wireless communications, and more specifically to user equipment (UE) and methods for supporting logical channel priorities. Background Technology

[0002] A wireless communication system may include one or more network communication devices (such as base stations), which may also be referred to as eNodeB (eNB), next-generation NodeB (gNB), or other suitable terms. Each network communication device (such as a base station) may support wireless communication with one or more user communication devices, which may also be referred to as UE or other suitable terms. The wireless communication system may support wireless communication with one or more user communication devices by utilizing the resources of the wireless communication system (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)). Furthermore, the wireless communication system may support wireless communication across a variety of wireless access technologies, including third-generation (3G) wireless access technology, fourth-generation (4G) wireless access technology, fifth-generation (5G) wireless access technology, and other suitable wireless access technologies beyond 5G (e.g., sixth-generation (6G)).

[0003] To enable latency status reporting for buffered data for Extended Reality (XR) services, the UE reports the latency status of buffered data to the base station so that latency-aware scheduling can be performed on the data.

[0004] However, the Logical Channel Prioritization (LCP) process does not consider the delay status of buffered data, but rather the priority of the logical channel. During the MAC PDU assembly process, delay-critical data may not be multiplexed into the Media Access Control (MAC) Protocol Data Unit (PDU) authorized for the uplink (UL), and delay-critical data may be discarded. Therefore, capacity is affected. Summary of the Invention

[0005] This disclosure relates to a UE and a method for supporting logical channel prioritization. This UE and method enable delay-aware logical channel prioritization.

[0006] Some implementations of a UE described herein may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: determine a first delay state of data for a first LCH; and, based on the first delay state of the data for the first LCH, prioritize the transmission of that data. In some implementations, the processor is configured to prioritize the transmission of that data based on the first delay state of the data for the first LCH by prioritizing the transmission of first type data of the first LCH. The first delay state includes a first remaining time for the first type data, the first remaining time of the first type data being less than a remaining time threshold.

[0007] In some implementations, the processor is configured to prioritize data transmission based on a first delay state of the first LCH data by: prioritizing the transmission of the first LCH data over the transmission of the second LCH data, or prioritizing the transmission of a first type of data of the first LCH over the transmission of the second LCH data, or prioritizing the transmission of a first type of data of the first LCH over the transmission of a second type of data of the first LCH, wherein the first delay state includes a second remaining time for the second type of data, the second remaining time for the second type of data being higher than a remaining time threshold.

[0008] In some implementations, the processor is configured to prioritize data transmission based on a first delay state of the first LCH data by: allocating resources for the data of the first LCH and the data of the second LCH in descending order of the priority level of the first LCH and the priority level of the second LCH; or allocating resources for the first type data of the first LCH and the data of the second LCH in descending order of the priority level of the first type data and the priority level of the second LCH; or allocating resources for the first type data of the first LCH and the second type data of the first LCH in descending order of the priority level of the first type data and the priority level of the second type data.

[0009] In some implementations, the processor is configured to prioritize the transmission of data in the first LCH by increasing the first priority level of the first type of data in the first LCH to a target priority level.

[0010] In some implementations, the data in the first LCH also includes second type data, and the first delay state includes a second remaining time for the second type data, the second remaining time of which is higher than a remaining time threshold. In such an implementation, the processor is configured to prioritize the transmission of the data in the first LCH by maintaining a first priority level for the second type data of the first LCH unchanged.

[0011] In some implementations, the processor is configured to prioritize the transmission of data in the first LCH by increasing the priority level of the data in the first LCH to a target priority level.

[0012] In some implementations, the target priority level is higher than one or more priority levels of one or more LCH groups.

[0013] In some implementations, the target priority level is higher than or equal to the third priority level of the third LCH, and a group of one or more LCHs excludes the third LCH.

[0014] In some implementations, the target priority level is lower than the fourth priority level of the fourth LCH.

[0015] In some implementations, the processor is also configured to: determine a second delay state of the data for the fifth LCH. The data for the fifth LCH includes at least first type data, and the second delay state includes a third remaining time for the first type data of the fifth LCH, wherein the third remaining time for the first type data is lower than a remaining time threshold. In such an implementation, the processor is configured to prioritize the transmission of data for the first LCH by: determining that a first priority level of the first LCH is higher than a fifth priority level of the fifth LCH, and prioritizing the transmission of data for the first LCH.

[0016] In some implementations, the processor is configured to prioritize the transmission of data from the first LCH and the fifth LCH by prioritizing the transmission of data from the first LCH and the fifth LCH in descending order of priority level 1 and priority level 3.

[0017] In some implementations, the processor is further configured to: determine a second delay state of the data of the fifth LCH, wherein the data of the fifth LCH includes at least first type data, the second delay state includes a third remaining time of the first type data of the fifth LCH, the third remaining time of the first type data being less than a remaining time threshold; and the processor is configured to prioritize the transmission of the data of the first LCH by prioritizing the transmission of the data of the first LCH and the data of the fifth LCH based on the first remaining time and the third remaining time.

[0018] In some implementations, the processor is configured to prioritize the transmission of data from the first LCH and the fifth LCH by prioritizing the transmission of data from the first LCH and the fifth LCH in ascending order of the first remaining time and the third remaining time.

[0019] In some implementations, the processor is configured to prioritize the transmission of data from the first LCH and the fifth LCH based on the following: first remaining time, third remaining time, first priority level of the first LCH, and fifth priority level of the fifth LCH.

[0020] In some implementations, the processor is configured to prioritize the transmission of data from the first LCH and the fifth LCH by: prioritizing the transmission of data from the first LCH and the fifth LCH in descending order of priority level and then in ascending order of first remaining time and third remaining time; or prioritizing the transmission of data from the first LCH and the fifth LCH in ascending order of first remaining time and third remaining time and then in descending order of priority level and fifth priority level.

[0021] In some implementations, the processor is configured to increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on at least one of the following: an absolute priority value, a priority offset value, or a factor.

[0022] In some implementations, a remaining time threshold is configured for the first LCH or the logical channel group (LCG) that includes the first LCH.

[0023] In some implementations, the processor is configured to prioritize the transmission of data for the first LCH by: prioritizing the transmission of data based on the delay state of the data for the first LCH and the values ​​maintained for the first LCH.

[0024] In some implementations, the processor is also configured to determine the value maintained for the first LCH based on at least one logical channel priority (LCP) configuration for the first LCH.

[0025] In some implementations, at least one LCP configuration includes a dedicated LCP configuration, which includes at least one of the following: second priority bit rate (PBR) or second bucket size duration (BSD).

[0026] In some implementations, at least one LCP configuration also includes a first LCP configuration, which includes a first priority bit rate (PBR) and a first bucket size duration (BSD), with the first PBR separate from the second PBR and the first BSD separate from the second BSD.

[0027] In some implementations, the processor is also configured to: determine a value maintained for the first LCH based on the size of the first type of data in the first LCH. The first latency state includes a first remaining time for the first type of data, where the first remaining time for the first type of data is less than a remaining time threshold.

[0028] In some implementations, the processor is configured to determine the value maintained for the first LCH by: determining the size of the first type of data as the value based on the determination that the value is less than the size of the first type of data.

[0029] In some implementations, the processor is configured to determine the value maintained for the first LCH by: determining the bucket size as the size of the first type of data based on the determination that the size of the first type of data is greater than the bucket size associated with the first LCH; and determining the value maintained for the first LCH based on the bucket size.

[0030] In some implementations, the processor is also configured to: receive configuration for the bucket size associated with the first LCH from the base station via a transceiver; and determine, based on the bucket size, a value maintained for the first LCH.

[0031] In some implementations, the processor is also configured to: determine the bucket size based on a first size of a set of Protocol Data Units (PDUs) including first type data or a second size of a data burst including first type data; and determine a value maintained for a first LCH based on the first size and the second size.

[0032] In some implementations, the processor is configured to prioritize data transmission based on a first delay state of the first LCH data, determined by one of the following: a Protocol Data Unit (PDU) set is configured to be dropped for the Data Radio Bearer (DRB) of the first LCH data; the DRB for the first LCH data is activated by PDU set dropping; the DRB for the first LCH data is deactivated by PDU set dropping; a first type of data in the first LCH has high importance; a PDU set importance (PSI)-based dropping is configured for the DRB of the first LCH data; the DRB for the first LCH data is activated by PSI-based dropping; or the DRB for the first LCH data is deactivated by PSI-based dropping.

[0033] In some implementations, the processor is configured to prioritize data transmission based on a first delay state of the data in the first LCH, regardless of the value maintained for the first LCH.

[0034] In some implementations, the data of the first LCH is the first type of data of the first LCH, and the first delay state includes the first remaining time of the first type of data, which is lower than the remaining time threshold.

[0035] In some implementations, UE 104 sends an indication of whether to prioritize the transmission of data based on the delay status of data from one or more LCHs.

[0036] In some implementations, the processor is also configured to receive a first indication from the base station via a transceiver, the first indication indicating whether to prioritize data transmission based on a first delay state of the data of the first LCH.

[0037] In some implementations, the processor is configured to receive the first instruction via Layer 1, Layer 2, or Layer 3 signaling.

[0038] In some implementations, the processor is configured to receive a first indication and an uplink (UL) grant. In such an implementation, the processor is configured to prioritize the transmission of the data based on a first delay state of the data based on the first LCH: prioritizing the transmission of the data based on determining that the first indication indicates a first delay state of the data based on the first LCH, and prioritizing the transmission of the data based on the UL grant.

[0039] In some implementations, the processor is also configured to receive a second indication from the base station via a transceiver, the second indication indicating whether to activate or deactivate a first delay state of data based on the first LCH to prioritize the transmission of that data.

[0040] Some implementations of a UE described herein may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver, a command from a base station indicating the prioritization of transmission of data for a first LCH; and, based on the command, prioritize the transmission of data for the first LCH.

[0041] In some implementations, this command instructs the prioritization of data transmission for the first LCH by indicating that a first priority level for the first type of data in the first LCH be increased to a target priority level. The first remaining time for the first type of data is below a remaining time threshold.

[0042] In some implementations, the processor is also configured to determine the first remaining time for the first type of data.

[0043] In some implementations, the command indicates that the transmission of the first LCH data should be prioritized by instructing that the priority level of the first LCH data be increased to the target priority level.

[0044] In some implementations, this command indicates information used to determine the priority level of a target.

[0045] In some implementations, this command indicates the target priority level.

[0046] In some implementations, the command indicates the target priority level by specifying one of the following: absolute priority value, priority offset value, or factor.

[0047] Some implementations of a base station described herein may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: receive from the UE via the transceiver an indication of whether to prioritize data transmission based on the delay state of data of one or more LCHs; and transmit to the UE via the transceiver an indication of whether to prioritize data transmission based on the delay state of data of one or more LCHs.

[0048] Some implementations of a method described herein may include: determining a first delay state of data for a first LCH; and prioritizing the transmission of that data based on the first delay state of the data for the first LCH.

[0049] Some implementations of a method described herein may include: receiving from a base station a command indicating that the transmission of data of a first LCH should be prioritized; and prioritizing the transmission of data of the first LCH based on the command.

[0050] Some implementations of a processor described herein may include at least one memory and a controller coupled to the at least one memory and configured such that the controller: determines a first delay state of data of a first LCH; and prioritizes the transmission of the data based on the first delay state of the data of the first LCH.

[0051] Some implementations of a processor described herein may include at least one memory and a controller coupled to the at least one memory and configured such that the controller: receives from a base station a command instructing the transmission of data of a first LCH to be prioritized; and prioritizes the transmission of data of the first LCH based on the command.

[0052] It should be understood that the summary portion is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0053] Figure 1 An example of a wireless communication system supporting logical channel priority according to various aspects of this disclosure is illustrated;

[0054] Figure 2 The illustration shows an example of traditional logical channel priority.

[0055] Figure 3 The diagram illustrates a flowchart of a MAC PDU process for multiplexing logical channels according to various aspects of this disclosure;

[0056] Figure 4 , Figure 5 and Figure 6 Signaling diagrams are illustrated, which illustrate example procedures for supporting logical channel priority according to various aspects of this disclosure;

[0057] Figure 7 The illustration shows an example of a device supporting logical channel priority according to some aspects of this disclosure;

[0058] Figure 8 Examples of processors supporting logical channel priorities according to various aspects of this disclosure are illustrated; and

[0059] Figure 9 and Figure 10 Flowcharts illustrating methods for supporting logical channel priority according to various aspects of this disclosure are provided. Detailed Implementation

[0060] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not constitute any limitation on the scope of this disclosure. The disclosure described herein can be implemented in various ways other than those described below.

[0061] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0062] References to "an embodiment," "an example embodiment," "an embodiment," "some embodiments," etc., in this disclosure indicate that the described embodiments(s) may include a particular feature, structure, or characteristic, but not every embodiment must include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same(s) embodiments(s). Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it should be understood that in conjunction with other embodiments (whether explicitly described or not) affecting such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0063] It should be understood that although the terms “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may also be referred to as a second element without departing from the scope of the embodiments, and similarly, a second element may also be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed terms.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” used herein include the plural forms as well. Furthermore, it should be understood that the terms “comprising,” “including,” “having,” “containing,” and / or “containing,” when used herein, specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0065] Various aspects of this disclosure are described in the context of wireless communication systems.

[0066] Figure 1 An example of a wireless communication system 100 supporting logical channel priority according to various aspects of this disclosure is illustrated. The wireless communication system 100 may include one or more network entities 102 (also referred to as network devices (NEs), one or more terminal devices or UEs 104, a core network 106, and a packet data network 108. The wireless communication system 100 may support various wireless access technologies. In some implementations, the wireless communication system 100 may be a 4G network, such as an LTE network or an Advanced LTE (LTE-A) network. In some other implementations, the wireless communication system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communication system 100 may be a combination of 4G and 5G networks, or other suitable wireless access technologies, including IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), and IEEE 802.20. The wireless communication system 100 may support wireless access technologies other than 5G. Furthermore, the wireless communication system 100 may support technologies such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), or Code Division Multiple Access (CDMA).

[0067] Network entity 102 can be distributed throughout a geographic area to form wireless communication system 100. One or more of the network entities 102 described herein can be, include, or may be referred to as network nodes, base stations (BS), network elements, radio access network (RAN) nodes, base transceiver stations, access points, NodeBs, eNodeBs (eNBs), next-generation NodeBs (gNBs), or other suitable terms. Network entity 102 and UE 104 can communicate via communication link 110, which can be a wireless or wired connection. For example, network entity 102 and UE 104 can perform wireless communication (e.g., receive signaling, send signaling) via a Uu interface. Network entity 102 can be collectively referred to as network entity 102 or referred to as network entity 102 individually. In the following description, some implementations of this disclosure will be described using base stations as an example of network entity 102. Therefore, network entity 102 can be used interchangeably with base station 102.

[0068] Network entity 102 can provide a geographic coverage area 112, and network entity 102 can support services (e.g., voice, video, packet data, messaging, broadcasting, etc.) for one or more UEs 104 within the geographic coverage area 112. For example, network entity 102 and UE 104 can support wireless communication of signals associated with services (e.g., voice, video, packet data, messaging, broadcasting, etc.) according to one or more radio access technologies. In some implementations, network entity 102 can be mobile, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies can overlap, but different geographic coverage areas 112 can be associated with different network entities 102. The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0069] One or more UEs 104 may be distributed throughout the geographic area of ​​the wireless communication system 100. UE 104 may include or be referred to as a mobile device, wireless device, remote device, remote unit, handheld device, subscriber device, or some other suitable term. In some implementations, UE 104 may be referred to as a unit, station, terminal, or client, etc. Alternatively or additionally, UE 104 may be referred to as an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a Machine Type Communication (MTC) device, etc. In some implementations, UE 104 may be stationary within the wireless communication system 100. In some other implementations, UE 104 may be mobile within the wireless communication system 100.

[0070] One or more UEs 104 can be devices of different forms or with different capabilities. Figure 1 The diagram illustrates some examples of UE 104. UE 104 is capable of communicating with various types of devices, such as network entity 102, other UEs 104, or network devices (e.g., core network 106, packet data network 108, relay equipment, integrated access and backhaul (IAB) node, or another network device). Figure 1 As shown. Alternatively or concurrently, UE 104 may support communication with other network entities 102 or UE 104 that may be used as relays in wireless communication system 100.

[0071] UE 104 can also support direct wireless communication with other UE 104s via communication link 114. For example, UE 104 can support direct wireless communication with another UE 104 via a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular V2X deployments, communication link 114 may be referred to as a sidelink. For example, UE 104 can support direct wireless communication with another UE 104 via a PC5 interface.

[0072] Network entity 102 may support communication with core network 106 or with another network entity 102, or both. For example, network entity 102 may interface with core network 106 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Network entities 102 may communicate with each other via backhaul links 116 (e.g., via X2, Xn, or another network interface). In some implementations, network entities 102 may communicate directly with each other (e.g., between network entities 102). In some other implementations, network entities 102 may communicate with each other or indirectly (e.g., via core network 106). In some implementations, one or more network entities 102 may include sub-components, such as access network entities, which may be examples of access node controllers (ANCs). An ANC may communicate with one or more UEs 104 via one or more other access network transport entities (which may be referred to as radio headends, smart radio headends, or transmit-receive points (TRPs)).

[0073] In some implementations, network entity 102 can be configured with a decomposed architecture that can utilize protocol stacks physically or logically distributed across two or more network entities 102, such as an Integrated Access Backhaul (IAB) network, Open RAN (O-RAN) (e.g., a network configuration led by the O-RAN Alliance), or Virtualized RAN (vRAN) (e.g., Cloud RAN (C-RAN)). For example, network entity 102 may include one or more of the following: Central Unit (CU), Distributed Unit (DU), Radio Unit (RU), RAN Intelligent Controller (RIC) (e.g., Near Real-Time RIC, Non-Real-Time RIC), Service Management and Orchestration (SMO) system, or any combination thereof.

[0074] An RU can also be referred to as a radio headend, intelligent radio headend, remote radio headend (RRH), remote radio unit (RRU), or transmit-receive point (TRP). In a decomposed RAN architecture, one or more components of network entity 102 can be co-located, or one or more components of network entity 102 can be located in distributed locations (e.g., separate physical locations). In some implementations, one or more network entities 102 in a decomposed RAN architecture can be implemented as virtual units (e.g., virtual CU (VCU), virtual DU (VDU), virtual RU (VRU)).

[0075] The functional decomposition between CU, DU, and RU can be flexible and can support different functions based on the functions performed at the CU, DU, or RU (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combination thereof). For example, a protocol stack functional decomposition can be used between the CU and DU, allowing the CU to support one or more layers of the protocol stack and the DU to support one or more different layers of the protocol stack. In some implementations, the CU can host upper-layer protocol layer (e.g., Layer 3 (L3), Layer 2 (L2)) functions and signaling (e.g., Radio Resource Control (RRC), Serving Data Adaptation Protocol (SDAP), Packet Data Convergence Protocol (PDCP)). The CU can connect to one or more DUs or RUs, and one or more DUs or RUs can host lower-layer protocol layer functions and signaling, such as Layer 1 (L1) (e.g., Physical (PHY) layer) or L2 (e.g., Radio Link Control (RLC) layer, Media Access Control (MAC) layer), and each can be at least partially controlled by the CU.

[0076] Alternatively, a functional split of the protocol stack can be employed between the DU and RU, allowing the DU to support one or more layers of the protocol stack and the RU to support one or more different layers of the protocol stack. The DU can support one or more different cells (e.g., via one or more RUs). In some implementations, the functional split between the CU and DU or between the DU and RU can be within a protocol layer (e.g., some functions of the protocol layer can be performed by one of the CU, DU, or RU, while other functions of the protocol layer can be performed by another of the CU, DU, or RU).

[0077] The CU can be further functionally divided into CU control plane (CU-CP) and CU user plane (CU-UP) functions. The CU can be connected to one or more DUs via midhaul communication links (e.g., F1, F1-c, F1-u), and the DUs can be connected to one or more RUs via fronthaul communication links (e.g., open fronthaul (FH) interfaces). In some implementations, the midhaul or fronthaul communication links can be implemented based on interfaces (e.g., channels) between layers of a protocol stack supported by the corresponding network entity 102 communicating via such communication links.

[0078] Core network 106 can support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. Core network 106 can be an evolved packet core (EPC) or a 5G core (5GC), which may include control plane entities that manage access and mobility (e.g., Mobility Management Entity (MME), Access and Mobility Management Functions (AMF)) and user plane entities that route packets or interconnect with external networks (e.g., Serving Gateway (S-GW), Packet Data Network (PDN) Gateway (P-GW), or User Plane Functions (UPF)). In some implementations, control plane entities may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signaling bearers, etc.) for one or more UEs 104 served by one or more network entities 102 associated with core network 106.

[0079] Core network 106 can communicate with packet data network 108 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Packet data network 108 may include application server 118. In some implementations, one or more UEs 104 may communicate with application server 118. UE 104 may establish a session (e.g., Protocol Data Unit (PDU) session, etc.) with core network 106 via network entity 102. Core network 106 can use the established session (e.g., an established PDU session) to route services (e.g., control information, data, etc.) between UE 104 and application server 118. A PDU session may be an example of a logical connection between UE 104 and core network 106 (e.g., one or more network functions of core network 106).

[0080] In the wireless communication system 100, network entity 102 and UE 104 can use the resources of the wireless communication system 100 (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communication). In some implementations, network entity 102 and UE 104 can support different resource structures. For example, network entity 102 and UE 104 can support different frame structures. In some implementations, such as in 4G, network entity 102 and UE 104 can support a single frame structure. In some other implementations, such as in 5G and other suitable wireless access technologies, network entity 102 and UE 104 can support various frame structures (i.e., multiple frame structures). Network entity 102 and UE 104 can support various frame structures based on one or more sets of parameters.

[0081] The wireless communication system 100 may support one or more parameter sets, and the parameter sets may include subcarrier spacing and cyclic prefixes. The first parameter set (e.g., μ =0) can be associated with the first subcarrier spacing (e.g., 15 kHz) and the regular cyclic prefix. In some implementations, the first set of parameters (e.g., ) associated with the first subcarrier spacing (e.g., 15 kHz) is... μ =0) can utilize one time slot per subframe. The second parameter set (e.g., μ =1) can be associated with the second subcarrier spacing (e.g., 30 kHz) and the regular cyclic prefix. The third parameter set (e.g., μ =2) can be associated with the third subcarrier spacing (e.g., 60 kHz) and the regular cyclic prefix or extended cyclic prefix. The fourth parameter set (e.g., μ =3) can be associated with the fourth subcarrier spacing (e.g., 120 kHz) and the regular cyclic prefix. The fifth parameter set (e.g., μ=4) can be associated with the fifth subcarrier spacing (e.g., 240 kHz) and the regular cyclic prefix.

[0082] The time intervals of resources (e.g., communication resources) can be organized according to frames (also called radio frames). Each frame can have a duration, for example, 10 milliseconds (ms). In some implementations, each frame can include multiple subframes. For example, each frame can include 10 subframes, and each subframe can have a duration, for example, 1 ms. In some implementations, each frame can have the same duration. In some implementations, each subframe of a frame can have the same duration.

[0083] Alternatively or concurrently, the time intervals of resources (e.g., communication resources) can be organized according to time slots. For example, a subframe may include a certain number (e.g., quantity) of time slots. The number of time slots in each subframe may also depend on one or more parameter sets supported in the wireless communication system 100. For example, a first parameter set, a second parameter set, a third parameter set, a fourth parameter set, and a fifth parameter set (i.e., ...) associated with corresponding subcarrier intervals of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz. μ =0、 μ =1、 μ =2、 μ =3、 μ =4) One time slot per subframe, two time slots per subframe, four time slots per subframe, eight time slots per subframe, and 16 time slots per subframe can be used, respectively. Each time slot can include a certain number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of time slots in a subframe can depend on the parameter set. For a regular cyclic prefix, a time slot can include 14 symbols. For an extended cyclic prefix (e.g., for a 60 kHz subcarrier spacing), a time slot can include 12 symbols. The relationship between the number of symbols per time slot, the number of time slots per subframe, and the number of time slots per frame for both regular and extended cyclic prefixes can depend on the parameter set. It should be understood that for a first parameter set (e.g., quantity) associated with a first subcarrier spacing (e.g., 15 kHz), μ The reference of =0 can be used interchangeably between subframes and time slots.

[0084] In the wireless communication system 100, the electromagnetic (EM) spectrum can be divided into various categories, frequency bands, frequency channels, etc., based on frequency or wavelength. For example, the wireless communication system 100 can support one or more operating frequency bands, such as frequency range identifiers FR1 (410MHz-7.125GHz), FR2 (24.25GHz-52.6GHz), FR3 (7.125GHz-24.25GHz), FR4 (52.6GHz-114.25GHz), FR4a or FR4-1 (52.6GHz-71GHz), and FR5 (114.25GHz-300GHz). In some implementations, network entity 102 and UE 104 can perform wireless communication on one or more operating frequency bands. In some implementations, FR1 can be used by network entity 102 and UE 104, along with other equipment or devices, for cellular communication services (e.g., control information, data). In some implementations, FR2 can be used by network entity 102 and UE 104, along with other equipment or devices, for short-range, high data rate capabilities.

[0085] FR1 can be associated with one or more parameter sets (e.g., at least three parameter sets). For example, FR1 can be associated with the first parameter set (e.g., ...). μ =0), which includes a 15 kHz subcarrier spacing; the second parameter set (e.g., μ =1), which includes a 30 kHz subcarrier spacing; the third parameter set (e.g., μ =2), which includes a subcarrier spacing of 60 kHz. FR2 can be associated with one or more parameter sets (e.g., at least two parameter sets). For example, FR2 can be associated with the following: a third parameter set (e.g., μ =2), which includes a 60 kHz subcarrier spacing; the fourth parameter set (e.g., μ =3), which includes a subcarrier spacing of 120kHz.

[0086] As mentioned above, the Logical Channel Prioritization (LCP) process does not consider the delay status of buffered data, but rather the priority of the logical channel. The delay status of buffered data can include the remaining time of the buffered data. During the MAC PDU assembly process, delay-critical data may not be multiplexed to the UL-licensed MAC PDU, and delay-critical data may be discarded. Therefore, capacity is affected. This will refer to... Figure 2 Describe it.

[0087] Figure 2 An example of a traditional LCP is illustrated. Figure 2In the example, the priority of Logical Channel (LCH) #1 is represented by P1, and the priority of LCH #2 is represented by P2, with P1 being higher than P2. The remaining time for data in LCH #1 is 10ms, and the remaining time for data in LCH #2 is 3ms. The value maintained for LCH #1 (represented by B1) is equal to the Priority Bit Rate (PBR) of 1. T, and the bucket size of LCH#1 (represented by bucket size 1) is equal to PBR 1. Bucket Size Duration (BSD). The value maintained for LCH#2 (denoted by B2) is equal to PBR 2. T.

[0088] Because P1 is higher than P2, the UE can allocate resources for LCH#1 data first, based on UL authorization. In other words, LCH#1 data is first multiplexed to the MAC PDU for UL authorization. If UL authorization is exhausted after LCH#1 data is multiplexed, LCH#2 data will not be multiplexed to the MAC PDU for UL authorization. If the remaining time of LCH#2 data is equal to or less than the threshold, and LCH#2 is not multiplexed to the MAC PDU for transmission in time, LCH#2 data can be discarded.

[0089] Figure 3 A flowchart of a process 300 for multiplexing a logical channel MAC PDU according to various aspects of this disclosure is illustrated.

[0090] In process 300, each LCH j It has a token bucket (also known as a "bucket") and targets LCH. j The value being maintained. For LCH j The value maintained by Bj express.

[0091] The maximum capacity of token bucket 305 is equal to the product PBR × BSD. The size of token bucket 305 is also known as the maximum capacity of token bucket 305.

[0092] Bj This can be used for LCH j The number of tokens in the token bucket. When LCH j When it is established, Bj Initialized to zero. For each LCH j UE 104 should include the following before each instance of the LCP procedure: Bj The increasing product PBR×T, where T is the product of the products ... Bj The time elapsed since the last increase. If Bj If the value is greater than the bucket size (i.e., PBR × BSD), then UE 104 will... Bj Set the bucket size.

[0093] like Figure 3 As shown, at 310, UE 104 injects PBR×T tokens into token bucket 305 for each instance of the LCP process.

[0094] At position 320, UE 104 will Bj The increasing product PBR×T, where T is the product of the products ... Bj The time elapsed since the last increase.

[0095] At position 330, UE 104 is determined. Bj Is it greater than zero?

[0096] if Bj If it is greater than zero, then UE 104 will... Bj Decreasing service for logical channels j Total size of the MAC SDU. Serving logical channels. j The total size of the MAC SDU is represented by Tsdu.

[0097] At 350, UE 104 multiplexes SDU 315 in the MAC PDU.

[0098] At 360, UE 104 determines whether the PBR is satisfied.

[0099] If the PBR is satisfied, UE 104 processes the next LCH at 370.

[0100] If the PBR is not satisfied, procedure 300 continues to box 395. At 395, UE 104 receives packets from the upper layer.

[0101] If UE 104 is determined at 330 Bj If the value is not greater than zero, then UE 104 determines at 380 that there are no available tokens in token bucket 305, and SDU 315 will not be reused in MAC PDU.

[0102] At 390, UE 104 determines that the processing of the LCH is complete, and then the next logical channel with lower priority will be processed.

[0103] In view of the above, this disclosure provides a technical solution supporting logical channel priority. In this solution, the UE determines a first delay state of the data in the first LCH. Then, the UE prioritizes the transmission of the data based on the first delay state of the data in the first LCH. In this way, delay-aware logical channel priority can be implemented.

[0104] The following will refer to Figures 4 to 10 The principles of this disclosure are described.

[0105] Figure 4 A signaling diagram is illustrated, which illustrates an example process 400 supporting logical channel prioritization according to various aspects of this disclosure. For discussion purposes, reference will be made to... Figure 1 Describe process 400. Process 400 may involve... Figure 1 UE 104 and base station 102.

[0106] like Figure 4 As shown, UE 104 determines the first delay state of the data of the first LCH of 410.

[0107] In some implementations, the delay status of LCH data may include the remaining time of a discard timer for data available for transmission on the LCH. For the sake of brevity, "the remaining time of a discard timer for data available for transmission on the LCH" will be referred to as "the remaining time of LCH data".

[0108] In some implementations, the remaining time of the LCH data can be less than a threshold. This threshold will be referred to as the remaining time threshold in the following text.

[0109] In some implementations, the remaining time for LCH data can be the minimum remaining time value of the PDCP discard timer in the Service Data Unit (SDU) of the LCH buffer.

[0110] In some implementations, the remaining time for LCH data can be the minimum remaining time value of the PDCP discard timer in the SDU that includes the logical channel group (LCG) buffer containing LCH.

[0111] Alternatively, in some implementations, the latency status of LCH data may include the total amount of data in the LCH buffer, where the remaining time until the discard timer expires is less than a threshold.

[0112] In some implementations, the data in the LCH may include at least one of the following: • MAC SDUs that have not yet been reused in MAC sub-PDUs; • MAC sub-PDUs not reused in MAC PDUs; • MAC sub-PDUs that have already been reused in MAC PDUs; • RLC SDU and RLC SDU segments not yet included in RLC data PDU; • Waiting for initial transmission and an RLC data PDU containing an RLC SDU or an RLC SDU segment; • RLC data PDUs (RLC AM) awaiting retransmission; • PDCP SDU for which PDCP data PDU has not yet been constructed; • PDCP data PDUs that contain PDCP SDUs but have not yet been submitted to the lower layer; •PDCP controls PDU; • For AM DRB, the PDCP SDU will be retransmitted; or • For AM DRB, PDCP data PDUs will be retransmitted.

[0113] UE 104 prioritizes the transmission of the first data based on the first delay state of the first LCH data.

[0114] In some implementations, the data of the first LCH may include first type data of the first LCH. The first delay state may include a first remaining time of the first type data, and the first remaining time of the first type data is lower than a remaining time threshold. For example, the first remaining time of the first type data is equal to or less than the remaining time threshold. In such an implementation, UE104 may prioritize the transmission of the first type data of the first LCH. For brevity, the first type data will also be referred to as delay-critical data in the following text.

[0115] In some implementations, if pdu-SetDiscard If not configured, then in discardTimer Data with remaining time equal to or less than the remaining time threshold before expiry can be identified as critical delay data.

[0116] In some implementations, if pdu-SetDiscard If configured, at least one piece of data in the PDU set will be in discardTimer Data belonging to the PDU set that is equal to or less than the remaining time threshold before the expiration date can be identified as critical data for delay.

[0117] Process 400 enables delay-aware logical channel prioritization.

[0118] Figure 5 A signaling diagram is illustrated, which shows an example process 500 supporting logical channel priority according to various aspects of this disclosure. Process 500 can be considered as an example implementation of process 400. For purposes of discussion, reference will be made to... Figure 1 Describe process 500. Process 500 may involve... Figure 1 UE 104 and base station 102.

[0119] like Figure 5 As shown, UE 104 determines the first delay state of the first LCH data in step 510. Action 510 is similar to... Figure 4 Action 410. For the sake of brevity, the details of this action have been omitted.

[0120] UE 104 can receive a first indication (520) from base station 102. The first indication can indicate whether to prioritize the transmission of data based on the delay status of data from one or more LCHs. One or more LCHs may include a first LCH.

[0121] In some implementations, UE 104 can receive the first indication via Layer 1 signaling.

[0122] In this implementation, UE 104 can receive the first instruction via downlink control information (DCI).

[0123] For example, the first instruction can be included in a dedicated DCI format.

[0124] For another example, the first indication may be included in an existing or legacy DCI format. For example, an existing or legacy DCI format may include one of the following: DCI format 0-0, DCI format 1-0, DCI format 0-1 or DCI format 1-1, DCI format 2-0, DCI format 2-1, DCI format 2-2, DCI format 2-3, DCI format 2-4, DCI format 2-5 or DCI format 2-6.

[0125] In some implementations, UE 104 may receive a first indication and a UL grant. In such an implementation, if the first indication specifies prioritizing the transmission of data based on a first delay state of the first LCH data, then UE 104 may prioritize the transmission of the first LCH data for the UL grant. For example, the first indication and the UL grant may be included in an existing or legacy DCI format. For example, an existing or legacy DCI format may include one of the following: DCI format 0-0 or DCI format 0-1. Alternatively, the first indication and the UL grant may be included in a dedicated DCI format.

[0126] Alternatively, in some implementations, UE 104 may receive the first indication via Layer 2 signaling. For example, the first indication may be included in a MAC CE. For example, the first indication may be included in one of the following: an RLC control PDU, a PDCP control PDU, or an SDAP control PDU.

[0127] Alternatively, in some implementations, UE 104 may receive the first indication via Layer 3 signaling. For example, the first indication may be included in an RRC message.

[0128] In some implementations, UE 104 can receive LCP configuration from base station 102. The LCP configuration may include a first indication.

[0129] In some implementations, the RRC entity of UE 104 can control the scheduling of uplink data based on the LCP configuration by signaling at least one of the following for each logical channel of each MAC entity: - Priority The increased priority value indicates a lower priority level; - prioritised BitRate It is used to set the PBR; or - bucketSizeDuration It is used to configure BSD.

[0130] In some implementations, the first indication can be configured per LCH. In other words, the first indication can indicate whether to prioritize the transmission of data based on the delay state of the data in the LCH. For example, the first indication can indicate whether to prioritize the transmission of data based on the first delay state of the data in the first LCH.

[0131] In some implementations, the first indication may indicate prioritizing the transmission of all data in the first LCH based on the first delay state of the first LCH.

[0132] Alternatively, in some implementations, the first indication may indicate prioritizing the transmission of a first type of data in the first LCH based on a first delay state of the first LCH.

[0133] In some implementations, the first indication may indicate a remaining time threshold for the first LCH. If the first indication does not indicate a remaining time threshold, UE 104 may use a delay threshold (or remaining time threshold) configured for a delay status report (DSR) triggered for a logical channel group (LCG) that includes the first LCH.

[0134] Alternatively, in some implementations, the first indication can be configured per LCG. In other words, the first indication can indicate whether to prioritize the transmission of data based on the delay state of the data in the LCG. The LCG may include a first LCH.

[0135] In some implementations, the first indication can prioritize the transmission of that data based on the delay status of all data in all LCHs within the LCG.

[0136] Alternatively, in some implementations, the first indication may indicate prioritizing the transmission of data based on the delay status of the first type of data in all LCHs within the LCG. The LCG may include a first LCH.

[0137] In some implementations, the first indication may indicate a remaining time threshold for the LCG. If the first indication does not indicate a remaining time threshold, UE 104 may use a delay threshold (or remaining time threshold) configured for the DSR triggered by the LCG. The LCG may include a first LCH. In some implementations, if UE 104 may use a delay threshold (or remaining time threshold) configured for the DSR triggered by an LCG that includes a first LCH, the UE prioritizes the transmission of first-type data of all LCHs in the LCG associated with the triggered delay state.

[0138] Continue to refer to Figure 5 UE 104 can also receive a second indication from base station 102. The second indication specifies activating a delay state for data based on one or more LCHs to prioritize the transmission of that data. The one or more LCHs may include a first LCH.

[0139] For example, one or more LCHs can be configured to allow prioritizing the transmission of data based on the delay status of the data in one or more LCHs. Alternatively, one or more LCHs can each be configured with a remaining time threshold.

[0140] In some implementations, the second indication may include a bit that indicates the priority of data transmission for UE 104 to activate or trigger one or more LCHs.

[0141] In some implementations, the second indication may include a bitmap that indicates the priority of data transmission for UE 104 to activate or trigger one or more LCHs. Each bit in the bitmap may be associated with one of the one or more LCHs.

[0142] Furthermore, UE 104 can prioritize the transmission of the first LCH data based on a first delay state of the first LCH data. For example, UE 104 can prioritize the transmission of the first LCH data based on a first delay state and a second indication of the data.

[0143] Then, in some implementations, UE 104 may also receive a second indication from base station 102, the second indication indicating to deactivate the delay state of data based on one or more LCHs to prioritize the transmission of that data. In such an embodiment, UE 104 may use, at least for delay-critical data of the LCH, in descending order of configured priority levels. Bj Allocate resources to the LCH selected by UL.

[0144] In some implementations, UE 104 can prioritize the transmission of data from the first LCH over the transmission of data from the second LCH. In such an implementation, UE 104 can allocate resources for the data from the first LCH and the second LCH in descending order of their priority levels, where the first LCH has a higher priority level than the second LCH. In other words, UE 104 can allocate resources for the data from the first LCH before allocating resources for the data from the second LCH.

[0145] In some implementations, the priority level of the LCH can indicate the priority level used to allocate resources for the data in the LCH. In the following text, the term "priority" may be used interchangeably with the term "priority level." An increase in priority can indicate a lower priority level. Alternatively, an increase in priority level can indicate a higher priority level.

[0146] Alternatively, in some implementations, UE 104 may prioritize the transmission of first type data of the first LCH over the transmission of data of the second LCH. In such an implementation, UE 104 may allocate resources for the first type data of the first LCH and the data of the second LCH in descending order of the first priority level of the first type data and the priority level of the second LCH. In other words, UE 104 may allocate resources for the first type data of the first LCH before allocating resources for the data of the second LCH.

[0147] Alternatively, in some implementations, UE 104 may prioritize the transmission of first type data of the first LCH over the transmission of second type data of the first LCH. A first delay state of the first LCH data may include a second remaining time for the second type data. The second remaining time for the second type data is equal to or greater than a remaining time threshold. Hereinafter, the second type data is also referred to as non-delay-critical data, or as data unrelated to the triggered delay state report. In such an implementation, UE 104 may allocate resources for the first type data and the second type data of the first LCH in descending order of the first priority level of the first type data and the second priority level of the second type data. In other words, UE 104 may allocate resources for the first type data of the first LCH before allocating resources for the second type data of the first LCH.

[0148] In some implementations, the buffered data of the second LCH may not be associated with the triggered DSR. In such implementations, the second LCH may be an LCH without delayed critical data. In some implementations, the second LCH may not be configured with a delay threshold (or remaining time threshold) to determine the data delay status. In some implementations, the second LCH is not allowed to trigger DSR.

[0149] Alternatively, the second LCH can be associated with the triggered DSR, and the remaining time of the data in the second LCH can be equal to or greater than a remaining time threshold. In such an implementation, the second LCH can be an LCH with non-delay-critical data. That is, the second LCH has buffered data with remaining time less than the remaining time threshold and data with remaining time equal to or greater than the remaining time threshold.

[0150] In some implementations, UE 104 can prioritize the transmission of data in the first LCH by increasing the first priority level of the first type of data in the first LCH to the target priority level.

[0151] In some implementations, UE 104 may increase the priority level of the first type of data in the first LCH during the first round of resource allocation. For example, before UE 104 can allocate resources to logical channels selected by UL grants (Bj>0) in descending priority order, UE 104 may first increase the priority level of the first type of data in the first LCH. Alternatively, UE 104 may increase the priority level of the first type of data in the first LCH during the second round of resource allocation. For example, after UE 104 can allocate resources to logical channels selected by UL grants (Bj>0) in descending priority order, UE 104 may first increase the priority level of the first type of data in the first LCH. In some implementations, during the first round of resource allocation, UE 104 allocates resources for each LCH j based on Bj.

[0152] In some implementations, during the second round of resource allocation, UE 104 allocates resources for each LCH j, regardless of Bj.

[0153] In some implementations, UE 104 may first increase the priority level of the first type of data in the first LCH. UE 104 may first allocate resources to logical channels with delay-critical data (Bj>0) under UL authorization, in descending order of priority, decrementing Bj by the total size of the MAC SDU serving logical channel j. Furthermore, if any resources remain, UE 104 may also first allocate resources to logical channels with non-delay-critical data (Bj>0) under UL authorization, in descending order of priority, decrementing Bj by the total size of the MAC SDU serving logical channel j. In some implementations, UE 104 may allocate resources to logical channels selected under UL authorization (Bj>0) in descending order of priority, decrementing Bj by the total size of the MAC SDU serving logical channel j. If any resources remain, UE 104 may increase the priority level of the first type of data in the first LCH. The selected logical channel is served in a strict order of first delayed critical data and then non-delayed critical data (regardless of the value of Bj) until the data or UL authorization of that logical channel is exhausted, whichever comes first. If there are more than one LCH with delayed critical data, the logical channels with delayed critical data are served in either a strict descending priority order or a strict ascending order of remaining time value.

[0154] In some implementations, an increased priority value can indicate a lower priority level. In such an implementation, UE104 can increase the first priority level of the first type of data in the first LCH by decreasing the priority value of the first type of data in the first LCH.

[0155] Alternatively, an increased priority value can indicate a higher priority level. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH by increasing the priority value of the first type of data in the first LCH.

[0156] In some implementations, UE 104 may increase only the first priority level of the first type of data in the first LCH to the target priority level, while keeping the priority level of the second type of data in the first LCH unchanged.

[0157] Consider the first example. In the first example, LCH#1 has a priority level of 1 (represented by priority 1), LCH#2 has a priority level of 2 (represented by priority 2), LCH#3 has a priority level of 3 (represented by priority 3), and LCH#4 has a priority level of 4 (represented by priority 4). Priority 1 is higher than priority 2, priority 2 is higher than priority 3, and priority 3 is higher than priority 4. In other words, the value of priority 1 < the value of priority 2 < the value of priority 3 < the value of priority 4.

[0158] In the first example, LCH#2 has delayed critical data and non-delayed critical data. LCH#3 has both delayed and non-delayed critical data. LCH#1 and LCH#4 have no delayed critical data. That is, LCH#2 and LCH#3 are LCHs with delayed critical data, LCH#2 and LCH#3 are LCHs with non-delayed critical data, LCH#1 and LCH#4 are LCHs without delayed critical data, and LCH#1 and LCH#4 are LCHs with non-delayed critical data.

[0159] To prioritize the transmission of delayed critical data for LCH#2 and LCH#3, UE 104 can increase the priority level of the delayed critical data for LCH#2 and LCH#3 while keeping the priority level of the non-delayed critical data for LCH#2 and LCH#3 unchanged. Therefore, the priority level of the non-delayed critical data for LCH#2 remains equal to priority 2, and the priority level of the non-delayed critical data for LCH#3 remains equal to priority 3.

[0160] Therefore, UE 104 can first allocate resources for the delayed critical data of LCH#2 and LCH#3. Then, UE 104 can allocate resources for the data of LCH#1, the non-delayed critical data of LCH#2, the non-delayed critical data of LCH#3, and the data of LCH#4 in descending order of priority 1, priority 2, priority 3, and priority 4.

[0161] In the first example, UE 104 can perform the procedures shown in Table 1 below. Table 1

[0162] In some implementations, UE 104 can prioritize the transmission of data in the first LCH by increasing the priority level of the data in the first LCH to a target priority level. In other words, UE 104 can prioritize the transmission of data in the first LCH by increasing the priority level of all data in the first LCH to a target priority level. That is, if the first LCH has delay-critical data and non-delay-critical data, the priority levels of both the delay-critical data and non-delay-critical data can be increased.

[0163] In some implementations, UE 104 can increase the priority level of all data in the first LCH during the first round of resource allocation. For example, UE 104 can first increase the priority level of all data in the first LCH, and then UE 104 can allocate resources to logical channels selected by UL grants with Bj>0 in descending priority order. Alternatively, UE 104 can increase the priority level of all data in the first LCH during the second round of resource allocation. For example, after UE 104 can allocate resources to logical channels selected by UL grants with Bj>0 in descending priority order, UE 104 can first increase the priority level of all data in the first LCH, and then UE 104 can allocate resources to logical channels selected by UL grants with Bj>0 in descending priority order.

[0164] In some implementations, UE 104 can allocate resources to logical channels selected for UL grants (Bj > 0) in descending priority order, decrementing Bj by the total size of the MAC SDU serving logical channel j, and increasing the priority level of all data in the first LCH. If any resources remain, all selected logical channels are served in strict descending priority order (regardless of the value of Bj) until the data or UL grant for that logical channel is exhausted, on the first available basis. UE 104 can increase the priority level of all data in the first LCH after the first round of resource allocation.

[0165] Consider the second example. In the second example, LCH#1 has a priority level of 1 (represented by priority 1), LCH#2 has a priority level of 2 (represented by priority 2), LCH#3 has a priority level of 3 (represented by priority 3), and LCH#4 has a priority level of 4 (represented by priority 4). Priority 1 is higher than priority 2, priority 2 is higher than priority 3, and priority 3 is higher than priority 4. In other words, the value of priority 1 < the value of priority 2 < the value of priority 3 < the value of priority 4.

[0166] In the second example, LCH#2 has delayed critical data and non-delayed critical data. LCH#3 has both delayed and non-delayed critical data. LCH#1 and LCH#4 have no delayed critical data. That is, LCH#2 and LCH#3 are LCHs with delayed critical data, LCH#1 and LCH#4 are LCHs without delayed critical data, and LCH#1 and LCH#4 are LCHs with non-delayed critical data.

[0167] The second example differs from the first example in that, in order to prioritize the transmission of data for LCH#2 and LCH#3, UE 104 can increase the priority level of all data for LCH#2 and LCH#3, making the priority level of all data for LCH#2 and LCH#3 higher than the priority level of all data for LCH#1 and LCH#4.

[0168] Therefore, UE 104 can first allocate resources for all data in LCH#2 and LCH#3. Then, UE 104 can allocate resources for data in LCH#1 and LCH#4 in descending order of priority 1 and priority 4. In other words, UE 104 can classify LCH#2 and LCH#3 into a first group of LCHs with delay-critical data, and classify LCH#1 and LCH#4 into a second group of LCHs without delay-critical data. UE 104 can allocate resources for the data in the order of first group of LCHs with delay-critical data, followed by second group of LCHs without delay-critical data.

[0169] In the second example, UE 104 can perform the procedures shown in Table 2 below. Table 2

[0170] In some implementations, if multiple LCHs have Bj If the latency critical data is greater than 0, then UE 104 can further prioritize the transmission of data from one or more LCHs based on the target logical channel priority of multiple LCHs.

[0171] In some implementations, if multiple LCHs have Bj If the latency critical data is greater than 0, then UE 104 can further prioritize the transmission of data from one or more LCHs based on the original logical channel priority of multiple LCHs.

[0172] For example, both the first LCH and the fifth LCH have Bj Delay critical data >0. UE 104 can prioritize the transmission of data in the first LCH and the fifth LCH in descending order of priority level of the first LCH and the fifth LCH.

[0173] If the priority level of the first LCH is higher than the priority level of the fifth LCH, then UE 104 may prioritize the transmission of data from the first LCH. If the priority level of the first LCH is lower than the priority level of the fifth LCH, then UE 104 may prioritize the transmission of data from the fifth LCH. The priority levels of the first LCH and the fifth LCH may be the original logical channel priorities or additional logical channel priorities.

[0174] Consider the third example. In the third example, LCH#1 has a priority level of 1 (represented by priority 1), LCH#2 has a priority level of 2 (represented by priority 2), LCH#3 has a priority level of 3 (represented by priority 3), and LCH#4 has a priority level of 4 (represented by priority 4). Priority 1 is higher than priority 2, priority 2 is higher than priority 3, and priority 3 is higher than priority 4. In other words, the value of priority 1 < the value of priority 2 < the value of priority 3 < the value of priority 4.

[0175] In the third example, LCH#2 has delayed key data, and LCH#3 has delayed key data. LCH#1 and LCH#4 do not have delayed key data. That is, LCH#2 and LCH#3 are LCHs with delayed key data, and LCH#1 and LCH#4 are LCHs without delayed key data.

[0176] To prioritize the transmission of data for LCH#2 and LCH#3, UE 104 can increase the priority level of all data for LCH#2 and LCH#3.

[0177] Therefore, UE 104 can first allocate resources for all data in LCH#2 and LCH#3. Because the original logical channel priority of LCH#2 (i.e., priority 2) is higher than that of LCH#3 (i.e., priority 3), UE 104 can allocate resources for all data in LCH#2 and LCH#3 in descending order of priority 2 and priority 3. In other words, UE 104 can first allocate resources for all data in LCH#2, and then allocate resources for all data in LCH#3.

[0178] Then, UE 104 can allocate resources for the data of LCH#1 and LCH#4 in descending order of priority 1 and priority 4.

[0179] In the third example, UE 104 can perform the procedures shown in Table 3 below. Table 3

[0180] In some implementations, if multiple LCHs have Bj If the latency critical data is greater than 0, then UE 104 can further prioritize the transmission of data from one or more LCHs based on the remaining time of the data from multiple LCHs.

[0181] For example, both the first LCH and the fifth LCH have BjDelay critical data >0. UE 104 can prioritize the transmission of data from the first LCH and the fifth LCH in ascending order of the remaining time of the first LCH data. For example, if the remaining time of the first LCH data is 2ms and the remaining time of the fifth LCH data is 4ms, UE 104 can prioritize the transmission of the first LCH data.

[0182] In some implementations, if multiple LCHs have Bj If the delay critical data is greater than 0, then UE 104 can further prioritize the transmission of data from one or more LCHs based on the remaining time of the data from multiple LCHs and the original logical channel priority of the multiple LCHs.

[0183] For example, UE 104 may first prioritize the transmission of data for one or more LCHs in descending order of their priority levels, and then prioritize the transmission of data for one or more LCHs in ascending order of the remaining time of their data.

[0184] Alternatively, UE 104 may first prioritize the transmission of data for one or more LCHs in ascending order of the remaining time of the data for one or more LCHs, and then prioritize the transmission of data for one or more LCHs in descending order of the priority level of the one or more LCHs.

[0185] As described above, in some implementations, UE 104 can prioritize the transmission of data in the first LCH by increasing the first priority level of the first type of data in the first LCH to the target priority level.

[0186] In some implementations, the target priority level is higher than one or more priority levels of one or more LCH groups.

[0187] In some implementations, each LCH in one or more LCHs within the group may not be associated with the triggered DSR. In such implementations, each LCH in one or more LCHs within the group may be an LCH without delayed critical data.

[0188] Alternatively, each LCH in one or more LCHs within the group can be associated with a triggered DSR, and the remaining time of data for each LCH in one or more LCHs within the group can be equal to or greater than a remaining time threshold. In such an implementation, each LCH in one or more LCHs within the group can be an LCH with non-delay-critical data.

[0189] In some implementations, the target priority level is higher than or equal to the third priority level of the third LCH, and a group of one or more LCHs does not include the third LCH. In such an implementation, even if the increased priority level (i.e., the target priority level) of the delay-critical data of the first LCH is equal to or higher than the original priority of the third LCH configured or indicated by base station 102, UE 104 may still consider the original priority of the third LCH to be higher than the target priority level of the delay-critical data. Therefore, UE 104 will not prioritize the transmission of the delay-critical data of the first LCH over the transmission of data or signaling of the third LCH.

[0190] In some implementations, the third LCH may include an LCH having at least one signaling radio bearer (SRB). The at least one SRB may include at least one of the following: SRB0, SRB1, SRB2, SRB3, or SRB4.

[0191] In some implementations, the third LCH can be configured or indicated by base station 102, or predefined.

[0192] In some implementations, the target priority level is lower than the fourth priority level of the fourth LCH. In some implementations, the fourth LCH may not have delayed critical data, but it may contain important data.

[0193] For example, LCH#1 is configured with priority 1 by base station 102, and LCH#2 is configured with priority 2 by base station 102, where priority 1 > priority 2. LCH#1 contains very important data. For example, LCH#1 has some RRC signaling but no delay-critical data. LCH#2 has delay-critical data. Therefore, the original priority of the data in LCH#2 is equal to priority 2. Even if LCH#2 has delay-critical data and LCH#1 does not, UE 104 may not increase the priority level of the data in LCH#2 (i.e., priority 2) to a target priority level higher than the priority of LCH#1 (i.e., priority 1). Therefore, the increased priority level is limited to a certain range.

[0194] In some implementations, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on an absolute priority value. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH to an absolute priority value. For example, the absolute priority value can be the absolute priority value of the first type of data.

[0195] In some implementations, the absolute priority can be configured by base station 102 or predefined.

[0196] Alternatively or additionally, in some implementations, UE 104 may increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on a priority offset value. In such an implementation, UE 104 may increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH by a priority offset value. For example, the priority offset value may be the priority offset value of the first type of data.

[0197] In some implementations, the priority offset value can be configured by the base station 102 or predefined.

[0198] Alternatively or additionally, in some implementations, UE 104 may increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on a factor. For example, UE 104 may determine the target priority level based on the following: floor (factor) (First priority level), where "floor" indicates a floor operation. This factor can be a factor of type 1 data.

[0199] Alternatively or additionally, in some implementations, UE 104 may increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on the mapping between the factor and the remaining time of the first type of data. The mapping between the factor and the remaining time may be configured by base station 102.

[0200] In some implementations, UE 104 may receive Layer 1, Layer 2, or Layer 3 signaling, which includes at least one of the following: an absolute priority value, a priority offset value, or a factor.

[0201] In some implementations, such as Figure 5 As shown, UE 104 can determine the value maintained by 540 for the first LCH. Furthermore, UE 104 can prioritize the transmission of the data based on the delay state of the data in the first LCH and the value maintained for the first LCH. As used herein, for LCH... j The value maintained by Bj express.

[0202] In the following text, it will be used for LCH j of Bj Let's take the determination of the value maintained by the first LCH as an example to describe some implementations.

[0203] In some implementations, UE 104 can be based on LCH. j At least one LCP configuration to determine Bj .

[0204] In some implementations, at least one LCP configuration includes a dedicated or new LCP configuration, and the dedicated LCP configuration includes at least one of the following: a second PBR or a second BSD.

[0205] In some implementations, at least one LCP configuration also includes a first or conventional LCP configuration, and the first LCP configuration includes a first PBR and a first BSD. The first PBR is separate from the second PBR, and the first BSD is separate from the second BSD.

[0206] In some implementations, UE 104 can determine the first or legacy LCP configuration based on the first PBR and the first BSD. Bj For example, UE 104 will... Bj Incrementing PBR×T, where T is the number of increments. Bj The time elapsed since the last increment. UE 104 determines this based on the bucket size. Bj Where the bucket size = first PBR × first BSD. If Bj If the value is greater than the bucket size (i.e., PBR × BSD), then UE 104 will... Bj Set the bucket size.

[0207] Alternatively, in some implementations, UE 104 can determine based on either a dedicated LCP configuration or a new LCP configuration. Bj For example, UE 104 will... Bj Incrementing the second PBR×T, where T is the number of PBRs. Bj The time elapsed since the last increment. The PBR can be either the first PBR or the second PBR. The UE determines this based on the bucket size. Bj Where the bucket size = second PBR × second BSD. If Bj If the value is greater than the bucket size (i.e., PBR × BSD), then UE 104 will... Bj Set the bucket size.

[0208] Alternatively, in some implementations, UE 104 can determine based on the dedicated LCP configuration and the first LCP configuration. Bj For example, UE 104 will... Bj Incrementing the second PBR×T, where T is the number of PBRs. Bj The time elapsed since the last increment. The PBR can be either the first PBR or the second PBR. UE 104 determines the bucket size. For example, bucket size = first PBR. Second BSD, or bucket size = second PBR First BSD.

[0209] Table 4 provides the following information: BjSome examples of determining the size of the bucket. Table 4

[0210] Alternatively, in some implementations, UE 104 can be based on LCH. j The size of the delay key data determines Bj .

[0211] In some implementations, if Bj If the value is less than the size of the delay critical data, then UE 104 can... Bj The size of the data that is critical to the delay is determined. In other words, UE 104 can... Bj Increase the size of the delay-critical data. For example, UE 104 can perform the process shown in Table 5. Table 5

[0212] In some implementations, if the size of the delayed critical data is greater than that of the LCH j Given the associated bucket size, UE 104 can determine the size of the delay-critical data based on the bucket size. Furthermore, UE 104 can determine... Bj In such an implementation, UE 104 can increase the bucket size to the size of the delayed critical data. For example, UE 104 can perform the procedures shown in Table 6. Table 6

[0213] In some implementations, if Bj Smaller than the size of the delayed critical data, and with LCH j If the associated bucket size is smaller than the size of the delay-critical data, then UE 104 can... Bj The size of the delay-critical data is determined, and the bucket size is determined as the size of the delay-critical data. For example, UE 104 can perform the procedure shown in Table 7. Table 7

[0214] In some implementations, UE 104 can receive data from base station 102 for communication with the LCH. j The associated bucket size configuration. Therefore, UE 104 can determine the bucket size based on the bucket size. Bj In this implementation, the bucket size is also referred to as the individual bucket size.

[0215] In some implementations, UE 104 can receive LCP configuration, including a separate bucket size, from base station 102.

[0216] In some implementations, a separate bucket size can be configured for each LCH, DRB, or QoS flow. UE 104 can determine the bucket size based on this individual bucket size. Bj .

[0217] In some implementations, a separate bucket size can be configured for the LCH. For example, the LCH can hold data from a PDU set or a data burst.

[0218] In some implementations, separate bucket sizes can be configured for high-importance PDU sets and low-importance PDU sets.

[0219] For example, when the LCH is established, the MAC entity of UE 104 should send the LCH to the MAC entity of UE 104. Bj Initialize to a single bucket size.

[0220] For another example, for each LCH j The MAC entity should submit the necessary information before each instance of the LCP process. Bj The increasing product PBR×T, where T is the product of the products ... Bj The time elapsed since the last increase. If Bj Larger than the size of a single bucket, and optionally, if an LCH exists. j If the critical data is delayed, the MAC entity will... Bj Set to a separate bucket size.

[0221] In some implementations, UE 104 can determine the bucket size based on a first size of the PDU set including latency-critical data or a second size of the data burst including latency-critical data. Furthermore, UE 104 can determine the bucket size based on the first size and the second size. Bj For example, if LCH j If the UE 104 has latency-critical data, it can determine the latency based on either the first size of the PDU set or the second size of the data burst. Bj .

[0222] In some implementations, if the first size of the PDU set or the second size of the data burst is greater than the bucket size, UE104 can set the bucket size to the first size of the PDU set or the second size of the data burst.

[0223] In some implementations, if the data radio bearer (DRB) for the data of the first LCH is configured with PDU set drop, then UE 104 can prioritize the transmission of the data based on the first delay state of the data of the first LCH.

[0224] In some implementations, if the DRB for discarding data for the first LCH is activated in the PDU set, the UE 104 can prioritize the transmission of the data based on the first delay state of the data for the first LCH.

[0225] In some implementations, if the DRB for the data dropped by the PDU set for the first LCH is deactivated, the UE 104 can prioritize the transmission of the data based on the first delay state of the data for the first LCH.

[0226] In some implementations, if the first type of data in the first LCH is of high importance, the UE 104 may prioritize the transmission of that data based on the first delay state of the data in the first LCH.

[0227] In some implementations, if the DRB for the data of the first LCH is configured with drop based on PDU set importance (PSI), then UE 104 can prioritize the transmission of the data based on the first delay state of the data of the first LCH.

[0228] In some implementations, if the DRB for dropping data for the first LCH based on PSI is activated, UE 104 can prioritize the transmission of the data based on the first delay state of the data for the first LCH.

[0229] In some implementations, if the DRB for dropping data for the first LCH based on PSI is deactivated, UE 104 can prioritize the transmission of the data based on the first delay state of the data for the first LCH.

[0230] In some implementations, UE 104 can prioritize the transmission of the first LCH data based on a first delay state, regardless of the value maintained for the first LCH. In such an implementation, during the second round of resource allocation, UE 104 can either increase the first priority level of the first type of data in the first LCH to a target priority level, or increase the priority level of the first LCH data to a target priority level. Then, UE 104 can allocate resources to the logical channels selected by the UL grant in descending order of priority. The timing of the priority increase can be configured by base station 102. As described above, the implementation of increasing the first priority level of the first type of data or the priority level of the first LCH data can be applied to such implementations.

[0231] In some implementations, regardless of whether UE 104 increases the priority level for data with at least a remaining time below a remaining time threshold, UE 104 can maximize the transmission of at least delayed critical data during the allocation of resources to the logical channel selected by UE 104 in the UL authorization. This enhancement to the implementation can be configured by base station 102.

[0232] In some implementations, based on Bj UE 104 allocates resources to the logical channels selected by the UL grant in descending order of priority. As described above... Bj Some definite implementations.

[0233] In some implementations, if delay-critical data can be incorporated into the resources of the associated MAC entity, UE 104 may, during the allocation of resources to the logical channel selected by the UL authorization, prioritize the transmission of at least delay-critical data over non-delay-critical data as much as possible. This enhancement to the implementation can be configured by base station 102.

[0234] In some implementations, in having Bj During the first round of resource allocation for the LCH, if delay-critical data for the LCH exists, UE 104 should allocate resources for at least the delay-critical data that can be transmitted on the logical channel before satisfying the PBR of (multiple) lower-priority logical channels. That is, regardless of the LCH's priority... Bj In any case, UE 104 should allocate resources to all latency-critical data of the LCH or all data of the LCH containing latency-critical data as much as possible. For example, UE 104 can perform the procedures shown in Table 8. Table 8

[0235] Figure 6 A signaling diagram is illustrated, which illustrates an example process 600 supporting logical channel prioritization according to various aspects of this disclosure. For discussion purposes, reference will be made to... Figure 1 Describe process 600. Process 600 may involve... Figure 1 UE 104 and base station 102.

[0236] like Figure 6 As shown, UE 104 receives a command from base station 102 610 indicating that the transmission of data of the first LCH should be prioritized.

[0237] In some implementations, UE 104 can receive the command via Layer 1, Layer 2, or Layer 3 signaling.

[0238] UE 104 prioritizes the transmission of data for the first LCH in 620 based on this command.

[0239] In some implementations, the command can instruct the prioritization of data transmission for the first LCH by indicating that a first priority level for first type data of the first LCH be increased to a target priority level. The first remaining time for the first type data is less than a remaining time threshold. In such an implementation, the command can instruct the first priority level for delay-critical data of the first LCH be increased to a target priority level. In such an implementation, UE 104 can determine the first remaining time for the first type data.

[0240] In some implementations, this command can instruct the transmission of data in the first LCH to be prioritized by increasing the priority level of the data in the first LCH to a target priority level. In such an implementation, the command can instruct the priority level of all data in the first LCH to be increased to the target priority level.

[0241] In some implementations, this command can indicate information used to determine the priority level of a target.

[0242] In some implementations, this command can indicate the target priority level.

[0243] In some implementations, the command can indicate the target priority level by specifying an absolute priority value. In some implementations, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on an absolute priority value. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH to an absolute priority value. For example, the absolute priority value could be the absolute priority value of the first type of data.

[0244] Alternatively or additionally, in some implementations, the command can indicate a target priority level by indicating a priority offset value. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on the priority offset value. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH by the priority offset value. For example, the priority offset value could be the priority offset value for the first type of data.

[0245] Alternatively or additionally, in some implementations, the command can indicate the target priority level via an indicator factor. In such an implementation, UE 104 can increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on this factor. For example, UE 104 can determine the target priority level based on the following: floor (factor) (First priority level), where "floor" indicates a floor operation. This factor can be a factor of type 1 data.

[0246] Alternatively or additionally, in some implementations, UE 104 may increase the first priority level of the first type of data in the first LCH or the first priority level of the data in the first LCH based on the mapping between the factor and the remaining time of the first type of data. The mapping between the factor and the remaining time may be configured by base station 102.

[0247] It should be noted that, for reference Figures 1 to 5 The implementation described also applies to procedure 600. For the sake of brevity, implementation details have been omitted.

[0248] Figure 7 An example of a device 700 supporting logical channel priority according to various aspects of this disclosure is illustrated. Device 700 may be an example of network entity 102 or UE 104 as described herein. Device 700 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 700 may include components for bidirectional communication, including components for transmitting and receiving communications (such as processor 702, memory 704, transceiver 706, and optional I / O controller 708). These components may communicate electronically or be otherwise coupled (e.g., operational ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., bus).

[0249] Processor 702, memory 704, transceiver 706, or various combinations thereof, or various components thereof, may be examples of components used to perform various aspects of the present disclosure described herein. For example, processor 702, memory 704, transceiver 706, or various combinations thereof, or components thereof, may support methods for performing one or more of the operations described herein.

[0250] In some implementations, processor 702, memory 704, transceiver 706, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described in this disclosure. In some implementations, processor 702 and memory 704 coupled to processor 702 may be configured to perform one or more functions described herein (e.g., by executing instructions stored in memory 704 by processor 702).

[0251] For example, according to the examples disclosed herein, processor 702 may support wireless communication at device 700. Processor 702 may be configured to support components for: determining a first delay state of data for a first LCH; and prioritizing the transmission of the data based on the first delay state of the data for the first LCH.

[0252] Alternatively, in some implementations, processor 702 may be configured to support components for: receiving from a base station a command indicating the priority of data transmission for the first LCH; and prioritizing data transmission for the first LCH based on the command.

[0253] Processor 702 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 702 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 702. Processor 702 may be configured to execute computer-readable instructions stored in memory (e.g., memory 704) to cause device 700 to perform various functions of this disclosure.

[0254] Memory 704 may include random access memory (RAM) and read-only memory (ROM). Memory 704 may store computer-readable and computer-executable code, including instructions that, when executed by processor 702, cause device 700 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 702, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 704 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0255] I / O controller 708 can manage the input and output signals of device 700. I / O controller 708 can also manage peripheral devices not integrated into device 700. In some implementations, I / O controller 708 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 708 can utilize an operating system such as iOS®, Android®, MS-WINDOWS®, OS / 2®, UNIX®, LINUX®, or other known operating systems. In some implementations, I / O controller 708 can be implemented as part of a processor, such as processor 702. In some implementations, a user can interact with device 700 via I / O controller 708 or via hardware components controlled by I / O controller 708.

[0256] In some implementations, device 700 may include a single antenna 710. However, in other implementations, device 700 may have more than one antenna 710 (i.e., multiple antennas), including multiple antenna panels or antenna arrays capable of concurrently transmitting or receiving multiple wireless transmissions. Transceiver 706 may communicate bidirectionally via one or more antennas 710, wired or wireless links, as described herein. For example, transceiver 706 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 706 may also include a modem for modulating packets, providing modulated packets to one or more antennas 710 for transmission, and demodulating packets received from one or more antennas 710. Transceiver 706 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0257] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. At least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 710 for transmitting the amplified signal over the air or wireless medium.

[0258] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 710 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0259] Figure 8 An example of a processor 800 supporting logical channel priorities according to various aspects of this disclosure is illustrated. Processor 800 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 800 may include a controller 802 configured to perform various operations according to the examples described herein. Processor 800 may optionally include at least one memory 804, such as an L1 / L2 / L3 cache. Additionally or alternatively, processor 800 may optionally include one or more arithmetic logic units (ALUs) 806. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0260] Processor 800 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 800)) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0261] Controller 802 can be configured to manage and coordinate various operations of processor 800 (e.g., signaling, receiving, acquiring, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 800 to support these operations according to the examples described herein. For example, controller 802 can operate as a control unit of processor 800 to generate control signals for managing the operation of various components of processor 800. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0262] Controller 802 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 804 and determine subsequent instructions(s) to be executed, enabling processor 800 to support various operations according to the examples described herein. Controller 802 can be configured to track the memory addresses of instructions associated with memory 804. Controller 802 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 802 can be configured to interpret instructions and determine control signals to be output to other components of processor 800, enabling processor 800 to support various operations according to the examples described herein. Additionally or alternatively, controller 802 can be configured to manage data flow within processor 800. Controller 802 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 800.

[0263] Memory 804 may include one or more caches (e.g., memory or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc., local to or included in processor 800). In some implementations, memory 804 may reside within or on the processor chipset (e.g., local to processor 800). In some other implementations, memory 804 may reside outside the processor chipset (e.g., remote from processor 800).

[0264] Memory 804 may store computer-readable, computer-executable code, including instructions that, when executed by processor 800, cause processor 800 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 802 and / or processor 800 may be configured to execute computer-readable instructions stored in memory 804 to cause processor 800 to perform various functions. For example, processor 800 and / or controller 802 may be coupled to or coupled to memory 804, and processor 800, controller 802, and memory 804 may be configured to perform the various functions described herein. In some examples, processor 800 may include multiple processors, and memory 804 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0265] One or more ALU 806s can be configured to support a variety of operations as described in the examples herein. In some implementations, one or more ALU 806s may reside within or on a processor chipset (e.g., processor 800). In some other implementations, one or more ALU 806s may reside outside the processor chipset (e.g., processor 800). One or more ALU 806s can perform one or more calculations on data, such as addition, subtraction, multiplication, and division. For example, one or more ALU 806s can receive input operands and an opcode that determines the operation to be performed. One or more ALU 806s are configured with a variety of logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operation. Alternatively or additionally, one or more ALU 806s may support logical operations such as AND, OR, XOR, NOR, and NAND, enabling one or more ALU 806s to handle conditional operations, comparisons, and bitwise operations.

[0266] Based on the examples disclosed herein, processor 800 may support wireless communication. Processor 800 may be configured to support components for: determining a first delay state of data for a first LCH; and prioritizing the transmission of that data based on the first delay state of the data for the first LCH.

[0267] Alternatively, in some implementations, the processor 800 may be configured to support components for: receiving from a base station a command indicating the priority of data transmission for the first LCH; and prioritizing data transmission for the first LCH based on the command.

[0268] Figure 9 A flowchart illustrating a method 900 for supporting logical channel priority according to various aspects of this disclosure is shown. Operation of method 900 may be implemented by the device or components thereof described herein. For example, operation of method 900 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the described functions.

[0269] At 910, the method may include: determining a first delay state of the data for the first LCH. The operation at 910 can be performed according to the examples described herein. In some implementations, aspects of the operation at 910 may be derived from references... Figure 1 The device described herein performs the operation.

[0270] At 920, the method may include: prioritizing the transmission of the data based on a first delay state of the first LCH data. The operation at 920 can be performed according to the examples described herein. In some implementations, aspects of the operation at 920 may be derived from references... Figure 1 The device described herein performs the operation.

[0271] Figure 10 A flowchart illustrating a method 1000 for supporting logical channel priority according to various aspects of this disclosure is shown. Operation of method 1000 may be implemented by the device or components thereof described herein. For example, operation of method 1000 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or concurrently, the device may use dedicated hardware to perform aspects of the described functions.

[0272] At point 1010, the method may include receiving from the base station a command indicating the transmission of data prioritizing the first LCH. The operation of 1010 can be performed according to the examples described herein. In some implementations, aspects of the operation of 1010 may be derived from references... Figure 1 The aforementioned device performs the operation.

[0273] At point 1020, the method may include prioritizing the transmission of data for the first LCH based on the command. The operation at 1020 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1020 can be found in the references. Figure 1 The device described herein performs the operation.

[0274] It should be noted that, for reference Figures 1 to 6 The implementation of this disclosure described herein is also applicable to device 700, processor 800, and methods 900 and 1000.

[0275] It should be noted that the methods described in this paper describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, aspects from two or more methods can be combined.

[0276] The various illustrative blocks and components disclosed herein can be implemented or executed using a general-purpose processor, DSP, ASIC, CPU, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0277] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including being distributed such that portions of the functions are implemented in different physical locations.

[0278] Computer-readable media include both non-transitory computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

[0279] As used herein, including in the claims, the article “a” preceding an element is a non-limiting article and should be understood to mean “at least one” or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. As used herein, including in the claims, the word “or” used in a list of items (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…” or “one or two of…”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, an example step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on.” Furthermore, as used herein, including in the claims, a “set” may include one or more elements.

[0280] The description provided herein is intended to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A user equipment (UE), comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: Determine the first delay state of the data in the first logical channel (LCH); and Based on the first delay state of the data from the first LCH, the transmission of the data is prioritized.

2. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data based on the first delay state of the data of the first LCH by: Prioritize the transmission of a first type of data in the first LCH, wherein the first delay state includes a first remaining time of the first type of data, and the first remaining time of the first type of data is lower than a remaining time threshold.

3. The UE according to claim 1 or 2, wherein the processor is configured to prioritize the transmission of the data based on a first delay state of the data according to the first LCH, using one of the following: The transmission of data in the first LCH takes precedence over the transmission of data in the second LCH, or The transmission of the first type of data in the first LCH takes precedence over the transmission of the data in the second LCH, or The transmission of the first type of data in the first LCH is prioritized over the transmission of the second type of data in the first LCH, wherein the first delay state includes the second remaining time of the second type of data, and the second remaining time of the second type of data is higher than the remaining time threshold.

4. The UE of claim 3, wherein the processor is configured to prioritize the transmission of the data based on a first delay state of the data according to the first LCH, using one of the following: Resources are allocated to the data in the first LCH and the second LCH in descending order of priority level of the first LCH; or Resources are allocated to the first type of data in the first LCH and the data in the second LCH in descending order of the first priority level of the first type of data and the priority level of the second LCH. or Resources are allocated to the first type of data and the second type of data of the first LCH in descending order of the first priority level of the first type of data and the second priority level of the second type of data.

5. The UE of claim 2, wherein the processor is configured to prioritize the transmission of the data of the first LCH by: Increase the first priority level of the first type of data in the first LCH to the target priority level.

6. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data of the first LCH by: Increase the priority level of the data in the first LCH to the target priority level.

7. The UE according to claim 5 or 6, wherein the target priority level is higher than or equal to the third priority level of the third LCH, and a group of one or more LCHs excludes the third LCH.

8. The UE according to claim 1 or 2, wherein: The processor is also configured to: Determine a second delay state for the data of the fifth LCH, wherein the data of the fifth LCH includes at least the first type of data, and the second delay state includes a third remaining time for the first type of data of the fifth LCH, wherein the third remaining time for the first type of data is lower than a remaining time threshold; and The processor is configured to prioritize the transmission of the data from the first LCH by: Based on the determination that the first priority level of the first LCH is higher than the fifth priority level of the fifth LCH, the transmission of the data of the first LCH is prioritized.

9. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data of the first LCH by: Based on the delay state of the data in the first LCH and the value maintained for the first LCH, the transmission of the data is prioritized.

10. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data based on a first delay state of the data of the first LCH, determined by one of the following: The data radio bearer (DRB) of the data for the first LCH is configured with a set of Protocol Data Units (PDUs) discarded; The DRB is activated when the PDU set discards the data for the first LCH; The DRB for the data in the PDU set that is discarded for the first LCH is deactivated; The first type of data in the first LCH is of high importance; The DRB for the data of the first LCH is configured with dropping based on PDU set importance (PSI); The DRB, which discards data from the first LCH based on PSI, is activated; or The DRB is deactivated when the data for the first LCH is discarded based on PSI.

11. The UE of claim 1, wherein the processor is configured to: prioritize the transmission of the data based on the first delay state of the data of the first LCH, regardless of the value maintained for the first LCH.

12. The UE of claim 11, wherein the data of the first LCH is first type data of the first LCH, wherein the first delay state includes a first remaining time of the first type data, and the first remaining time of the first type data is lower than a remaining time threshold.

13. The UE of claim 1, wherein the processor is further configured to: The transceiver receives a first indication from the base station, the first indication indicating whether to prioritize the transmission of the data based on the first delay state of the data in the first LCH.

14. A user equipment (UE), comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: The transceiver receives a command from the base station via the transceiver indicating the priority of data transmission for the first logical channel (LCH); and Based on the command, the transmission of the data in the first LCH is prioritized.

15. The UE of claim 14, wherein the command indicates the prioritization of the transmission of the data of the first LCH by instructing the first priority level of the first type of data of the first LCH to be increased to a target priority level, wherein the first remaining time of the first type of data is less than a remaining time threshold.

16. The UE of claim 15, wherein the processor is further configured to: Determine the first remaining time for the first type of data.

17. The UE of claim 14, wherein the command indicates prioritizing the transmission of the data of the first LCH by instructing the priority level of the data of the first LCH to be increased to a target priority level.

18. The UE of claim 15 or 17, wherein the command indicates information for determining the target priority level.

19. The UE of claim 18, wherein the command indicates the target priority level.

20. A base station, comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: The ability to receive from the user equipment (UE) via the transceiver whether to prioritize the transmission of data based on the delay state of data on one or more logical channels (LCHs); as well as The transceiver sends an indication to the UE indicating whether to prioritize the transmission of the data based on the delay state of the data in one or more LCHs.

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