Method for manufacturing optoelectronic devices

Abstract

The present invention relates to a method for manufacturing a photovoltaic device with vertical nanostructures, comprising an active zone (ZA) designed for emitting ultraviolet photons by radiative recombination of electron-hole pairs, or designed for generating electron-hole pairs from absorbed ultraviolet photons; the vertical nanostructures are made of n-doped gallium nitride GaN and are formed by epitaxial growth on a selective epitaxial region (SAG), said method comprising a step of selective etching of the vertical nanostructures, which leaves a residual portion (30) of each vertical nanostructure adapted to maintain the mechanical strength of a lateral region (41) of an electron transport layer made of a III-n alloy containing aluminum Al.

Description

Technical Field

[0001] This invention relates to the technical field of manufacturing optoelectronic devices. More precisely, optoelectronic devices can be electroluminescent devices or photodetectors. Electroluminescent devices are designed to emit ultraviolet (UV) photons through the radiative recombination of electron-hole pairs. Photodetectors are designed to generate electron-hole pairs from absorbed UV photons.

[0002] This invention is particularly applicable to the manufacture of light sources, displays, detectors for imaging (e.g., biology), etc. Background Technology

[0003] Typically, planar light-emitting diodes (LEDs) for UV emission consist of a substrate made of sapphire Al₂O₃, a thick layer of aluminum nitride (AlN), and a thin layer of a III-N alloy stacked together. This stack includes an electron transport layer, an active region, and a hole transport layer. The active region (typically including a quantum well) is designed to emit ultraviolet photons through the radiative recombination of electron-hole pairs. Due to the thin-layer technology employed, such planar LEDs have low efficiency (approximately 10%). In particular, the presence of structural defects and point defects reduces the internal quantum efficiency.

[0004] In this regard, nanowire LEDs for UV emission are a favorable alternative to planar LEDs. Specifically, the absence of structural defects (dislocations) allows for a significant improvement in efficiency. Due to the slow diffusion of aluminum (Al) atoms, the technology for industrial-scale growth of aluminum nitride (AlN) nanowires (or aluminum gallium nitride (AlGaN)) via metal-organic vapor phase epitaxy (MOVPE) is not yet fully developed. Conversely, the technology for orderly growth of gallium nitride (GaN) nanowires via MOVPE is well-established.

[0005] Therefore, it is known from existing technology, particularly from the article "UV-A to UV-Belectroluminescence of core-shell GaN / AlGaN wire heterostructures" by V. Grenier et al., Appl. Phys. Lett., 121, 131102, 2022, that nanowire LEDs for UV emission are fabricated by epitaxially growing LED stacks (electron transport layer, active region, hole transport layer) around gallium nitride (GaN) nanowires. This is known as core-shell epitaxial growth, where the core is formed by the nanowire and the shell is formed by the stack extending around the nanowire.

[0006] However, this existing technological approach is not entirely satisfactory because:

[0007] (i) The core made of gallium nitride (GaN) absorbs most of the UV photons emitted by the active region, and the band gap of gallium nitride is narrower than the energy of the emitted UV photons;

[0008] (ii) The epitaxial growth of the LED stack (which is based on aluminum gallium nitride, AlGaN) generates tensile elastic stress along the nanowires, promoting the formation of cracks perpendicular to the nanowires. Summary of the Invention

[0009] The present invention aims to improve all or some of the disadvantages described above. To this end, one aspect of the present invention is a method for manufacturing an optoelectronic device, the method comprising the following steps:

[0010] a) Use:

[0011] - A substrate made of a material that allows for the epitaxial growth of gallium nitride (GaN);

[0012] - A dielectric layer, which is formed on the substrate and defines a selectively grown region;

[0013] - Vertical nanostructures, made of n-type doped gallium nitride (GaN), are formed by epitaxial growth in selectively grown regions;

[0014] b) An electron transport layer is formed around each vertical nanostructure by epitaxy, the electron transport layer being made of an aluminum-containing Al-III-N alloy, the electron transport layer having an upper region and a side region;

[0015] c) Exposing vertical nanostructures by removing the upper region of the electron transport layer;

[0016] d) Selectively etch the exposed vertical nanostructures so that:

[0017] - Etch a portion of each exposed vertical nanostructure;

[0018] - Retain the remaining portion of each exposed vertical nanostructure, which is adapted to maintain the mechanical strength of the side regions of the electron transport layer;

[0019] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing Al-III-N alloys;

[0020] e) A stack is formed on the side region of the electron transport layer by epitaxy, the stack being made of an aluminum-containing III-N alloy, the stack comprising an active region and a hole transport layer, the active region being designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons.

[0021] Therefore, compared to the prior art, the method according to the present invention reduces the absorption of UV photons emitted by the active region through steps c) and d) (these two steps partially etching the vertical nanostructure (core). The selectivity of the partial etching of the core made of gallium nitride (GaN) relative to the shell (electron transport layer) is obtained by the presence of aluminum (Al) in the III-N alloy of the electron transport layer.

[0022] Furthermore, compared to existing technologies, this method according to the invention reduces elastic stress along the vertical nanostructure because step e) of forming the stack via epitaxy is performed using a partially etched core, rather than an initial core, which limits the formation of cracks perpendicular to the vertical nanostructure. During the stack formation process, if the elastic energy of the side regions of the electron transport layer is limited to 4 J / m², 2 This can prevent cracks from forming.

[0023] Another subject of the present invention is a method for manufacturing an optoelectronic device, the method comprising the following steps:

[0024] a) Use:

[0025] - A substrate made of a material that allows for the epitaxial growth of gallium nitride (GaN);

[0026] - A dielectric layer, which is formed on the substrate and defines a selectively grown region;

[0027] - Vertical nanostructures, made of n-type doped gallium nitride (GaN), are formed by epitaxial growth in selectively grown regions;

[0028] b') A stack is formed around each vertical nanostructure via epitaxy, the stack being made of an aluminum-containing Al-III-N alloy, the stack comprising, in sequence:

[0029] - Electron transport layer;

[0030] - Active regions, which are designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons;

[0031] - Hole transport layer;

[0032] The stack has an upper region and a side region;

[0033] c') Exposing vertical nanostructures:

[0034] - By removing the top area of ​​the stack; or

[0035] - By intentionally or unintentionally forming at least one through hole in the stack;

[0036] d) Selectively etch the exposed vertical nanostructures so that:

[0037] - Etch a portion of each exposed vertical nanostructure;

[0038] - Retain the remaining portion of each exposed vertical nanostructure, which is adapted to maintain the mechanical strength of the stacked side regions;

[0039] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing III-N alloys.

[0040] Therefore, compared to the prior art, the method according to the present invention reduces the absorption of UV photons emitted by the active region through steps c') and d) (these two steps partially etching the vertical nanostructure (core). The selectivity of the partial etching of the core made of gallium nitride (GaN) relative to the shell (stack) is obtained by the presence of aluminum (Al) in the stacked III-N alloy.

[0041] The method according to the invention may have one or more of the following features.

[0042] According to one feature of the invention, step c) is performed such that the upper region of the electron transport layer is removed by reactive ion etching.

[0043] Therefore, one advantage of this technology is that it allows etching to be both anisotropic and selective.

[0044] According to one feature of the invention, step c') is performed such that the upper region of the stack is removed by reactive ion etching.

[0045] Therefore, one advantage of this technology is that it allows etching to be both anisotropic and selective.

[0046] According to one feature of the invention, step c') is performed such that:

[0047] - Intentionally form at least one via in the stack by photolithography and subsequent etching;

[0048] - Cracks (F) generated during epitaxial growth in step b') unintentionally form at least one through-hole in the stack.

[0049] According to one feature of the present invention, the III-N alloy is selected from ternary aluminum gallium nitride alloy AlGaN, quaternary aluminum indium gallium nitride alloy AlInGaN, and pentary aluminum boron indium gallium nitride alloy AlBInGaN.

[0050] According to one feature of the invention, the III-N alloy contains aluminum (Al) in an atomic proportion greater than or equal to 5%.

[0051] Therefore, one advantage of the above features is that they improve the selectivity of partial etching of vertical nanostructures.

[0052] According to one feature of the invention, selective etching is performed in step d):

[0053] - By performing thermal annealing in an atmosphere containing dihydrogen (H2) and ammonia (NH3); or

[0054] - By plasma etching; or

[0055] - Through chemical etching.

[0056] According to one feature of the invention, step a) is performed such that the vertical nanostructure is selected from nanowires, nanotubes, nanoribbons, nanopillars, nanoneedles, nanocones, nanopistons, and nanowalls.

[0057] According to one feature of the invention, step a) is performed such that the substrate is made of a material selected from silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and sapphire (Al2O3).

[0058] Therefore, one advantage of this substrate is that it allows for the epitaxial growth of gallium nitride (GaN).

[0059] According to one feature of the invention, step a) is performed such that the dielectric layer is made of a material selected from silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0060] According to one feature of the invention, the electron transport layer contains an n-type dopant, preferably silicon (Si) atoms or germanium (Ge) atoms.

[0061] Therefore, one of its advantages is to increase the conductivity of the electron transport layer.

[0062] According to one feature of the invention, the hole transport layer contains a p-type dopant, preferably magnesium (Mg) atoms.

[0063] Therefore, one of its advantages is that it increases the conductivity of the hole transport layer.

[0064] According to one feature of the present invention, the active region includes at least one quantum well, said quantum well comprising, in sequence:

[0065] - The first barrier layer, which is made of ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N;

[0066] - Active layer, which is made of ternary aluminum gallium nitride alloy Al y Ga 1-yThe active layer is made of N, where “y” is strictly greater than “x”, and is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons.

[0067] - The second barrier layer, which is made of ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N;

[0068] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0069] According to one feature of the present invention, the active region includes at least one quantum well, said quantum well comprising, in sequence:

[0070] - The first barrier layer is made of aluminum gallium nitride alloy AlGaN;

[0071] - An active layer, which is made of quaternary aluminum indium gallium nitride alloy AlInGaN or pentary aluminum boron indium gallium nitride alloy AlBInGaN, is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or is designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0072] - The second barrier layer is made of aluminum gallium nitride alloy AlGaN;

[0073] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0074] definition

[0075] - The term "substrate" refers to a self-supporting physical carrier made of a base material from which optoelectronic devices can be formed. A substrate can be a "wafer," typically in the form of a disk, created by dicing an ingot of crystalline material.

[0076] - The term "dielectric" refers to the dielectric properties of the layer, which have a conductivity of less than or equal to 10 at 300 K. -6 Made of a material with an S / cm ratio.

[0077] - A "selective growth region" refers to a localized area on the substrate surface, defined by a dielectric layer, where selective epitaxial growth (SAG) occurs, while no SAG occurs elsewhere on the substrate surface. The dielectric layer forms a growth mask. The term "selective epitaxy" is also used. Each localized area on the substrate surface where epitaxial growth occurs forms a seed crystal, from which vertical nanostructures can grow. When the seed crystal and the vertical nanostructure are made of the same material, it is called homoepitaxial growth. When the seed crystal and the vertical nanostructure are made of different materials, it is called heteroepitaxial growth.

[0078] - The term "exposing vertical nanostructures" refers to the action of partially exposing a vertical nanostructure so that the vertical nanostructure has at least one free surface.

[0079] - The term "nanostructure" refers to a structure whose at least one dimension is at the nanoscale (i.e., between 0.1 nm and 10,000 nm).

[0080] - A "vertical nanostructure" refers to a nanostructure that extends along a direction corresponding to the normal to the surface of the substrate (on which the dielectric layer is formed) (i.e., the vertical direction under normal operating conditions of the optoelectronic device). As a non-limiting example, a vertical nanostructure can be columnar, meaning it can have an aspect ratio strictly greater than 1. The aspect ratio is the ratio of the height (thickness) to the width of the vertical nanostructure. The height (thickness) is the dimension along the normal to the surface of the substrate (on which the dielectric layer is formed).

[0081] - The term "III-N alloy" refers to an alloy between at least one element from Group III of the Periodic Table (PTE) and nitrogen (N). In the presence of a single element from Group III of the PTE and nitrogen, the alloy can be binary. In the presence of two elements from Group III of the PTE and nitrogen (N), the alloy can be ternary. In the presence of three elements from Group III of the PTE and nitrogen (N), the alloy can be quaternary, and so on.

[0082] - The term "upper region" refers to the region where the electron transport layer reaches its highest point along the normal to the surface of the substrate (on which the dielectric layer is formed). Similarly, it refers to the region where the stack formed in step b') reaches its highest point along the normal to the surface of the substrate (on which the dielectric layer is formed).

[0083] - The term "side region" refers to the region adjacent to one side of the electron transport layer. Similarly, it refers to the region adjacent to one side of the stack formed in step b'). The side regions of the electron transport layer are interconnected through the upper regions of the electron transport layer. Similarly, the side regions of the stack formed in step b') are interconnected through the upper regions of the stack.

[0084] - The term "selective etching of material A relative to material B" refers to the ability to etch material A without etching material B. In practice, the etchant is typically selected such that the etching rate of material A is at least 3 times higher than that of material B (preferably at least 5 times higher, more preferably at least 10 times higher).

[0085] - "Maintaining mechanical strength" means that the side regions of the electron transport layer do not fracture in response to mechanical stress at the end of step d). Similarly, it means that the side regions of the stack formed in step b') do not fracture in response to mechanical stress at the end of step d).

[0086] - The phrase "inheriting elements A, B, etc." means that elements A and B are arranged sequentially along the normals of the surfaces receiving elements A and B in a defined order. For example, the surface receiving the stack formed in step e) is the surface of the side region of the electron transport layer. The surface receiving the stack formed in step b') is the (top and side) surface of each vertical nanostructure around which the stack extends.

[0087] - The term "ultraviolet (UV)" refers to photons that are emitted or absorbed in at least one of the following spectral ranges:

[0088] (i) UV-A: [315 nm; 400 nm]

[0089] (ii) UV-B: [280 nm; 315 nm]

[0090] (iii) UV-C: [100 nm; 280 nm]

[0091] - The term "hot annealing" refers to a heat treatment process that includes the following stages:

[0092] (i) The stage of gradually increasing the temperature (slope rise) until the temperature known as the annealing temperature is reached;

[0093] (ii) A period of time, known as annealing time, during which the temperature is maintained (remained stable) at the annealing temperature;

[0094] (iii) Cooling stage.

[0095] The thermal budget is the energy input of thermal properties, defined by the selected annealing temperature and the selected annealing time.

[0096] - The term "n-type dopant" refers to a substance (e.g., an impurity) that contributes electrons to the conduction band when introduced into the matrix of a III-N alloy.

[0097] - The term "p-type dopant" refers to a substance (e.g., an impurity) that accepts electrons from the valence band (i.e. contributes holes to the valence band) when introduced into the matrix of a III-N alloy.

[0098] - The term "quantum well" can refer to a one-dimensional quantum well, a two-dimensional quantum well (also known as a quantum wire), or a three-dimensional quantum well (also known as a quantum dot). Attached Figure Description

[0099] Other features and advantages will become apparent from the detailed description of various embodiments of the invention (which includes examples and reference to the accompanying drawings).

[0100] Figure 1This is a cross-sectional schematic diagram showing step a) of the method according to the present invention.

[0101] Figure 2 This is a cross-sectional schematic diagram showing step b) of the method according to the present invention.

[0102] Figure 3 This is a cross-sectional schematic diagram showing step c) of the method according to the present invention.

[0103] Figure 4 It is shown in Figure 3 A cross-sectional schematic diagram of step d) of the method according to the present invention, performed after step c).

[0104] Figure 5 This is a cross-sectional schematic diagram showing step e) of the method according to the present invention.

[0105] Figure 6 This is a cross-sectional schematic diagram showing step b') of the method according to the present invention.

[0106] Figure 7 This is a cross-sectional schematic diagram showing a first embodiment of step c') of the method according to the invention, wherein the upper region of the stack has been removed.

[0107] Figure 8 It is shown in Figure 7 A cross-sectional schematic diagram of step d) of the method according to the present invention, performed after step c').

[0108] Figure 9 This is a cross-sectional schematic diagram showing a second embodiment of step c') of the method according to the invention, wherein at least one through hole is intentionally formed in the stack.

[0109] Figure 10 It is shown in Figure 9 A cross-sectional schematic diagram of step d) of the method according to the present invention, performed after step c').

[0110] Figure 11 This is a cross-sectional schematic diagram showing a third embodiment of step c') of the method according to the invention, wherein a through-hole is unintentionally formed in the stack.

[0111] Figure 12 It is shown in Figure 11 A cross-sectional schematic diagram of step d) of the method according to the present invention, performed after step c').

[0112] Figure 13 This is a partial cross-sectional schematic diagram of an optoelectronic device obtained using the method according to the invention, showing in particular detail the stacked active regions.

[0113] It will be noted that, for clarity and to simplify understanding, the accompanying figures described above are schematic and not necessarily drawn to scale. In particular, for the reasons stated above, only a single nanostructure is shown, and the views are drawn at magnified scale. The cross-sections are cut perpendicular to the surface of the substrate (on which the dielectric layer is formed). Detailed Implementation

[0114] For simplicity, the same elements or elements that perform the same function in the various embodiments will have the same reference numerals.

[0115] Topic 1: Formation of active regions after partial etching of nanostructures

[0116] One aspect of this invention is a method for manufacturing an optoelectronic device, comprising the following steps:

[0117] a) Use:

[0118] - Substrate 1, which is made of a material that allows for the epitaxial growth of gallium nitride (GaN);

[0119] - Dielectric layer 2, which is formed on substrate 1 and defines a selectively grown region SAG;

[0120] - Vertical nanostructure 3, which is made of n-type doped gallium nitride (GaN) and formed by epitaxial growth on selectively grown region SAG;

[0121] b) An electron transport layer 4 is formed around each vertical nanostructure 3 by epitaxy. The electron transport layer 4 is made of an aluminum-containing Al-III-N alloy and has an upper region 40 and a side region 41.

[0122] c) The vertical nanostructure 3 is exposed by removing the upper region 40 of the electron transport layer 4;

[0123] d) Selectively etch the exposed vertical nanostructure 3 so that:

[0124] - Etch a portion of each exposed vertical nanostructure 3;

[0125] - Retain the remaining portion 30 of each exposed vertical nanostructure 3, said portion being adapted to maintain the mechanical strength of the side region 41 of the electron transport layer 4;

[0126] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing Al-III-N alloys;

[0127] e) A stack is formed on the side region 41 of the electron transport layer 4 by epitaxy. The stack is made of an aluminum-containing III-N alloy. The stack includes an active region ZA and a hole transport layer 5 in sequence. The active region ZA is designed to emit ultraviolet photons through the radiative recombination of electron-hole pairs, or is designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0128] Step a)

[0129] The substrate 1 used in step a) is made of a material that allows for the epitaxial growth of gallium nitride (GaN). Step a) is advantageously performed such that the substrate 1 is made of a material selected from silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and sapphire (Al2O3).

[0130] A dielectric layer 2 formed on substrate 1 defines a selectively grown region SAG. Step a) is advantageously performed such that the dielectric layer 2 is made of a material selected from silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0131] The vertical nanostructure 3 is made of n-type doped gallium nitride (GaN). The n-type dopant is preferably silicon (Si) atoms or germanium (Ge) atoms. The vertical nanostructure 3 is formed on a selectively grown region SAG by epitaxial growth (preferably by metal-organic vapor phase epitaxy). Step a) is advantageously performed such that the vertical nanostructure 3 is selected from nanowires, nanotubes, nanoribbons, nanopillars, nanoneedles, nanocones, nanoparticles, and nanowalls.

[0132] Step b)

[0133] The electron transport layer 4 formed in step b) is made of an aluminum (Al)-containing III-N alloy. The III-N alloy is advantageously selected from ternary aluminum gallium nitride alloy AlGaN, quaternary aluminum indium gallium nitride alloy AlInGaN, and pentary aluminum boron indium gallium nitride alloy AlBInGaN. The III-N alloy advantageously contains aluminum (Al) in an atomic proportion greater than or equal to 5%.

[0134] In step b), the electron transport layer 4 is formed around each vertical nanostructure 3 by epitaxy (preferably by metal-organic vapor phase epitaxy). The electron transport layer 4 formed in step b) has an upper region 40 and a side region 41.

[0135] The electron transport layer 4 formed in step b) advantageously contains an n-type dopant, preferably silicon (Si) atoms or germanium (Ge) atoms.

[0136] Step c)

[0137] Step c) involves exposing the vertical nanostructure 3 by removing the upper region 40 of the electron transport layer 4 formed in step b).

[0138] Step c) is performed advantageously, such that the upper region 40 of the electron transport layer 4 is removed by reactive ion etching.

[0139] Step d)

[0140] Step d) involves performing selective etching adapted to partially etch the vertical nanostructures 3 exposed at the end of step c). The volume of the unetched portion 30 of each vertical nanostructure 3 is adapted to maintain the mechanical strength of the side regions 41 of the electron transport layer 4 formed in step b). In other words, the remaining (i.e., unetched) portion 30 of each exposed vertical nanostructure 3 forms a base that allows the mechanical strength of the side regions 41 of the electron transport layer 4 to be maintained.

[0141] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) (i.e., the material of vertical nanostructure 3) relative to aluminum-containing Al III-N alloy (i.e., the material of electron transport layer 4).

[0142] Selective etching is advantageously performed in step d):

[0143] - By performing thermal annealing in an atmosphere containing dihydrogen H2 and ammonia NH3 (e.g., at a temperature of 1000°C); or

[0144] - By plasma etching (e.g., using a chlorine-based Cl2 gas); or

[0145] - By chemical etching (e.g., using potassium hydroxide KOH or phosphoric acid H3PO4).

[0146] Step e)

[0147] The stack formed in step e) is made of an aluminum-containing Al-III-N alloy. The III-N alloy is advantageously selected from ternary aluminum gallium nitride alloy AlGaN, quaternary aluminum indium gallium nitride alloy AlInGaN and pentary aluminum boron indium gallium nitride alloy AlBInGaN.

[0148] In step e), the stack is formed on the side region 41 of the electron transport layer 4 by epitaxy (preferably by metal-organic vapor phase epitaxy). The stack formed in step e) sequentially includes the active region ZA and the hole transport layer 5.

[0149] The active region ZA can be designed to emit ultraviolet photons via radiative recombination of electron-hole pairs. Alternatively, the active region ZA can be designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0150] According to the first embodiment, the active region ZA includes at least one quantum well, wherein the quantum well comprises, in sequence:

[0151] - The first barrier layer B1 is made of a ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N;

[0152] - Active layer CA, which is composed of ternary aluminum gallium nitride alloy Al y Ga 1-y The active layer is made of N, where “y” is strictly greater than “x”, and is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons.

[0153] - The second barrier layer B2 is made of a ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N.

[0154] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0155] According to the second embodiment, the active region ZA includes at least one quantum well, wherein the quantum well comprises, in sequence:

[0156] - The first barrier layer B1 is made of aluminum gallium nitride alloy AlGaN;

[0157] - Active layer CA, which is made of quaternary aluminum indium gallium nitride alloy AlInGaN or pentary aluminum boron indium gallium nitride alloy AlBInGaN, is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or is designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0158] - The second barrier layer B2 is made of aluminum gallium nitride alloy AlGaN.

[0159] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0160] Hole transport layer 5 advantageously contains p-type dopants, preferably magnesium (Mg) atoms.

[0161] Topic 2: Forming active regions prior to partial etching of nanostructures

[0162] Another subject of the present invention is a method for manufacturing an optoelectronic device, the method comprising the following steps:

[0163] a) Use:

[0164] - Substrate 1, which is made of a material that allows for the epitaxial growth of gallium nitride (GaN);

[0165] - Dielectric layer 2, which is formed on substrate 1 and defines a selectively grown region SAG;

[0166] - Vertical nanostructure 3, which is made of n-type doped gallium nitride (GaN) and formed by epitaxial growth on selectively grown region SAG;

[0167] b') A stack is formed around each vertical nanostructure 3 by epitaxy, the stack being made of an aluminum-containing Al-III-N alloy, the stack comprising, in sequence:

[0168] - Electron transport layer 4;

[0169] - Active region ZA, which is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons;

[0170] - Hole transport layer 5;

[0171] The stack has an upper region ZS and a side region ZL;

[0172] c') Exposing vertical nanostructures 3:

[0173] - By removing the upper region ZS of the stack; or

[0174] - By intentionally or unintentionally forming at least one through-hole O in the stack;

[0175] d) Selectively etch the exposed vertical nanostructure 3 so that:

[0176] - Etch a portion of each exposed vertical nanostructure 3;

[0177] - Retain the remaining portion 30 of each exposed vertical nanostructure 3, which is adapted to maintain the mechanical strength of the stacked side regions ZL;

[0178] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing III-N alloys.

[0179] Step a)

[0180] The substrate 1 used in step a) is made of a material that allows for the epitaxial growth of gallium nitride (GaN). Step a) is advantageously performed such that the substrate 1 is made of a material selected from silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and sapphire (Al2O3).

[0181] A dielectric layer 2 formed on substrate 1 defines a selectively grown region SAG. Step a) is advantageously performed such that the dielectric layer 2 is made of a material selected from silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0182] The vertical nanostructure 3 is made of n-type doped gallium nitride (GaN). The n-type dopant is preferably silicon (Si) atoms or germanium (Ge) atoms. The vertical nanostructure 3 is formed on a selectively grown region SAG by epitaxial growth (preferably by metal-organic vapor phase epitaxy). Step a) is advantageously performed such that the vertical nanostructure 3 is selected from nanowires, nanotubes, nanoribbons, nanopillars, nanoneedles, nanocones, nanoparticles, and nanowalls.

[0183] Step b')

[0184] The stack formed in step b') is made of an aluminum (Al)-containing III-N alloy. The III-N alloy is advantageously selected from ternary aluminum gallium nitride alloy AlGaN, quaternary aluminum indium gallium nitride alloy AlInGaN, and pentary aluminum boron indium gallium nitride alloy AlBInGaN. The III-N alloy advantageously contains aluminum (Al) in an atomic proportion greater than or equal to 5%.

[0185] In step b'), the stack is formed around each vertical nanostructure 3 by epitaxy (preferably by metal-organic vapor phase epitaxial growth). The stack formed in step b') has an upper region ZS and a side region ZL.

[0186] The stack formed in step b') consists of an electron transport layer 4, an active region ZA, and a hole transport layer 5.

[0187] Electron transport layer 4 advantageously contains n-type dopants, preferably silicon (Si) atoms or germanium (Ge) atoms.

[0188] The active region ZA can be designed to emit ultraviolet photons via radiative recombination of electron-hole pairs. Alternatively, the active region ZA can be designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0189] According to the first embodiment, the active region ZA includes at least one quantum well, wherein the quantum well comprises, in sequence:

[0190] - The first barrier layer B1 is made of a ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N;

[0191] - Active layer CA, which is composed of ternary aluminum gallium nitride alloy Al y Ga 1-y The active layer is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons.

[0192] - The second barrier layer B2 is made of a ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N.

[0193] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0194] According to the second embodiment, the active region ZA includes at least one quantum well, wherein the quantum well comprises, in sequence:

[0195] - The first barrier layer B1 is made of aluminum gallium nitride alloy AlGaN;

[0196] - Active layer CA, which is made of quaternary aluminum indium gallium nitride alloy AlInGaN or pentary aluminum boron indium gallium nitride alloy AlBInGaN, is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or is designed to generate electron-hole pairs from absorbed ultraviolet photons.

[0197] - The second barrier layer B2 is made of aluminum gallium nitride alloy AlGaN.

[0198] The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

[0199] Hole transport layer 5 advantageously contains p-type dopants, preferably magnesium (Mg) atoms.

[0200] Step c')

[0201] Step c') involves exposing the vertical nanostructure 3.

[0202] According to the first embodiment, step c') is performed by removing the upper region ZS of the stack formed in step b'). Advantageously, step c') is performed such that the upper region ZS of the stack is removed by reactive ion etching.

[0203] According to the second embodiment, step c') is performed by intentionally or unintentionally forming at least one via O in the stack formed in step b'). Advantageously, step c') is performed such that at least one via O is intentionally formed in the stack by photolithography and subsequent etching (e.g., reactive ion etching). Advantageously, step c') is performed such that at least one via O is unintentionally formed in the stack by a crack F generated during the epitaxial growth in step b').

[0204] Step d)

[0205] Step d) involves performing selective etching adapted to partially etch the vertical nanostructures 3 exposed at the end of step c'). The volume of the unetched portion 30 of each vertical nanostructure 3 is adapted to maintain the mechanical strength of the stacked side regions ZL formed in step b'). In other words, the remaining (i.e., unetched) portion 30 of each exposed vertical nanostructure 3 forms a base that allows the mechanical strength of the stacked side regions ZL to be maintained.

[0206] Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) (i.e., the material of vertical nanostructure 3) relative to aluminum-containing III-N alloys (i.e., stacked materials).

[0207] Selective etching is advantageously performed in step d):

[0208] - By performing thermal annealing in an atmosphere containing dihydrogen H2 and ammonia NH3 (e.g., at a temperature of 1000°C); or

[0209] - By plasma etching (e.g., using a chlorine-based Cl2 gas); or

[0210] - By chemical etching (e.g., using potassium hydroxide KOH or phosphoric acid H3PO4).

[0211] This invention is not limited to the disclosed embodiments. Those skilled in the art will be able to consider technically feasible combinations therein and use them to replace equivalents.

Claims

1. A method for manufacturing an optoelectronic device, the method comprising the following steps: a) Use: - Substrate (1), which is made of a material that allows for the epitaxial growth of gallium nitride (GaN); - A dielectric layer (2) is formed on the substrate (1) and defines a selectively grown region (SAG); - Vertical nanostructure (3), which is made of n-type doped gallium nitride GaN and formed by epitaxial growth in the selective growth region (SAG); b) An electron transport layer (4) is formed around each vertical nanostructure (3) by epitaxy, the electron transport layer (4) being made of an aluminum-containing III-N alloy, the electron transport layer (4) having an upper region (40) and a side region (41); c) The vertical nanostructure (3) is exposed by removing the upper region (40) of the electron transport layer (4); d) Selectively etch the exposed vertical nanostructure (3) so that: - Etch a portion of each exposed vertical nanostructure (3); - Retain the remaining portion (30) of each exposed vertical nanostructure (3), the portion being adapted to maintain the mechanical strength of the side region (41) of the electron transport layer (4); Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing Al-III-N alloys; e) A stack is formed on the side region (41) of the electron transport layer (4) by epitaxy. The stack is made of an aluminum-containing III-N alloy and includes an active region (ZA) and a hole transport layer (5). The active region (ZA) is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs or to generate electron-hole pairs from absorbed ultraviolet photons.

2. A method for manufacturing an optoelectronic device, the method comprising the following steps: a) Use: - Substrate (1), which is made of a material that allows for the epitaxial growth of gallium nitride (GaN); - A dielectric layer (2) is formed on the substrate (1) and defines a selectively grown region (SAG); - Vertical nanostructure (3), which is made of n-type doped gallium nitride GaN and formed by epitaxial growth in the selective growth region (SAG); b') A stack is formed around each vertical nanostructure (3) by epitaxy, the stack being made of an aluminum-containing Al-III-N alloy, the stack comprising, in sequence: - Electron transport layer (4); - Active region (ZA), which is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons; - Hole transport layer (5); The stack has an upper region (ZS) and a side region (ZL); c') Expose the vertical nanostructure (3): - By removing the upper region (ZS) of the stack; or - By intentionally or unintentionally forming at least one through-hole (O) in the stack; d) Selectively etch the exposed vertical nanostructure (3) so that: - Etch a portion of each exposed vertical nanostructure (3); - Retain the remaining portion (30) of each exposed vertical nanostructure (3), the remaining portion being adapted to maintain the mechanical strength of the side regions (ZL) of the stack; Step d) is performed using an etchant that allows selective etching of gallium nitride (GaN) relative to aluminum-containing III-N alloys.

3. The method according to claim 1, wherein, Step c) is performed such that the upper region (40) of the electron transport layer (4) is removed by reactive ion etching.

4. The method according to claim 2, wherein, Step c') is performed to remove the upper region (ZS) of the stack by reactive ion etching.

5. The method according to claim 2, wherein, Executing step c') results in: - The at least one via (O) is intentionally formed in the stack by photolithography and subsequent etching; - Cracks (F) generated during epitaxial growth in step b') unintentionally form at least one through-hole (O) in the stack.

6. The method according to any one of claims 1 to 5, wherein, The III-N alloy is selected from ternary aluminum gallium nitride alloy AlGaN, quaternary aluminum indium gallium nitride alloy AlInGaN, and pentary aluminum boron indium gallium nitride alloy AlBInGaN.

7. The method according to any one of claims 1 to 6, wherein, The III-N alloy contains aluminum (Al) with an atomic ratio greater than or equal to 5%.

8. The method according to any one of claims 1 to 7, wherein, The selective etching is performed in step d): - By thermal annealing in an atmosphere containing dihydrogen (H2) and ammonia (NH3); or - By plasma etching; or - Through chemical etching.

9. The method according to any one of claims 1 to 8, wherein, Step a) is performed such that the vertical nanostructure (3) is selected from nanowires, nanotubes, nanoribbons, nanopillars, nanoneedles, nanocones, nanopistons and nanowalls.

10. The method according to any one of claims 1 to 9, wherein, Step a) is performed such that the substrate (1) is made of a material selected from silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and sapphire (Al2O3).

11. The method according to any one of claims 1 to 10, wherein, Step a) is performed such that the dielectric layer (2) is made of a material selected from silicon dioxide (SiO2) and silicon nitride (Si3N4).

12. The method according to any one of claims 1 to 11, wherein, The electron transport layer (4) contains an n-type dopant, preferably silicon (Si) atoms or germanium (Ge) atoms.

13. The method according to any one of claims 1 to 12, wherein, The hole transport layer (5) contains a p-type dopant, preferably magnesium (Mg) atoms.

14. The method according to any one of claims 1 to 13, wherein, The active region (ZA) includes at least one quantum well, which comprises, in sequence: - First barrier layer (B1), which is made of ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N; - Active layer (CA), which is made of ternary aluminum gallium nitride alloy Al y Ga 1-y N is made, where "y" is strictly greater than "x", and the active layer is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or to generate electron-hole pairs from absorbed ultraviolet photons; - Second barrier layer (B2), which is made of ternary aluminum gallium nitride alloy Al x Ga 1-x Made of N; The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

15. The method according to any one of claims 1 to 13, wherein, The active region (ZA) includes at least one quantum well, which comprises, in sequence: - The first barrier layer (B1) is made of aluminum gallium nitride alloy AlGaN; - Active layer (CA), which is made of quaternary aluminum indium gallium nitride alloy AlInGaN or pentary aluminum boron indium gallium nitride alloy AlBInGaN, is designed to emit ultraviolet photons through radiative recombination of electron-hole pairs, or is designed to generate electron-hole pairs from absorbed ultraviolet photons. - The second barrier layer (B2) is made of aluminum gallium nitride alloy AlGaN; The at least one quantum well can be one-dimensional, two-dimensional, or three-dimensional.

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