Clock phase alignment circuit, method, fpga chip and laser communication ranging system

Abstract

The application provides a clock phase alignment circuit, a method, an FPGA chip and a laser communication ranging system, and relates to the technical field of satellite communication. The clock phase alignment circuit comprises a first D flip-flop, a second D flip-flop, a counter module and a phase control module. The first D flip-flop is used for sampling a first clock signal based on a second clock signal. The second D flip-flop is used for synchronously processing an initial sampling result. The counter module is used for counting a target sampling result to obtain a count result. The phase control module is used for generating a phase adjustment control signal according to the count result and controlling a phase interpolation module to perform phase adjustment, so that the phase relationship between the first clock signal and the second clock signal tends to a target phase relationship. The application aims to improve the problem that the processing delay of the existing technology transmission link is prone to change during the reinitialization process, thereby causing poor consistency of the system transmission and reception delay.