A high-speed and high-reliability trench-gate silicon carbide VDMOS and a preparation method thereof

Abstract

The application provides a high-speed and high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and relates to the field of semiconductors. The method comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and forming a P-type region through ion implantation; re-forming the barrier layer, etching and ion implantation to form a P-type well region and an N-type source region; re-forming the barrier layer, etching, oxidizing to form a gate insulating medium layer, and arranging a trench in the gate insulating medium layer; re-forming the barrier layer, etching the barrier layer to form a through hole, depositing to form a field plate insulating layer, and repeating the step until all the field plate insulating layers are deposited; re-forming the barrier layer, etching, depositing to form a gate metal layer, a Schottky metal layer and a source metal layer, and removing the barrier layer to complete the preparation of reducing the on-resistance of the device and improving the switching speed.