A hierarchical background calibration method for time-interleaved ADCs

Abstract

The application discloses a hierarchical background calibration method for a time-interleaved ADC (Analog to Digital Converter), which is suitable for a multi-channel time-interleaved and single-channel two-stage ADC structure analog-digital conversion system. After code conversion and data alignment of each sub-channel output code stream, the method firstly estimates and eliminates each channel misadjustment and mismatch by using a second-order digital tracking loop after down-sampling, then constructs a gain error iterative update loop based on channel output power consistency to obtain a digital gain compensation coefficient, and finally performs same-frequency quadrature demodulation on each channel sequence after misadjustment and gain correction, extracts each channel phase information and converts it into a relative sampling time sequence deviation, and quantitatively compensates through a programmable clock delay unit. The method classifies static mismatch and dynamic time sequence mismatch, can suppress interleaving spur without interrupting normal sampling, improves the SNDR (Signal-to-Noise and Distortion Ratio) and SFDR (Spurious Free Dynamic Range) of the time-interleaved ADC, is simple in hardware implementation, is suitable for RTL (Register Transfer Level) implementation and on-chip background operation.

Description

Technical Field

[0001] This invention relates to the field of high-speed analog-to-digital converters and their digital-assisted calibration technology, and in particular to a hierarchical background calibration method for time-interleaved ADCs. Background Technology

[0002] Time-interleaved ADCs improve the overall system sampling rate by alternating sampling through multiple sub-channels, making them an important technical approach for achieving high-speed, high-precision data conversion. For time-interleaved ADCs with a two-stage structure, a single channel can balance speed and energy efficiency, while multi-channel interleaving can further expand the overall throughput.

[0003] However, multi-channel parallel operation introduces inter-channel mismatch, gain mismatch, and sampling timing mismatch. Mismatch creates spurious signals at fixed frequencies of interleaved correlation, gain mismatch generates mirror spurious signals on both sides of the input frequency, and sampling timing mismatch is particularly significant under high-frequency input conditions, which can severely degrade the system's SNDR and SFDR.

[0004] Among the existing time-interleaving calibration methods, some methods are designed for a single mismatch type and cannot take into account both static and dynamic timing mismatches; some methods require additional reference channels or complex digital calculations, which result in high hardware costs and are not conducive to on-chip back-end implementation for ADCs. Summary of the Invention

[0005] The purpose of this invention is to provide a hierarchical background calibration method for time-interleaved ADCs to solve the problem of prominent interleaving spuriousness and degraded dynamic performance caused by the combined effects of offset, gain and sampling timing mismatch in multi-channel time-interleaved systems.

[0006] To achieve the above objectives, the present invention provides the following technical solution.

[0007] A hierarchical back-end calibration method for time-interleaved ADCs includes the following steps.

[0008] (1) Convert the code system and align the data of the output digital codes of each sub-channel to form a unified channel output sequence.

[0009] (2) Perform offset mismatch calibration on the unified channel output sequence to obtain the offset estimate of each sub-channel, and perform offset compensation in the digital domain.

[0010] (3) Perform gain mismatch calibration on the channel output sequence after offset compensation to obtain the digital gain compensation coefficient of each sub-channel and complete the gain compensation.

[0011] (4) Perform sampling timing mismatch estimation on the channel output sequence after offset compensation and gain compensation to obtain the relative sampling time deviation of each sub-channel.

[0012] (5) Based on the relative sampling time deviation, control the programmable clock delay unit to compensate the sampling clock of each sub-channel.

[0013] Repeat the above steps until the relative mismatch of each channel converges to within the predetermined threshold range.

[0014] The time-interleaved ADC has an i-channel time-interleaved structure, with a total sampling rate of i times the single-channel sampling rate.

[0015] The mismatch calibration employs a second-order digital tracking loop. Since channel mismatch not only has a static component but may also drift slowly with temperature, power supply disturbances, and device aging, using only first-order estimation would result in slowly varying mismatch residuals. Therefore, an integral term is introduced outside the proportional term to improve long-term tracking capability.

[0016] The offset estimation process for the k-th sub-channel includes: the output of the k-th sub-channel after downsampling. As input; calculate error Update points status Update the imbalance estimate ;use Channel-by-channel offset compensation is performed on the original channel output, where k=1,2,...,i.

[0017] Gain mismatch calibration employs a power normalization iterative update method. For the k-th sub-channel output after offset compensation... First, estimate the power after weighting by the current digital gain, then compare it with the reference power to form a normalized error, and update the corresponding digital gain coefficient accordingly, where k=1,2,...,i.

[0018] The gain mismatch calibration specifically includes: downsampling the output of each sub-channel; and calculating the power estimate of each sub-channel. Calculate the average of all channel power estimates. ;Will As the gain error of the kth sub-channel; using Update the gain coefficients; change all After normalization to the final digital gain compensation coefficient, multiplication compensation is performed on the output of each sub-channel.

[0019] To avoid excessive updates to the gain coefficients before the power estimation is stable, and to prevent the coefficients from being difficult to adjust after the power estimation has converged, the power estimation update coefficient β and the gain update step size μ satisfy that μ is not greater than β. At the same time, a dead zone is set for the minimum error, and upper and lower limits are set for the gain coefficients to improve loop stability and hardware feasibility.

[0020] Sampling timing mismatch calibration employs a phase estimation method based on I / Q demodulation. For the k-th sub-channel sequence after offset and gain correction... Construct cosine and quadrature local oscillators with the same frequency as the calibration signal, and calculate the in-phase components respectively. and orthogonal components Then, the phase is obtained from the two. , where k=1,2,...,i.

[0021] The sampling timing mismatch estimation process includes: multiplying the output of the k-th sub-channel with the in-phase local oscillator and averaging the results to obtain... Multiply the output of the k-th sub-channel by the orthogonal local oscillator and calculate the average to obtain... ;calculate Remove the common phase reference shared by all channels. The relative phase difference is obtained; finally, it is converted into the relative time deviation. .

[0022] When compensating the sampling clock of each sub-channel, only the relative sampling time difference between channels is corrected, without eliminating the absolute time shift common to all channels. Therefore, it does not change the common phase of the system and is only used to suppress interleaved correlation timing spurious signals.

[0023] Compared with existing technologies, the present invention has the following advantages: The present invention processes offset mismatch, gain mismatch, and sampling timing mismatch in a hierarchical manner, avoiding the coupling of different types of errors in the same loop; the offset calibration adopts a second-order digital tracking structure, which is suitable for both static offset and slow drift offset; the gain calibration adopts power consistency constraints, does not rely on an additional reference channel, and is easy to implement in the background; the sampling timing calibration adopts I / Q demodulation and phase conversion, with a clear structure and easy to cooperate with programmable clock delay units; the entire method is applicable to digital background calibration and RTL implementation of time-interleaved ADCs, and can effectively suppress interleaved spurious signals and improve dynamic performance. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall process of the graded background calibration method of the present invention.

[0025] Figure 2 This is a schematic diagram of the mismatch calibration loop principle of the present invention.

[0026] Figure 3 This is a schematic diagram illustrating the gain mismatch calibration principle of the present invention.

[0027] Figure 4 This is a schematic diagram illustrating the principle of sampling timing mismatch estimation and clock compensation in this invention. Detailed Implementation

[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but the scope of protection of the present invention is not limited to the following embodiments.

[0029] This embodiment is designed for an i-channel time-interleaved ADC, where i is a positive integer greater than or equal to 2. Let the sampling rate of a single sub-channel be... The total sampling rate is .

[0030] After being integrated with digital codes, the outputs of each sub-channel enter the hierarchical back-end calibration link. The link includes a code conversion module, a data alignment module, an offset calibration module, a gain calibration module, a timing estimation module, and a programmable clock delay control module.

[0031] First, the output of each sub-channel is unified into the same digital format, and the data is reorganized according to the channel sampling order, so that the subsequent digital calibration module can extract the sample value sequence of each sub-channel according to the channel index.

[0032] Offset mismatch calibration is performed. Considering that the offset drift rate is much lower than the sampling rate, the output of each channel is downsampled first to reduce the computational load. Then, a second-order digital tracking loop is established for each sub-channel to continuously estimate the channel mean offset. The estimated offset value is applied to the original channel data by a channel-by-channel subtractor to achieve background compensation.

[0033] In this embodiment, the offset loop is updated jointly using proportional and integral terms. The proportional term is used to improve the convergence speed, while the integral term is used to reduce the steady-state residual under slowly varying offsets. Preferably, a proportional step size can be selected. Integral step size To balance convergence speed and stability.

[0034] Gain mismatch calibration is performed. First, sub-sequences of each sub-channel are extracted from the offset-corrected output data and downsampled. Then, the mean square power of each sub-channel under the current gain coefficient is estimated. Next, the power error of each channel is normalized using the average power of all channels as a reference power. Finally, the digital gain coefficients of each channel are updated using a multiplicative method. The updated gain coefficients are then normalized and applied to the original channel data to restore the amplitude consistency of each channel.

[0035] To avoid numerical oscillations, a dead zone can be set for the power error, and upper and lower limits can be set for the digital gain coefficient. Preferably, both the power estimation update coefficient β and the gain update step size μ can be set to a value that is not explicitly specified. And limit the digital gain coefficient within a preset working range.

[0036] Sampling timing mismatch estimation is performed. First, a channel-by-channel subsequence is constructed for the output of each channel after offset and gain compensation; then, the corresponding in-phase local oscillator and quadrature local oscillator are generated based on the calibration signal frequency; and calculations are performed for each channel. and Then determine the phase. The common phase reference is removed to obtain the relative phase difference of each channel; finally, it is converted into a relative time offset. .

[0037] The programmable clock delay unit is controlled based on the relative time deviation of each sub-channel. Since the actual hardware clock delay unit has limited resolution, it is necessary to... The time step is quantized to the closest discrete time step. Preferably, the minimum programmable delay step can be 0.5 ps. The quantized compensation is applied to the sampling clock of each channel in a negative feedback manner until the relative timing mismatch between channels is compressed to a predetermined range.

[0038] In this embodiment, the calibration signal can be either a directly multiplexed input single-tone signal or a specially injected calibration pilot. For timing estimation based on I / Q demodulation, the result is independent of the common scaling factor in the input amplitude. Therefore, once the offset and gain mismatch have been suppressed by the preceding calibration link, the relative timing deviation can be estimated relatively stably.

[0039] The hierarchical background calibration method of the present invention can be implemented by digital logic circuits or by a processor executing a program stored in a storage medium. For on-chip implementation, the offset calibration module, gain calibration module, and timing estimation module can be integrated into a digital background calibration unit, and clock compensation information can be output to a programmable clock delay unit to form a closed-loop calibration system.

[0040] By using the method of this invention, fixed frequency offset spurious, mirror gain spurious, and high-frequency interleaving spurious caused by timing deviation in time-interleaved ADCs can be significantly suppressed, making it suitable for i-channel time-interleaved ADC systems.

[0041] Any matters not covered in this invention may be replaced or modified by those skilled in the art without departing from the concept of this invention, and all such replacements or modifications shall fall within the protection scope of this invention.

Claims

1. A hierarchical background calibration method for time-interleaved ADCs, characterized by, The process includes the following steps: Code conversion and data alignment are performed on the output digital codes of the i sub-channels to form a unified format channel output sequence, where i is a positive integer greater than or equal to 2; offset mismatch calibration is performed based on the output sequences of each sub-channel to obtain the offset estimate of each sub-channel and perform digital offset compensation; gain mismatch calibration is performed based on the offset-compensated output sequences of each sub-channel to obtain the digital gain compensation coefficient of each sub-channel and perform amplitude correction; sampling timing mismatch estimation is performed based on the offset-compensated and gain-compensated output sequences of each sub-channel to obtain the relative sampling timing deviation of each sub-channel; a programmable clock delay unit is controlled according to the relative sampling timing deviation to compensate the sampling clock of each sub-channel; the above process is repeated until the inter-channel mismatch converges to a predetermined range.

2. The hierarchical background calibration method of claim 1, wherein, The time-interleaved ADC has an i-channel time-interleaved structure, with a total sampling rate of i times the single-channel sampling rate.

3. The hierarchical background calibration method of claim 1, wherein, The offset mismatch calibration is achieved using a downsampled second-order digital tracking loop. For the k-th sub-channel, where k=1,2,...,i, the error term is the difference between the current output of the sub-channel and the offset estimate of the sub-channel. The loop includes both a proportional update branch and an integral update branch to reduce the steady-state residual of static offset and slow drift offset caused by temperature, power supply fluctuations and device aging.

4. The hierarchical background calibration method of claim 3, wherein, In the mismatch calibration, the error term, integral state quantity, and mismatch estimate of the k-th sub-channel respectively satisfy: ； ； ； wherein, is the current estimation error, is the integral state quantity, is the misadjustment estimate for this channel, is the proportional step size, determining the speed of transient response of the loop, is the integral step size, determining the ability to compensate for long-term drift.

5. The hierarchical background calibration method according to claim 1, characterized in that, The gain mismatch calibration is implemented using a normalized iterative method based on the consistency of channel output power, including: downsampling the output data of each sub-channel after offset compensation; calculating the power estimate of each sub-channel after weighting by the current digital gain coefficient; taking the average of all sub-channel power estimates as the reference power; updating the digital gain coefficient of the corresponding sub-channel according to the deviation between the power estimate of each sub-channel and the reference power; and normalizing the updated digital gain coefficient and using it to perform gain compensation on the sub-channel output.

6. The graded background calibration method according to claim 5, characterized in that, In the gain mismatch calibration, the power estimate, power error, and digital gain coefficient of the k-th sub-channel at the j-th iteration satisfy the following: ； ； ； ； ； in, The output of the channel after mismatch calibration. The output after gain calibration The average power of the k-th channel, These are the update coefficients for power estimation. To normalize the power error, Digital gain coefficient.

7. The hierarchical background calibration method according to claim 1, characterized in that, The sampling timing mismatch estimation is achieved using an orthogonal demodulation method, including: multiplying the output sequence of the k-th sub-channel after mismatch compensation and gain compensation by the local oscillator cosine sequence and the negative sine sequence of the same frequency, and averaging them to obtain the in-phase component of the k-th sub-channel. and orthogonal components ;according to and Find the phase of the k-th sub-channel Subtracting the common phase reference from the phase of each sub-channel yields the relative sampling timing deviation of each sub-channel. ;Will Quantization is performed according to the minimum time step of the programmable clock delay unit to generate the clock compensation amount for each sub-channel.

8. The hierarchical background calibration method according to claim 7, characterized in that, The relative sampling timing deviation of the k-th sub-channel satisfies: ； ； in, This is the average value of the phase of all sub-channels. To calibrate the signal angular frequency; the clock compensation amount is for... The negative compensation amount is calculated by rounding down the minimum resolution of the programmable clock delay unit.

9. The graded background calibration method according to claim 7 or 8, characterized in that, The calibration signal used for the sampling timing mismatch calibration is an input single-tone signal or a dedicated calibration pilot signal; the frequency of the calibration signal is less than half of the total sampling rate.

10. The hierarchical background calibration method according to claim 1, characterized in that, Both the mismatch calibration and gain mismatch calibration are performed in the digital domain background. The sampling timing mismatch calibration is achieved by combining digital estimation and analog clock compensation, thereby separating static mismatch and timing mismatch for processing.

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