Counter for image sensor column-level single-slope adc and driving method thereof

Abstract

This invention relates to the field of image sensor technology, specifically to a counter and its driving method for a column-level single-slope ADC in image sensors. The counter consists of a Gray code generation module and a counting system. The Gray code generation module generates the Gray code sequence required for counting. The counting system includes multiple counting units, each consisting of a low-order latch module, a conversion module, an adder module, a high-order counting module, and an output latch module. The low-order latch module latches the current Gray code when the compout signal transitions; the conversion module converts the latched Gray code into binary code; the adder module performs binary addition operations; the high-order counting module performs binary counting based on the low-order latch signal or the adder carry signal; and the output latch module stores the value at the time of the compout signal transition and outputs it externally. Through the Gray code generation module and the cascaded counting structure, the counter achieves high-precision, low-power column-level ADC counting functionality.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and more specifically to a counter for a column-level single-slope ADC of an image sensor and its driving method. Background Technology

[0002] CMOS image sensors (CIS) are rapidly developing image sensors that have emerged in the last decade. They are compatible with traditional CMOS manufacturing processes, integrating photosensitive analog circuits and digital signal processing circuits into a compact and efficient system-on-a-chip (SoC). Analog-to-digital converters (ADCs) are a crucial module in CIS, converting analog signals from a pixel array into digital signals. Traditional CIS commonly uses column-level ADCs to improve speed and reduce power consumption. Single-slope ADCs (SSADCs) are widely used due to their low power consumption, small area, and simple structure, and their counters (connecting the comparator and digital circuitry) are critical. However, as CIS array sizes increase, the power consumption and area limitations of the counters become more prominent. Furthermore, traditional column-level SSADCs involve numerous counter flips during quantization (especially for low-bit values), resulting in high dynamic power consumption and impacting performance reliability. The Correlated Double Sampling (CDS) method used in mainstream CIS requires subtraction during two counts to improve speed, which is currently difficult to implement.

[0003] To address these issues, existing technologies have made various attempts. For the problem of high power consumption and numerous counter flips, the circuit structure is optimized. For example, segmented counting is used, separating the high and low bits to reduce the number of low-bit flips, or a synchronization signal is used to control the counter to avoid unnecessary flips. Regarding the CDS processing speed issue, some technologies store the digital values ​​of the reset and signal components in the digital module before performing the subtraction, while others perform a preliminary subtraction on the analog side before transmitting the data to the ADC for conversion, attempting to shorten the processing time.

[0004] However, existing solutions still have shortcomings. When optimizing the counter structure, segmented counting increases the complexity of the control circuit, which may not reduce the area much and even affect the counting speed. Synchronous control may also require an additional clock signal, increasing power consumption. When processing CDS, the subtraction after digital storage will have a significant delay, which cannot meet the speed requirements of CIS. The initial subtraction on the analog side is easily affected by noise, which reduces signal accuracy. Most of these methods can only solve a single problem and cannot simultaneously take into account the power consumption and area of ​​the counter, as well as the processing speed of the CDS, making it difficult to meet the overall performance requirements of CIS. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a counter for a column-level single-slope ADC of an image sensor and its driving method, which solves the technical problem of excessive dynamic power consumption caused by the high number of counter circuit flips.

[0006] The objective of this invention is achieved through the following technical solutions: In a first aspect, the present invention provides a counter for a column-level single-slope ADC of an image sensor, the counter comprising: a Gray code generation module and a counting system connected in communication; The Gray code generation module is used to generate the Gray code values ​​required for counting; The counting system includes several counting units for receiving the Gray code value and performing counting operations. Each counting unit includes: The low-order latch module is used to receive the Gray code value and the compute signal from the Gray code generation module, and latch the current Gray code value when the compute signal changes. The conversion module is used to convert latched Gray code values ​​into binary code; The adder module is used to perform addition operations on the converted binary code values; The high-order counting module is used to selectively receive the set latch signal from the low-order latch module or the carry signal from the adder module to perform binary counting. The output latch module is used to latch and output the final count value in the high-order counting module.

[0007] As a further improvement of the present invention, an intermediate latch is also included, connected between the low-order latch module and the high-order counting module, for latching the highest-order Gray code output by the low-order latch module and serving as the clock control signal for the high-order counting module.

[0008] As a further improvement of the present invention, the low-order latch module includes: The input control circuit receives the first enable signal and the compout signal, and is used to control the start of the latching function; Multiple latch units are provided, with their data input terminals connected to the Gray code generation module and their control terminals connected to the output terminal of the input control circuit. These units are used to latch the current Gray code value when the compout signal changes and output it to the conversion module. An initialization circuit receives a second enable signal and a third enable signal to initialize the output of the low-order latch module to a predetermined value before counting begins. The first enable signal, the second enable signal, and the third enable signal are generated by a digital circuit connected to the counter.

[0009] As a further improvement of the present invention, the conversion module includes a conversion circuit composed of several logic gates. The conversion circuit is controlled by a fourth enable signal. When the fourth enable signal is valid, the conversion circuit is turned on and converts the input Gray code value into the corresponding binary inverse code output. The fourth enable signal is generated by a digital circuit connected to a counter.

[0010] As a further improvement of the present invention, the adder module includes multiple cascaded trigger units, which are used to add the binary inverse code of the conversion module to the inverse code inside the adder module under the action of an external addition control pulse sequence, and generate an addition carry signal to be output to the high-order counting module.

[0011] As a further improvement of the present invention, the high-order counting module includes: The first flip-flop group receives the signal from the intermediate latch at its clock input terminal to implement binary decrement counting. The second flip-flop group receives the carry signal from the adder module at its clock input terminal to perform counting operations. The operating mode of the high-order counting module is controlled by an external path selection signal to select whether to receive input signals from the intermediate latch or the adder module.

[0012] As a further improvement of the present invention, both the adder module and the high-order counting module receive the same set and invert control signals to realize the initialization of the internal counting state and the inverting of the value.

[0013] Secondly, the present invention provides a counting method for a column-level single-slope ADC of an image sensor, applied to the aforementioned counter for a column-level single-slope ADC of an image sensor, comprising: The low-order latch module, adder module, and high-order counter module in the counter are reset to set their internal counting states to zero. The Gray code generation module is started to count, and when the compout signal changes, the first Gray code value is latched by the low-bit latching module and the current high-bit binary code value is latched by the high-bit counting module. The initial value and the high-order binary code value of the adder are inverted, and the first Gray code value is converted into the inverse code of the low-order binary code value using the conversion module. The adder module adds the inverse code of the low-order binary code value to the initial value and stores it. The code value stored in the adder and the data stored in the high-order counting module together constitute the first intermediate data. Restart the counting process and latch the second Gray code value and the corresponding high-order binary count value when the compout signal changes. The code value stored in the adder and the code value of the high-order counter are inverted; the conversion module converts the second Gray code value into the inverse of the binary code value; The adder module adds the inverse of the binary code value to the stored code value and performs an addition operation with borrow; it obtains the final low-bit difference result and the high-bit difference result; and it combines the low-bit difference result and the high-bit difference result for output.

[0014] As a further improvement of the present invention, when the comparator output signal of a certain counting unit changes, the corresponding low-order latch module latches the current Gray code value, while the Gray code generation module continues to operate and provides Gray code values ​​for other counting units.

[0015] As a further improvement of the present invention, the first intermediate data is inverted, and the latched first Gray code value is converted into binary inverse code. Then, an addition operation is performed with the inverted low-order digits to update the low-order digits and prepare the initial state for the high-order counting, including: The current output value of the counter is inverted bit by bit using a control signal; The conversion module is activated to convert the Gray code value latched by the low-order latch module into binary code. Then, by sequentially inputting pulse signals, the adder module is controlled to perform the addition of the binary code with the inverted low-order value.

[0016] The beneficial effects of this invention are as follows: This invention provides a counter for a column-level single-slope ADC of an image sensor, achieving high-precision counting of the column-level single-slope ADC through the collaborative design of a Gray code generation module and a counting system connected by communication. Specifically, the Gray code generation module generates Gray code values ​​where adjacent values ​​change by only one bit to reduce dynamic power consumption; the low-bit latch module latches the current Gray code value when the comparator output signal changes, ensuring accurate capture of instantaneous signal changes; the conversion module converts the latched Gray code value into binary code to adapt to subsequent addition operations; the adder module performs addition operations on the binary code to achieve the counting function; the high-bit counting module selectively receives the set latch signal from the low-bit latch module or the carry signal from the adder module to perform binary counting, supporting both direct latching and carry propagation, improving counting flexibility; and the output latch module latches and stably outputs the final count value from the high-bit counting module. The counter of this invention reduces counting errors, ensures accurate capture of signal transition moments, adapts to binary addition operations, realizes counting functions, and improves counting flexibility. After the modules work together, a high-precision, low-error, and stable output counting system is formed from Gray code generation to binary counting. It is particularly suitable for the high-speed and high-precision counting requirements of image sensor column-level single-slope ADCs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a low-power counter for an image sensor provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the Lower_LSB module described in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the gray2bin conversion module described in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the Adder module Adder according to an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the Upper_LSB high-order counting module according to an embodiment of the present invention.

[0023] Figure 6 This is a complete timing diagram related to the counter counting mode described in the embodiments of the present invention. Detailed Implementation

[0024] To make the objectives and technical solutions of this invention clearer and easier to understand, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0025] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. The described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] Example 1 This embodiment provides a counter for a column-level single-slope ADC of an image sensor, connected to an external comparator and digital circuitry. The counter includes a Gray code generation module and a counting system connected in communication. The Gray code generation module generates the Gray code values ​​required for counting; the counting system includes several counting units for receiving the Gray code values ​​and performing counting operations. In this embodiment, the output signal of the external comparator is a comput signal.

[0027] The counting unit includes a low-order latch module, a conversion module, a high-order counting module, and an output latch module, all connected via communication. The low-order latch module receives the Gray code value and the `compout` signal from the Gray code generation module, and latches the current Gray code value when the `compout` signal transitions. The conversion module converts the latched Gray code value into binary code. The adder module performs addition operations on the converted binary code value. The high-order counting module selectively receives the set latch signal from the low-order latch module or the carry signal from the adder module to perform binary counting. The output latch module latches and outputs the final count value from the high-order counting module.

[0028] The counter provided in this embodiment works by generating Gray code values ​​required for counting through a Gray code generation module, providing the basic counting signal for the entire counting system. Several counting units within the counting system receive the Gray code values ​​and perform counting operations. Specifically, the low-order latch module receives the Gray code values ​​and the `compout` signal from the Gray code generation module, and latches the current Gray code value when the comparator output signal transitions. Compared to existing designs where counting units do not specifically latch the Gray code value at the transition moment, this ensures accurate latching of the counting signal at the transition moment, avoiding counting deviations. The conversion module converts the latched Gray code values ​​into binary code, solving the technical problem that Gray code cannot be directly used for subsequent addition operations and high-order counting, realizing the conversion of Gray code into a signal form that can be subsequently processed. The adder module performs addition operations on the converted binary code values ​​to accumulate the count values, improving the continuity and integrity of the counting. The high-order counting module selectively receives data from the low-order latch module. The counter sets the latch signal or carry signal of the adder module and performs binary counting, flexibly adapting to the signal input requirements of different counting scenarios. Compared with the high-order counting design with fixed signal input, it improves the adaptability and counting range of the counting system. The output latch module latches and outputs the final count value in the high-order counting module, ensuring a stable output of the final count value and avoiding counting errors caused by signal fluctuations during the output process. The counter in this embodiment can accurately, stably, and efficiently complete the counting operation of the image sensor's column-level single-slope ADC, greatly improving counting accuracy, stability, and efficiency. At the same time, it optimizes the counting signal processing flow and adapts to the counting requirements of the image sensor's column-level single-slope ADC. In addition, the Gray code generation module is shared by multiple counting structures, thereby reducing the overall power consumption of the image sensor. The counter performs the subtraction operation of two numbers in two counting processes, eliminating the need for an additional subtraction calculation unit.

[0029] In this embodiment, the counter also includes an intermediate latch. The intermediate latch is connected between the low-order latch module and the high-order counting module, and is used to latch the most significant Gray code output by the low-order latch module and serve as the clock control signal for the high-order counting module.

[0030] In this embodiment, the low-order latch module includes: an input control circuit, multiple latch units, and an initialization circuit. The input control circuit receives a first enable signal and a comparator output signal to control the activation of the latch function. The data input terminals of the multiple latch units are connected to the Gray code generation module, and the control terminals are connected to the output terminal of the input control circuit to latch the current Gray code value when the compout signal changes and output it to the conversion module. The initialization circuit receives a second enable signal and a third enable signal to initialize the output of the low-order latch module to a predetermined value before counting begins. The first, second, and third enable signals are generated by a digital circuit connected to the counter. The low-order latch module receives a first enable signal from the input control circuit and coordinates with the comparator output signal to control the latch function to start, ensuring that the latch operation is triggered only under specific conditions, reducing invalid latches and improving the accuracy of latch timing. Multiple latch units latch the current Gray code value when the comparator output signal changes and output it to the conversion module and intermediate latches, ensuring accurate capture of the value at the moment of change and avoiding erroneous latching of intermediate values ​​during signal changes. The initialization circuit initializes the output to a predetermined value before counting begins using a second and third enable signal, eliminating counting errors caused by initial state uncertainty and ensuring deterministic counting start. Each enable signal is synchronously generated by the connected digital circuit, achieving timing coordination between signal generation and the counter's operating state, enhancing the overall system stability. Furthermore, in this embodiment, after the compout transition, the signal from the low-order latch module does not pass through the g... <m>The signal is transmitted to the intermediate latch. Before the component signal transitions, that is, while the lower-order latch module is still receiving Gray code, the signal from the lower-order latch module is transmitted through g. <m>The data is transmitted to the intermediate latch.

[0031] The conversion module comprises a conversion circuit consisting of several logic gates. This circuit is controlled by a fourth enable signal. When the fourth enable signal is valid, the conversion circuit turns on and converts the input Gray code value into the corresponding binary inverse code output. The fourth enable signal is generated by a digital circuit connected to the counter. By enabling the conversion circuit through logic gates when the fourth enable signal is valid, the conversion module achieves accurate Gray code to binary inverse code conversion, avoiding the extra power consumption caused by invalid conversions. The fourth enable signal is synchronously generated by the connected digital circuit, ensuring strict alignment between the conversion operation and system timing, improving the accuracy of the conversion timing. The binary inverse code output directly adapts to the computational needs of the subsequent adder module, reducing intermediate format conversion losses and improving counting efficiency.

[0032] The adder module includes multiple cascaded trigger units, which, under the action of an external addition control pulse sequence, add the binary inverse code of the conversion module to the inverse code output inside the adder module, and generate an addition carry signal to be output to the high-order counting module. The adder module employs multiple cascaded trigger units. Compared to non-cascaded trigger unit designs, this allows for hierarchical and orderly execution of addition operations, avoiding computational delays caused by excessive single-operation loads and improving the speed and stability of addition operations. Multiple cascaded trigger units execute addition operations under the influence of an external addition control pulse sequence. Through timing control of this external pulse sequence, the start, execution, and stop times of addition operations can be precisely controlled, significantly improving the controllability and synchronization of addition operations compared to designs without explicit timing control. The trigger units add the binary inverse code from the conversion module to the inverse code output within the adder module. Using inverse code addition, compared to directly adding the original code, effectively simplifies the addition logic, reduces errors during computation, and improves the accuracy of addition operations.

[0033] The high-order counting module includes a first flip-flop group and a second flip-flop group. The clock input of the first flip-flop group receives the signal from the intermediate latch and is used to implement binary decrement counting; the clock input of the second flip-flop group receives the carry signal from the adder module and is used to implement counting operation with borrow.

[0034] The operating mode of the high-order counting module is controlled by an external path selection signal to select whether to receive clock signals from the intermediate latch or the adder module. Specifically, the high-order counting module has two independent flip-flop groups: a first flip-flop group and a second flip-flop group. Compared to existing high-order counting modules with only a single flip-flop group, this allows for the independent implementation of two different counting functions, improving the functional versatility of the counting module. The clock input of the first flip-flop group receives the signal from the intermediate latch and performs binary decrement counting, specifically adapting to scenarios requiring decrement counting, ensuring the accuracy of decrement counting, and avoiding counting errors. The clock input of the second flip-flop group receives the carry signal from the adder module and performs counting operations with borrow. This accurately responds to the carry requirements of the adder module, completing counting with borrow, improving the accuracy and reliability of counting in carry scenarios, and avoiding counting deviations during borrowing. The operating mode of the high-order counting module is controlled by the external path selection signal, allowing for flexible switching of the operating mode according to actual counting needs, improving the scenario adaptability and usage flexibility of the high-order counting module.

[0035] Both the adder module and the high-order counter module receive the same set and invert control signals to initialize the internal counting state and invert the value.

[0036] Example 2 This embodiment provides a specific implementation of a counter and its driving method for a column-level single-slope ADC of an image sensor. This embodiment uses an n-bit counter as an example, where the lower m bits use Gray code counting, the higher nm bits use binary counting, and the highest bit is the sign bit.

[0037] like Figure 1 The diagram shown is a schematic representation of a low-power counter for an image sensor provided in an embodiment of the present invention. The counter includes a Gray code generator module and a counting unit.

[0038] The counting unit Count consists of the lower_LSB low-order latch module, the gray2bin conversion module, the adder module Adder, the upper_LSB high-order counter module, the latch LATCH0, and the output latch module OutLatch.

[0039] The number of counting units can be expanded according to the needs of array size, and they share the output signal of the Gray code generator module, thereby reducing power consumption and area.

[0040] The input signals SET0, SET1, and G_2 of the Gray code generation module Gray-code-generator <m:1>Provided by digital circuitry; the input signal clk is a clock signal generated by the clock circuit; when SET1 is low, the Gray code generation module stops working, G_2 <m:1>When all three are low; SET1 is high, the counter operates. When SET0 is low, the Gray code generator module counts according to the Gray code. When SET0 is high, the Gray code generator module outputs the signal from input signal G_2. <m:1>control.

[0041] The output signal G of the gray code generator module <m:1>The signal is transmitted to the lower_LSB latch module, which latches the signal; the output signal H15 is transmitted to the latch LATCH0 as the control signal for the latch function of the latch LATCH0.

[0042] The input signal `compout` of the Lower_LSB module is the comparator output signal; input signals H1, H2, H3, and H8 are provided by digital circuitry; the output signal `g`... <m:1>The signal is transmitted to the conversion module gray2bin; the output signal g is then sent. <m>It is also transmitted to latch LATCH0.

[0043] The gray2bin conversion module converts Gray code to binary code. The input signal H9 is provided by digital circuitry; the output signal b... <m:1>Send to the Adder module.

[0044] The input signals of the adder module Adder are con1, inv_en0, inv_en1, and A. <m:1>Provided by digital circuitry; output signal B <m:1>The signal is transmitted to the output latch module OutLatch; <m>Transmitted to the Upper_LSB high-order counter module.

[0045] The input signals con1, inv_en0, inv_en1, con2, and H10 of the upper-order counter module Upper_LSB are provided by digital circuitry; among them, con1, inv_en0, and inv_en1 are the same as the input signals con1, inv_en0, and inv_en1 of the adder module Adder; the output signal B<n:m+1> The data is transmitted to the Output Latch module.

[0046] The input signal C of the output latch module OutLatch <n:1>Provided by digital circuitry; when C <n:1>When it is low, the output signal Q of the output latch module OutLatch is... <n:1>It is then passed to the next stage of the circuit for processing.

[0047] Input signal A <m:1>Used to implement the addition function of the Adder module; The input signals con1, inv_en0, and inv_en1 are used to set and invert the bits of the adder module Adder and the high-order bit counter module Upper_LSB, respectively. Input signal con2 is used to control the signal input of the Upper_LSB high-order counter module; The input signal H10 is used to control the path of the signal received by the Upper_LSB high-order counting module. When H10 is low, the Upper_LSB high-order counting module receives the signal from the latch Latch0. When H10 is high, the Upper_LSB high-order counting module receives the signal from the Adder.

[0048] Figure 2 This is a schematic diagram of the Lower_LSB module described in an embodiment of the present invention. The Lower_LSB module consists of AND gate AND0, OR gate OR0, OR gate OR1, register REG0, and NAND gate NAND. <m:1>LATCH <m:1>The inverter INV0 is used. H3 is the reset input of register REG0, active low. Input signal H2 is used to initialize the lower_LSB latch module. When H8 is high, the latch LATCH is active. <m:1>It is in a transparent state. Input signal H1 is the compout input enable signal, active high.

[0049] like Figure 3 The diagram shown is a structural schematic of the gray2bin conversion module. Figure 3 The gray2bin conversion module consists of NAND gates and XNOR gates. Input signal H9 controls the gray2bin conversion module to turn on and off. When input signal H9 is high, the gray2bin conversion module is turned on, controlling it to convert the input signal G... <m:1>The code value is converted to the corresponding binary code value and then inverted. When H9 is low, the gray2bin conversion module is turned off.

[0050] like Figure 4 The diagram shows the structure of the adder module Adder. The adder module Adder consists of AND gates, XOR gates, and five flip-flops (TIR). <m:1>Composition. Input signal A <m:1>Input the pulse sequence sequentially, and b <m:1>Add the corresponding code value to Q <m:1>Terminal. Due to the Q of the flip-flop. The B terminal and the Q terminal have opposite code values, therefore, B <m:1>Code value and Q <m:1>The code values ​​are reversed. Inputs C1, C2, and C3, when used in a specific timing sequence, can set the flip-flop. Inputs C2 and C3, when used in a specific timing sequence, can toggle the code value at the Q input of the flip-flop. The output signal B of the adder module Adder... <m:1>The code values ​​correspond sequentially to the lower m bits of the counter.

[0051] like Figure 5 The diagram shows the structure of the Upper_LSB high-order counting module. The Upper_LSB module consists of two NAND gates, one inverter, and a TIR flip-flop.<n:m+2> and trigger TIR1<m+1> Composition. Among them, the trigger TIR1<m+1> When the T terminal is at a low potential, the trigger TIR1<m+1> To maintain the state, output signal B. <n:m>The code values ​​corresponding to the high nm bits of the counter are sequentially assigned.

[0052] Trigger TIR <m:1>TIR<n:m+2> Trigger TIR1 <m>The C1, C2, and C3 terminals, when input in a specific timing sequence, can achieve the setting function of the flip-flop. The C2 and C3 terminals, when input in a specific timing sequence, can also achieve the toggling of the Q-terminal code value of the flip-flop.

[0053] Figure 6 This is a complete timing diagram related to the counter counting mode in an embodiment of the present invention.

[0054] The t0 to t1 stage is the counter initialization stage. First, H1 is enabled, allowing the comparator output signal `compout` to be transmitted to the lower-order latch module (Lower_LSB). Then, H3 initializes the REG0 register in the Lower_LSB. Next, a pulse is input to H2, setting REG0 to a high level. Then, a pulse is input to H8. It can be seen that during the initialization stage, SET1 is low, and the Gray code output is all 0. After the H8 pulse, the Lower_LSB latch `LATCH`... <m:1>The output is set to 0. This completes the initialization of Lower_LSB. Simultaneously, con1, inv_en0, and inv_en1 are initialized to Adder and Upper_LSB according to the waveforms shown in the figure, setting B... <n:1>Set all values ​​to 0.

[0055] The t1 to t3 phases constitute the first counting stage, during which the reset component is quantized. After the initialization phase is complete, SET1 goes high, the Gray code generation module starts working, and simultaneously, compout changes from high to low. The counting unit Count receives the Gray code input, and g... <m:1>Signals and G <m:1>The signals are consistent. <m>The signal passes through LATCH0 and is transmitted to Upper_LSB as a clock signal. Whenever g... <m>Upon a rising edge, Upper_LSB is decremented by 1. At time t2, the compout signal toggles, at which point Lower_LSB is latched, and Upper_LSB stops counting.

[0056] Define the value of the first count (Upper_LSB) as A1, and the binary value corresponding to the value of the lower m Gray code as B1.

[0057] B of Upper_LSB<n:m+1> The code value is .

[0058] t3 to t6 constitute the first counting process. The first step is inversion, achieved through the inv_en0 and inv_en1 signals, setting B... <n:1>Invert all values. The Upper_LSB counter code value becomes Adder's B <m:1>Become all 1s, <m:1>The result is all zeros. Then comes the addition phase. H10 changes from high to low, switching the input signal path of Upper_LSB. H9 is enabled, controlling the gray2bin conversion module to start, and the conversion module converts the Gray code G... <m:1>Convert to the corresponding binary code value b <m:1>And inverse it. A <m:1>Pulses are sequentially fed in, and b <m:1>and <m:1>Add them together. Because gray2bin converts the Gray code to its corresponding binary complement, the result after adding them is... <m:1>The code value is And B <m:1>The code value is B1. Next, during the set phase, H8 is enabled, setting the Lower_LSB flip-flop to 0. Note that during the addition and set phases, con2 is set low to prevent Adder from affecting Upper_LSB.

[0059] The t6 to t8 stage is the second counting stage, which quantizes the signal components and follows the same timing as the first counting stage.

[0060] t8 to t 11 This stage is the second counting process. Note that in this step, the con2 signal is set to a low level at both the rising and falling edges of the H9 signal, and at A... <m:1>The pulse signal has a built-in high potential during its time period to enable borrowing from the higher bits. The timing of the remaining signals is the same as in the first counting process.

[0061] In the second counting phase, the Upper_LSB module counts downwards from the value of the first count. After the counting is complete, B...<n:m+1> The code value is .

[0062] This achieves the subtraction of the two counts. For the lower m bits, after the inversion step, the Adder module... <m:1>The code value becomes B1, while B <m:1>The code value is After the addition step, The code value of B<4:0> is .

[0063] t 11 The subsequent two counts were completed, and the second count was subtracted from the first count. B <m:1>The code value is .

[0064] After the final count is completed, C will be... <n:1>When set to a low potential, the counter will B <n:1>The code value is transmitted to the input Q. <n:1>And output it.

[0065] Within the two counting phases, after each compout flip, only the Lower_LSB module latches the Gray code value at the flip moment; the Gray code generation module does not stop. Therefore, when one counting unit in the counter array stops, the remaining counting units can still receive signals from the Gray code generation module and continue counting. Thus, this structure enables the sharing of Gray code modules and can be applied to column-level ADCs in image sensors.

[0066] This invention achieves the subtraction of the reset component and the signal component in two counting processes, which helps to improve the speed of CIS.

[0067] Example 3 Based on the counters for column-level single-slope ADCs of image sensors in Embodiments 1 and 2, this embodiment provides a counting method for a counter for a column-level single-slope ADC of an image sensor.

[0068] The counting method includes the following steps: resetting the low-order latch module, adder module, and high-order counting module in the counter to set the internal counting state to zero; starting the Gray code generation module to count, and latching the current first Gray code value and the corresponding high-order binary count value when the comparator output signal changes, thus obtaining the first intermediate data; inverting the first intermediate data, converting the latched first Gray code value into binary inverse code, and adding it with the initial value to update the low-order digits; restarting the counting process, and latching the second Gray code value and the corresponding high-order binary count value when the comparator output signal changes, thus obtaining the second intermediate data; inverting the second intermediate data, converting the latched second Gray code value into binary inverse code, and adding it with the current low-order digits with borrow to obtain the final low-order difference result, and simultaneously obtaining the high-order difference result; and combining the low-order difference result and the high-order difference result for output.

[0069] This embodiment resets the low-order latch module, adder module, and high-order counting module in the counter and sets their internal counting states to zero. Compared to designs without initialization reset operations or with incomplete resets, this eliminates interference from residual states from previous counts. The Gray code generation module is activated for counting, and when the comparator output signal transitions, the current first Gray code value and the corresponding high-order binary count value are latched to obtain the first intermediate data. Compared to designs that do not accurately latch data at signal transition moments, this captures the true count data at the transition moment, avoiding data latching deviations and improving the accuracy of intermediate data. The first intermediate data is inverted, and the latched first Gray code value is converted to binary inverse code. This inverse code is then added to the inverted low-order digits to update the low-order digits and prepare the initial state for high-order counting. Compared to designs that directly use original code operations without updating the low-order digits, this simplifies the computational logic and provides accurate data for subsequent high-order counting and difference calculations. Initial data support reduces computational errors. The counting process is restarted, and upon a transition in the output signal, the second Gray code value and its corresponding high-order binary count value are latched to obtain the second intermediate data. This accurately captures the count data at the second transition moment, establishing a correspondence with the data latched in the first instance. Compared to designs that only latch data for a single count, this provides complete foundational data for difference calculation, ensuring the calculation is based on sound reasoning. The second intermediate data is inverted, and the latched second Gray code value is converted to its binary inverse code. Then, it is added with the current low-order digits using a borrow operation to obtain the final low-order difference result. The high-order difference result is then calculated, accurately completing the difference calculation between the two counts, improving the accuracy and completeness of the difference calculation, and avoiding counting deviations that occur during the borrowing process. The low-order and high-order difference results are combined and output to provide the complete final count difference, ensuring the completeness and practicality of the counting result and meeting actual counting output requirements.

[0070] The present invention has been disclosed above. Without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and embodiments shown herein. < / m> < / m> < / m> < / n:m> < / m> < / m> < / m> < / m>

Claims

1. A counter for a column-level single-slope ADC in an image sensor, characterized in that, The counter includes: a Gray code generation module and a counting system connected in communication; The Gray code generation module is used to generate the Gray code values ​​required for counting; The counting system includes several counting units for receiving the Gray code value and performing counting operations. Each counting unit includes: The low-order latch module is used to receive the Gray code value and the compute signal from the Gray code generation module, and latch the current Gray code value when the compute signal changes. The conversion module is used to convert latched Gray code values ​​into binary code; The adder module is used to perform addition operations on the converted binary code values; The high-order counting module is used to selectively receive the set latch signal from the low-order latch module or the carry signal from the adder module to perform binary counting. The output latch module is used to latch and output the final count value in the high-order counting module.

2. The counter for a column-level single-slope ADC of an image sensor according to claim 1, characterized in that, It also includes an intermediate latch connected between the low-order latch module and the high-order counter module, used to latch the highest-order Gray code output by the low-order latch module and serve as the clock control signal for the high-order counter module.

3. The counter for a column-level single-slope ADC of an image sensor according to claim 2, characterized in that, The low-order latch module includes: The input control circuit receives the first enable signal and the compout signal, and is used to control the start of the latching function; Multiple latch units are provided, with their data input terminals connected to the Gray code generation module and their control terminals connected to the output terminal of the input control circuit. These units are used to latch the current Gray code value when the compout signal changes and output it to the conversion module. An initialization circuit receives a second enable signal and a third enable signal to initialize the output of the low-order latch module to a predetermined value before counting begins. The first enable signal, the second enable signal, and the third enable signal are generated by a digital circuit connected to the counter.

4. The counter for a column-level single-slope ADC of an image sensor according to claim 3, characterized in that, The conversion module includes a conversion circuit composed of several logic gates. The conversion circuit is controlled by a fourth enable signal. When the fourth enable signal is valid, the conversion circuit is turned on and converts the input Gray code value into the corresponding binary inverse code output. The fourth enable signal is generated by a digital circuit connected to a counter.

5. The counter for a column-level single-slope ADC of an image sensor according to claim 4, characterized in that, The adder module includes multiple cascaded trigger units, which, under the action of an external addition control pulse sequence, add the binary inverse code of the conversion module to the inverse code inside the adder module, and generate an addition carry signal to be output to the high-order counting module.

6. The counter for a column-level single-slope ADC of an image sensor according to claim 1 or 5, characterized in that, The high-order counting module includes: The first flip-flop group receives the signal from the intermediate latch at its clock input terminal to implement binary decrement counting. The second flip-flop group receives the carry signal from the adder module at its clock input terminal, and is used to implement a counting operation with borrow. The operating mode of the high-order counting module is controlled by an external path selection signal to select whether to receive input signals from the intermediate latch or the adder module.

7. The counter for a column-level single-slope ADC of an image sensor according to claim 6, characterized in that, Both the adder module and the high-order counter module receive the same set and invert control signals to initialize the internal counting state and invert the values.

8. A counting method for a column-level single-slope ADC in an image sensor, characterized in that, A counter applied to any one of claims 1 to 7 for a column-level single-slope ADC of an image sensor, comprising: The low-order latch module, adder module, and high-order counter module in the counter are reset to set their internal counting states to zero. The Gray code generation module is started to count, and when the compout signal changes, the first Gray code value is latched by the low-bit latching module and the current high-bit binary code value is latched by the high-bit counting module. The initial value and the high-order binary code value of the adder are inverted, and the first Gray code value is converted into the inverse code of the low-order binary code value using the conversion module. The adder module adds the inverse code of the low-order binary code value to the initial value and stores it. The code value stored in the adder and the data stored in the high-order counting module together constitute the first intermediate data. The counting process is restarted, and the second Gray code value and the corresponding high-order binary count value are latched when the compout signal changes. The code value stored in the adder and the code value of the high-order counter are inverted; the conversion module converts the second Gray code value into the inverse of the binary code value; The adder module adds the inverse of the binary code value to the stored code value and performs an addition operation with borrow; it obtains the final low-bit difference result and the high-bit difference result; and it combines the low-bit difference result and the high-bit difference result for output.

9. The counting method for a column-level single-slope ADC of an image sensor according to claim 8, characterized in that, When the comparator output signal of a certain counting unit changes, the corresponding low-order latch module latches the current Gray code value, while the Gray code generation module continues to operate and provides Gray code values ​​for other counting units.

10. The counting method for a column-level single-slope ADC of an image sensor according to claim 8, characterized in that, The first intermediate data is inverted, and the latched first Gray code value is converted to binary one's complement. Then, an addition operation is performed with the inverted lower-order digits to update the lower-order digits and prepare the initial state for the higher-order counting, including: The current output value of the counter is inverted bit by bit using a control signal; The conversion module is activated to convert the Gray code value latched by the low-order latch module into binary code. Then, by sequentially inputting pulse signals, the adder module is controlled to perform the addition of the binary code with the inverted low-order value.

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