An all-digital IMD2 cancellation circuit

Abstract

The application discloses a kind of full digital IMD2 elimination circuits, including four times interpolation module, time delay estimation module, selection alignment module, IMD2 elimination module.The four times interpolation module is used to carry out four times interpolation to a reference signal, and four interpolation reference signals are obtained.The time delay estimation module is used to accurately estimate the time delay between received signal and reference signal.The selection alignment module is used to align the selected interpolation reference signal and received signal.The IMD2 elimination module is used to obtain the error signal of received signal and aligned interpolation reference signal by least mean square LMS filtering algorithm, and the IMD2 elimination signal is obtained by subtracting the error signal from received signal.The application first accurately estimates the time delay of transmission signal to receiving end, then aligns the reference signal and received signal according to the time delay, and finally performs IMD2 elimination on the received signal, so as to meet the high accuracy requirement of IMD2 elimination caused by high sampling rate of 5G signal.

Description

Technical Field

[0001] This invention relates to a digital circuit for eliminating second-order intermodulation distortion (IMD2). Background Technology

[0002] 5G mobile communication systems employ Frequency Division Duplex (FDD) technology to improve spectral efficiency and data rates. This simultaneous transmit (TX) and receive (RX) operation can cause transmitted signals to leak to the receiver, resulting in second-order intermodulation distortion (IMD2). Receiver front-end components—such as low-noise amplifiers (LNAs) and mixers—exhibit a degree of nonlinearity. When the receiver receives a portion of the transmitted signal, IMD2 is introduced into the received signal, significantly impacting the signal-to-noise ratio (SNR) of 5G mobile communication, increasing the bit error rate, and reducing system capacity and coverage.

[0003] One existing method for reducing IMD2 in 5G chips is through factory calibration using software algorithms. However, factory calibration is time-consuming and expensive. Furthermore, test results from already-released 5G chips show that factory calibration is ineffective. Therefore, a more flexible and cost-effective IMD2 elimination method is needed. Summary of the Invention

[0004] The technical problem to be solved by this invention is that the delay caused by the propagation path of the transmitted signal leaking to the receiver will affect the accuracy and effectiveness of IMD2 elimination, and how to improve the accuracy and effectiveness of IMD2 elimination.

[0005] To address the aforementioned technical problems, this invention proposes a fully digital IMD2 cancellation circuit, comprising a quadruple interpolation module, a delay estimation module, a selection alignment module, and an IMD2 cancellation module. The quadruple interpolation module performs quadruple interpolation on one reference signal to obtain four interpolated reference signals. The delay estimation module accurately estimates the delay between the received signal and the reference signal, and transmits the delay estimate and a selection signal to the selection alignment module; the selection signal is used to select only one of the four interpolated reference signals to retain. The selection alignment module selects only one of the four interpolated reference signals according to the selection signal, aligns the selected interpolated reference signal with the received signal, and transmits the aligned interpolated reference signal to the IMD2 cancellation module. The IMD2 cancellation module obtains the error signal between the received signal and the aligned interpolated reference signal using a least mean square (LMS) filtering algorithm, subtracts the error signal from the received signal, and obtains the IMD2-cancelled received signal.

[0006] As a first example, the time delay estimation module performs cross-correlation operations on one continuously sliding received signal and four interpolated reference signals respectively, obtaining four sets of absolute values ​​of correlation, which are called correlation peaks; retains the interpolated reference signal containing the largest correlation peak, represented by a selection signal; removes the remaining interpolated reference signals; obtains the integer time delay part of the received signal and the reference signal based on the number of sliding steps corresponding to the largest correlation peak; obtains the fractional time delay part of the received signal and the reference signal based on the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal; the integer time delay part and the fractional time delay part constitute the complete time delay estimate of the received signal and the reference signal.

[0007] As a second example, the time delay estimation module performs cross-correlation operations on one continuously sliding received signal and four interpolated reference signals respectively, obtaining four sets of absolute values ​​of correlation, which are called correlation peaks. Then, based on the difference between the maximum, second largest, and third largest values ​​of each set of correlation peaks, it determines whether there are noise spikes. After removing noise spikes, the true maximum correlation peak is obtained. The interpolated reference signal corresponding to the true maximum correlation peak is retained, and the remaining interpolated reference signals are removed. The integer time delay part between the received signal and the reference signal is obtained based on the number of sliding steps of the received signal corresponding to the true maximum correlation peak. The fractional time delay part between the received signal and the reference signal is obtained based on the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal. The integer time delay part and the fractional time delay part constitute the complete time delay estimate of the received signal and the reference signal.

[0008] Furthermore, in the two examples above, the integer delay from the reference signal to the received signal is T×n-Δ; T is the quotient of the sampling period of the reference signal and the clock period; n is the number of slides of the received signal corresponding to the true maximum correlation peak; if the retained reference signal is the first interpolated reference signal, Δ is 0; if the retained reference signal is the second interpolated reference signal, Δ is T / 4; if the retained reference signal is the third interpolated reference signal, Δ is T / 2; if the retained reference signal is the fourth interpolated reference signal, Δ is 3T / 4; the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal, in clock periods, is the fractional delay δ from the reference signal to the received signal; the complete delay estimate between the received signal and the reference signal is T×n-Δ+δ.

[0009] Furthermore, the difference between the maximum, second largest, and third largest values ​​in each group of correlation values ​​is analyzed to determine whether the correlation peak is sharp. If the second largest and third largest values ​​are much smaller than the maximum value, it indicates that the energy is concentrated, and a low-order LMS is used. If multiple peaks of the maximum, second largest, and third largest values ​​are close to each other, it indicates that the energy is dispersed, and a high-order LMS is used.

[0010] As a preferred example, the time delay estimation module includes five compression modules, four buffer modules, one sliding buffer module, four correlation modules, four comparison modules, and a decimal time delay recording module. The compression modules are used to compress the four interpolated reference signals and one received signal, respectively, using either normal compression mode or differential compression mode. The buffer modules are used to buffer the compression results of the first L sampling points of the four interpolated reference signals, where L represents the correlation length of the cross-correlation operation. The sliding buffer module is used to slide and buffer the compression results of the L sampling points of the received signal. The correlation modules are used to perform cross-correlation operations of length L on the four interpolated reference signals and one received signal, respectively. The comparison modules are used to record the maximum, second-largest, and third-largest absolute values ​​of the correlation values ​​from the four sets of correlation values ​​sent from the four correlation modules, as well as the correlation value after which the received signal has slid, and calculate the sum of the absolute values ​​of each set of correlation values. The fractional delay recording module is used to record and calculate the number of clock cycles between the first sampling point of the four interpolated reference signal and the first sampling point of the received signal, as the fractional delay between each interpolated reference signal and the received signal.

[0011] As a preferred example, the alignment selection module includes a selection module, a storage module, and a counting module. The selection module selects only one interpolated reference signal from the four interpolated reference signals to participate in IMD2 elimination, based on a selection signal, and sends it to the storage module and the counting module. The storage module uses the valid indication signal of the selected interpolated reference signal as a write enable to write that interpolated reference signal into the storage module; it also uses the valid indication signal of the received signal as a read enable after receiving a start signal from the counting module to read the retained interpolated reference signal from the storage module, and transmits it as the aligned interpolated reference signal to the IMD2 elimination module; the phase of the aligned interpolated reference signal is aligned with the phase of the received signal. The counting module starts a counter from zero upon receiving the first signal of the retained interpolated reference signal, incrementing the counter by one each clock cycle until the counter value equals the complete time delay estimate, at which point it stops counting and transmits the start signal to the storage module.

[0012] The technical effect achieved by this invention is as follows: first, the time delay from the transmitted signal to the receiver is accurately estimated; then, the reference signal and the received signal are aligned according to the time delay; and finally, IMD2 cancellation is performed on the received signal, thereby meeting the high accuracy requirement of IMD2 cancellation caused by the high sampling rate of 5G signals. Attached Figure Description

[0013] Figure 1This is a schematic diagram of the structure of the all-digital IMD2 elimination circuit proposed in this invention.

[0014] Figure 2 yes Figure 1 A schematic diagram of the delay estimation module 1 in the diagram.

[0015] Figure 3 yes Figure 1 The diagram shows the structure of the alignment selection module 2.

[0016] The attached diagrams are labeled as follows: Delay estimation module 1, Compression modules 111 to 115, Cache modules 116 to 119, Sliding cache module 120, Correlation modules 121 to 124, Comparison modules 125 to 128, Decimal delay recording module 129, Selection alignment module 2, Selection module 21, Storage module 22, Counter 23, IMD2 elimination module 3, and Quadruple interpolation module 4. Detailed Implementation

[0017] Please see Figure 1 The all-digital IMD2 cancellation circuit proposed in this invention includes a quadruple interpolation module 4, a delay estimation module 1, a selection alignment module 2, and an IMD2 cancellation module 3. The entire circuit has two input signals: a reference signal and a received (RX) signal. The reference signal is a key auxiliary signal used to estimate and cancel second-order intermodulation distortion, typically originating from the transmitted (TX) signal of the 5G mobile communication system transmitter or its nonlinear function (such as a squared term). The received signal is the signal received by the receiver of the 5G mobile communication system, containing the transmitted signal leaked to the receiving end, i.e., the IMD2 component. The sampling rates of the received signal and the reference signal are aligned using upsampling and downsampling filters. The entire circuit is used to eliminate the IMD2 component in the received signal at the receiving end of the 5G mobile communication system. The entire circuit outputs only one signal, which is the IMD2-cancelled received signal.

[0018] The quadruple interpolation module 4 is used to perform quadruple interpolation on one original reference signal to obtain four interpolated reference signals. Interpolation is used to overcome the sampling rate limitation of the original reference signal and achieve sub-sample time delay estimation accuracy. For example, if one original reference signal is data with 1024 sampling points, an additional 3072 sampling points are added between the original 1024 sampling points through uniform interpolation, increasing the total number of sampling points to 4096. The 4096 sampling points are then divided into four channels, each with 1024 sampling points, which are the four interpolated reference signals. The first interpolated reference signal consists of sampling points 0, 4, ..., 4092. The second interpolated reference signal consists of sampling points 1, 5, ..., 4093. The third interpolated reference signal consists of sampling points 2, 6, ..., 4094. The fourth interpolated reference signal consists of sampling points 3, 7, ..., 4095. Each interpolated reference signal has the same time difference as the sampling points of the previous interpolated reference signal. Quadruple interpolation can improve the signal alignment accuracy to 1 / 4 of the original signal sampling period.

[0019] The time delay estimation module 1 is used to accurately estimate the time delay between the received signal and the reference signal, and transmits the time delay estimate and the selection signal (collectively referred to as the estimation result) to the selection and alignment module 2. The selection signal refers to selecting only one of the four interpolated reference signals to retain.

[0020] As a first example, the four-channel interpolated reference signal consists of 1024 sample points per channel. After initially receiving 1024 sample points (sample point 0 to sample point 1023), the received signal is cross-correlated with each of the four interpolated reference signals, and the absolute values ​​of the four correlation peaks are recorded. The cross-correlation operation involves multiplying and summing the corresponding sample points of the two signals. Then, the received signal is slid, removing sample point 0 and adding sample point 1024, resulting in 1024 sample points (sample point 1 to sample point 1024); this is then cross-correlated with the four interpolated reference signals again, and the four correlation peaks are recorded. Then, the received signal is slid, removing sample point 1 and adding sample point 1025, resulting in 1024 sample points (sample point 2 to sample point 1025); this is then cross-correlated with the four interpolated reference signals again, and the four correlation peaks are recorded. Similarly, if the received signal slides 1000 times, then a total of 4000 correlation peaks are calculated with the four interpolated reference signals. The received signal contains components leaked from the transmitted signal. The cross-correlation result is maximized when the phase of a certain interpolated reference signal best matches the phase of the received signal in a certain sliding state. Among the four sets of correlation peaks between the continuously sliding received signal and the four interpolated reference signals, the interpolated reference signal containing the largest correlation peak is retained and represented by a selection signal; the other three interpolated reference signals are removed. Among the 1000 correlation peaks of the retained interpolated reference signal, if the largest correlation peak appears at the 500th slide of the received signal, the position of the largest correlation peak is recorded as 500 (i.e., the largest correlation peak corresponds to a slide number n of 500 for the received signal). This indicates that the received signals from sampling points 500 to 1523 have the highest correlation with the retained interpolated reference signal, meaning that the retained interpolated reference signal was sent after passing through "500 × the sampling period of the received signal".

[0021] As a second example, the maximum, second-largest, third-largest, and so on values ​​among the four sets of correlation peaks between the continuously sliding received signal and the four interpolated reference signals are statistically analyzed. If the second-largest or third-largest value in a certain set of correlation peaks is close to the maximum value, it is determined to be a noise spike. The noise spike in that set of correlation peaks is removed, and the Xth largest value that is not subsequently determined to be a noise spike is taken as the true maximum correlation peak in that set of correlation peaks. The interpolated reference signal containing the true maximum correlation peak is retained and represented by a selection signal; the other three interpolated reference signals are removed. The number of times the true maximum correlation peak of the retained interpolated reference signal corresponds to the sliding of the received signal is recorded as n. The second example adds the operation of judging and removing noise spikes based on the first example, which can obtain more accurate time delay estimation results.

[0022] In the two examples above, the integer time delay from the original reference signal to the received signal is represented as T×n-Δ. T is the quotient of the sampling period of the original reference signal and the clock period. For example, if there is a sampling point of the original reference signal every 8 clock cycles, then T is 8. The sampling period of the original reference signal is equal to the sampling period of the received signal. If the retained reference signal is the first interpolated path, Δ is 0. If the retained reference signal is the second interpolated path, Δ is T / 4. If the retained reference signal is the third interpolated path, Δ is T / 2. If the retained reference signal is the fourth interpolated path, Δ is 3T / 4. The distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal (in clock cycles) is the fractional time delay δ from the original reference signal to the received signal. The integer time delay T×n-Δ and the fractional time delay δ constitute the complete time delay estimate T×n-Δ+δ between the received signal and the reference signal.

[0023] The selection and alignment module 2 is used to select only one of the four interpolated reference signals according to the selection signal, and align the selected interpolated reference signal with the received signal, and then pass the aligned interpolated reference signal to the IMD2 elimination module 3.

[0024] The IMD2 elimination module 3 is used to obtain the error signal between the received signal and the interpolated reference signal after alignment by using the LMS (Least Mean Square) filtering algorithm, and subtract the error signal from the received signal to obtain the received signal after IMD2 elimination.

[0025] Please see Figure 2The latency estimation module 1 includes five compression modules 111 to 115, four caching modules 116 to 119, one sliding caching module 120, four correlation modules 121 to 124, four comparison modules 125 to 128, and a decimal latency recording module 129.

[0026] There are five compression modules, 111 to 115, which are used to compress the four interpolated reference signals and one received signal, respectively. The compression methods include ordinary compression mode and differential compression mode. These compression modules are used to compress multi-bit data into 2 bits, saving a significant amount of computational logic area. The introduction of differential compression mode increases processing flexibility and robustness.

[0027] There are four cache modules 116 to 119, each used to cache the compression results of the first L sampling points of the four-channel interpolated reference signal, where L represents the correlation length of the cross-correlation operation. For example, if the reference signal is data from 1024 sampling points, then L is 1024.

[0028] There is only one sliding buffer module 120, which uses L registers to slide and buffer the compression results of L sample points of the received signal. When all L registers are full, the sliding buffer module 120 notifies the subsequent modules to perform cross-correlation calculations. After that, the compression results of the new input sample points of the received signal are stored in the last of the L registers. The data in each register is shifted to the previous register, and the data in the first register is deleted, thus realizing the sliding buffer.

[0029] There are four correlation modules 121 to 124, which are used to perform cross-correlation operations of length L on the four interpolated reference signals and one received signal, respectively. The principle can be expressed by the following formula: Where R[m] represents the correlation value of the m-th cross-correlation operation, and m is an integer ranging from 0 to the sliding range S. L represents the correlation length. ref_data[k] represents the compressed interpolated reference signal. rx_data[k+m] represents the compressed received signal.

[0030] There are four comparison modules 125 to 128, which are used to record the maximum, second largest, third largest, etc. of the absolute value of the correlation value of each correlation module from the S+1 correlation values ​​sent by the four correlation modules 121 to 124, as well as their position information n in the sliding sequence (which is the correlation value after which the received signal has slid), and to calculate the sum of the absolute values ​​of all S+1 correlation values ​​of each correlation module.

[0031] There is only one fractional delay recording module 129, which is used to record the number of clock cycles between the first sampling point of the first interpolated reference signal and the first sampling point of the received signal, as the fractional delay FD1 of the first interpolated reference signal and the received signal. The fractional delay FD2 of the second interpolated reference signal and the received signal is FD1 plus 1 / 4 of the sampling period of the original reference signal. The fractional delay FD3 of the third interpolated reference signal and the received signal is FD1 plus 1 / 2 of the sampling period of the original reference signal. The fractional delay FD4 of the fourth interpolated reference signal and the received signal is FD1 plus 3 / 4 of the sampling period of the original reference signal.

[0032] The first example of the time delay estimation module 1 selects the largest correlation peak from four sets of correlation peaks between the continuously sliding received signal and the four interpolated reference signals, retains the corresponding interpolated reference signal, and removes the remaining interpolated reference signals. Then, it calculates the integer time delay T×n-Δ between the received signal and the original reference signal. The number of clock cycles recorded by the fractional time delay recording module 129 is denoted as δ. Therefore, the complete time delay estimate between the received signal and the original reference signal is T×n-Δ+δ.

[0033] The second example of the time delay estimation module 1, based on the absolute values ​​(correlation peaks) of four sets of correlation values ​​between the continuously sliding received signal and the four interpolated reference signals, first determines whether there are noise spikes, removes the noise spikes, and then determines the true maximum correlation peak. The largest true maximum correlation peak is selected from the four interpolated reference signals, and the corresponding interpolated reference signal is retained, while the remaining interpolated reference signals are removed. Subsequently, the integer time delay T×n-Δ between the received signal and the original reference signal is calculated. The number of clock cycles recorded by the fractional time delay recording module 129 is denoted as δ. Therefore, the complete time delay estimate between the received signal and the original reference signal is T×n-Δ+δ.

[0034] The order of an LMS filter is typically determined by the energy concentration of the channel or interference path. The second example of the delay estimation module 1 determines whether the correlation peaks are sharp (i.e., whether the energy is concentrated in a few taps) by analyzing the differences between the maximum, second-largest, and third-largest values ​​in each set of correlation peaks. If the second-largest and third-largest values ​​are much smaller than the maximum value, it indicates concentrated energy, and a lower-order LMS can be used. If multiple peaks of the maximum, second-largest, and third-largest values ​​are close, it indicates dispersed energy, requiring a higher-order LMS to cover multipath or wide-tailed interference. Therefore, the required LMS filter order can be estimated based on the attenuation rate or effective support length of the correlation peaks.

[0035] Please see Figure 3 The alignment selection module 2 includes a selection module 21, a storage module 22, and a counting module 23.

[0036] The selection module 21 is used to select only one interpolated reference signal from the four interpolated reference signals to participate in IMD2 elimination according to the selection signal, and send it to the storage module 22 and the counting module 23.

[0037] The storage module 22 is used to write the interpolated reference signal selected by the selection module 21 into the storage module 22 as a write enable signal. The storage module 22 is also used to read the retained interpolated reference signal from the storage module 22 after receiving a start signal from the counting module 23, using the valid indicator signal of the received signal as a read enable signal, and then transmit this as the aligned interpolated reference signal to the IMD2 elimination module 3. The phase of the aligned interpolated reference signal is aligned with the phase of the received signal, and can be used for IMD2 elimination.

[0038] The counting module 23 is used to start the counter from zero after receiving the first signal of the retained interpolated reference signal. The counter increments by one every clock cycle until the value of the counter is equal to the time delay parameter (i.e., the complete time delay estimate T×n-Δ+δ), then the counting stops and the start signal is transmitted to the storage module 22.

[0039] The IMD2 elimination module 3 includes an LMS filtering module and an error elimination module, etc., which are existing technologies and will not be described in detail here.

[0040] The all-digital IMD2 cancellation circuit proposed in this invention offers greater flexibility and adaptability. By monitoring and estimating the results, the software adjusts the configuration parameters of the digital circuit in real time, adapting to complex environmental changes such as signal conditions, temperature fluctuations, and aging effects, without requiring physical adjustments to the circuit parameters. The digital circuit design also offers advantages such as small area and low power consumption.

[0041] In the all-digital IMD2 cancellation circuit proposed in this invention, the core of digital signal processing for IMD2 cancellation is adaptive filtering, which dynamically adjusts the filter coefficients to counteract distortion caused by nonlinear components. The transmitted signal generates a reference signal, which, after passing through the adaptive filter, is compared with the received signal to generate an error signal. This error signal is used for IMD2 cancellation and updating the filter coefficients. However, the propagation delay caused by the transmitted signal leaking to the receiver will affect the accuracy and effectiveness of IMD2 cancellation. The high sampling rate of 5G signals requires sufficiently accurate delay calculation; otherwise, the reference signal and IMD2 cannot be aligned. This invention adds a delay estimation module and an alignment selection module before the traditional IMD2 cancellation circuit, ensuring that the reference signal entering the IMD2 cancellation module is aligned with the received signal beforehand, thus improving the accuracy of IMD2 cancellation. Considering the low latency requirements of 5G communication, IMD2 cancellation is performed online in real-time in a pipeline manner, without offline processing, minimizing the impact on the receiving path processing time.

[0042] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fully digital IMD2 cancellation circuit, characterized in that, Includes a quadruple interpolation module, a delay estimation module, a selection alignment module, and an IMD2 elimination module; The four-fold interpolation module is used to perform four-fold interpolation on one reference signal to obtain four interpolated reference signals; The time delay estimation module is used to accurately estimate the time delay between the received signal and the reference signal, and transmits the time delay estimate and the selection signal to the selection alignment module; the selection signal is used to select only one of the four interpolated reference signals to retain. The selection alignment module is used to select only one of the four interpolated reference signals according to the selection signal, and align the selected interpolated reference signal with the received signal, and then pass the aligned interpolated reference signal to the IMD2 elimination module. The IMD2 elimination module is used to obtain the error signal between the received signal and the aligned interpolated reference signal through the Least Mean Square (LMS) filtering algorithm, and subtract the error signal from the received signal to obtain the IMD2-eliminated received signal.

2. The all-digital IMD2 elimination circuit according to claim 1, characterized in that, The time delay estimation module performs cross-correlation operations on one continuously sliding received signal and four interpolated reference signals respectively, obtaining four sets of absolute values ​​of correlation, which are called correlation peaks; retains the interpolated reference signal containing the largest correlation peak, represented by a selection signal; removes the remaining interpolated reference signals; obtains the integer time delay part of the received signal and the reference signal based on the number of sliding steps corresponding to the largest correlation peak; obtains the fractional time delay part of the received signal and the reference signal based on the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal; the integer time delay part and the fractional time delay part constitute the complete time delay estimate of the received signal and the reference signal.

3. The all-digital IMD 2 cancellation circuit of claim 1, wherein, The time delay estimation module performs cross-correlation calculations on one continuously sliding received signal and four interpolated reference signals respectively, obtaining four sets of absolute values ​​of correlation, which are called correlation peaks. Then, based on the difference between the maximum, second largest, and third largest values ​​of each set of correlation peaks, it determines whether there are noise spikes. After removing noise spikes, the true maximum correlation peak is obtained. The interpolated reference signal corresponding to the true maximum correlation peak is retained, and the remaining interpolated reference signals are removed. The integer time delay part between the received signal and the reference signal is obtained based on the number of sliding steps of the received signal corresponding to the true maximum correlation peak. The fractional time delay part between the received signal and the reference signal is obtained based on the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal. The integer time delay part and the fractional time delay part constitute the complete time delay estimate of the received signal and the reference signal.

4. The all-digital IMD 2 cancellation circuit of claim 2 or 3, wherein, The integer time delay from the reference signal to the received signal is T×n-Δ; T is the quotient of the sampling period of the reference signal and the clock period; n is the number of slides of the received signal corresponding to the true maximum correlation peak; if the retained reference signal is the first interpolated reference signal, Δ is 0; if the retained reference signal is the second interpolated reference signal, Δ is T / 4; if the retained reference signal is the third interpolated reference signal, Δ is T / 2; if the retained reference signal is the fourth interpolated reference signal, Δ is 3T / 4; the distance between the first sampling point of the retained interpolated reference signal and the first sampling point of the received signal, in clock periods, is the fractional time delay δ from the reference signal to the received signal; the complete time delay estimate between the received signal and the reference signal is T×n-Δ+δ.

5. The all-digital IMD 2 cancellation circuit of claim 2 or 3, wherein, To determine whether the correlation peak is sharp, analyze the differences between the maximum, second largest, and third largest values ​​in each group of correlation values. If the second largest and third largest values ​​are much smaller than the maximum value, it indicates that the energy is concentrated, and a low-order LMS is used. If multiple peaks of the maximum, second largest, and third largest values ​​are close to each other, it indicates that the energy is dispersed, and a high-order LMS is used.

6. The all-digital IMD 2 cancellation circuit of claim 1, wherein, The latency estimation module includes five compression modules, four caching modules, one sliding caching module, four correlation modules, four comparison modules, and a decimal latency recording module; The compression module is used to compress the four interpolated reference signals and one received signal, and the compression methods are divided into ordinary compression mode and differential compression mode. The buffer module is used to buffer the compression results of the first L sampling points of the four interpolated reference signals, where L represents the correlation length of the cross-correlation operation. The sliding buffer module is used to slide buffer the compression results of L sampling points of the received signal; The relevant modules are used to perform cross-correlation operations of length L on the four interpolated reference signals and one received signal, respectively. The comparison module is used to record the maximum, second largest, and third largest absolute values ​​of the correlation values ​​of each correlation module from the four sets of correlation values ​​sent by the four correlation modules, as well as the correlation value after which the received signal has slid for a certain number of times, and to calculate the sum of the absolute values ​​of each set of correlation values. The fractional delay recording module is used to record and calculate the number of clock cycles between the first sampling point of the four interpolated reference signal and the first sampling point of the received signal, as the fractional delay between each interpolated reference signal and the received signal.

7. The all-digital IMD 2 cancellation circuit of claim 1, wherein, The alignment selection module includes a selection module, a storage module, and a counting module; The selection module is used to select only one interpolated reference signal from the four interpolated reference signals to participate in IMD2 elimination according to the selection signal, and send it to the storage module and the counting module. The storage module is used to use the valid indication signal of the interpolated reference signal selected by the selection module as a write enable, and write the interpolated reference signal into the storage module. It is also used to, after receiving the start signal from the counting module, use the valid indication signal of the received signal as a read enable, read the retained interpolated reference signal from the storage module, and pass it to the IMD2 elimination module as the aligned interpolated reference signal; the phase of the aligned interpolated reference signal is aligned with the phase of the received signal. The counting module is used to start the counter from zero after receiving the first signal of the retained interpolated reference signal. The counter increments by one every clock cycle until the value of the counter is equal to the complete time delay estimate, at which point the counting stops and the start signal is transmitted to the storage module.

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