Soft reset retry method

Abstract

The application belongs to the technical field of software and provides a soft reset retry method applied to an electronic device containing firmware, a host controller and an embedded storage device; when the firmware initializes the storage device, the host controller is initialized and configured as an initial state of a device identification stage, an idle state command is sent to make the storage device enter an idle state; an operation condition command is sent according to a preset polling rule, and whether internal initialization is completed is judged according to a busy state indication in returned information; if the initialization is completed, the device identification stage is entered; if the initialization is not completed continuously within a preset timeout window, it is determined that polling is timed out and the number of retries is judged; when the number of retries does not reach a maximum number, the host controller is soft reset and reconfigured, the idle state command is sent again, and polling is re-performed after waiting; when the number of retries reaches the maximum number, a device error state is returned and the initialization is ended. The application can solve the problem that the embedded storage device is directly determined to fail by the firmware due to polling timeout of the operation condition command in the initialization process.

Description

Technical Field

[0001] This invention relates to the field of software technology, and in particular to a soft reset and retry method. Background Technology

[0002] Embedded storage devices are typically used as boot or data storage media for electronic devices. During power-on or reboot, firmware, in conjunction with the host controller, needs to initialize and identify the storage device. Existing initialization processes usually rely on protocol commands to determine if the storage device has completed internal power-on preparation. If the storage device's response preparation time is prolonged due to factors such as component differences, temperature changes, short-term power outages and reboots, or incomplete internal background processing, the firmware may directly determine initialization failure after the waiting period expires and return an error status to the upper layer. This approach lacks the ability to recover from temporary abnormal states, easily leading to probabilistic device boot failures. This is especially problematic in applications with high boot reliability requirements, such as servers, industrial control equipment, and embedded terminals, affecting overall system stability and storage media compatibility. Simply extending the waiting time or adjusting the hardware design to circumvent this could increase normal boot time or implementation costs, and it's difficult to adapt to initialization differences between different batches and manufacturers of storage devices. Summary of the Invention

[0003] In view of the above technical problems, the present invention provides a soft reset retry method to solve the problem that embedded storage devices are directly judged as failing by the firmware due to the timeout of operation condition command polling during the initialization process. This allows the firmware to restore the host controller and re-initiate the initialization polling without performing a power-off reset on the power supply circuit of the storage device, thereby improving the fault tolerance capability and startup reliability of the embedded storage device initialization.

[0004] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0005] This invention discloses a soft reset retry method, applied to an electronic device including firmware, a host controller, and an embedded storage device. The method includes... When the firmware initiates the initialization of the embedded storage device, it performs hardware initialization on the host controller and configures the host controller to an initial operating state suitable for the device identification phase. The host controller sends a protocol-defined idle state command to the embedded storage device, causing the embedded storage device to enter an idle state; The host controller sends a protocol-defined operation condition command to the embedded storage device according to a preset polling rule, receives the operation condition information returned by the embedded storage device, and determines whether the embedded storage device has completed internal initialization based on the busy status indication in the operation condition information. When the busy status indicator indicates that the embedded storage device has completed internal initialization, the firmware enters the device identification phase. When the busy status indicator continues to indicate that the embedded storage device has not completed internal initialization within the preset timeout window, it is determined that the operation condition command polling timeout has occurred, and it is determined whether the number of soft reset retries executed has reached the preset maximum number of retries. When the number of soft reset retries performed has not reached the preset maximum number of retries, the number of soft reset retries performed is updated, a soft reset is performed on the host controller, the host controller is reconfigured to the initial working state, the idle state command is sent to the embedded storage device again, and after a preset waiting condition is met, the polling for executing the operation condition command is returned. When the number of soft reset retries reached the preset maximum number of retries, the firmware returned a device error status to the upper layer and ended the initialization of the embedded storage device.

[0006] Furthermore, the embedded storage device is an embedded multimedia memory, the idle state command is a protocol command used to put the embedded multimedia memory into an idle state and trigger an internal reset process, the operation condition command is a protocol command used to make the embedded multimedia memory return operation condition register information, the operation condition information includes host supported voltage range confirmation information and the busy state indication, and the firmware determines whether the embedded multimedia memory has completed internal power-on initialization by whether the busy state indication is set.

[0007] Furthermore, the preset polling rules include: After establishing the polling timing start point, continuously send the operation condition commands; After each sending of the operation condition command, determine whether the command response was successful. The operation condition information is parsed when the command response is successful. Continue sending the operation condition command when the busy status indicator is not set and the preset timeout window is not met; When the command response is abnormal and the busy status indicator remains unset, resulting in the preset timeout window being met, the operation condition command polling timeout is determined to have occurred.

[0008] Furthermore, performing a soft reset on the host controller includes: A software reset is performed on the command sending circuit, data receiving circuit, control state machine, and error status register of the host controller to clear the command error status, data error status, and interrupt pending status generated by the host controller in the previous round of initialization polling, so that the host controller recovers from the abnormal polling state to a controllable state that can re-initiate the initialization command; wherein, the software reset does not perform a power-off reset on the power supply circuit of the embedded storage device.

[0009] Furthermore, reconfiguring the host controller to the initial operating state includes: The host controller is reconfigured to the conservative parameter set corresponding to the device identification phase. The conservative parameter set includes initialization clock parameters, initial bus transmission parameters, command sending parameters, data receiving parameters, and controller power status parameters, so that the host controller can regain stable operating conditions to send the idle state command and the operating condition command after performing the soft reset.

[0010] Furthermore, the preset waiting conditions include: After sending the idle state command to the embedded storage device again, the device waits until a preset delay strategy is met. The preset delay strategy adopts at least one of a fixed waiting strategy, a waiting strategy that increases with the number of retries, and an adaptive waiting strategy. The adaptive waiting strategy determines the waiting time based on at least one of the following: the polling time of the previous round, the current retry order, the device operating temperature, historical initialization failure records, and the platform startup reliability strategy, so as to provide the embedded storage device with a recovery window to complete the background processing of internal reset, garbage collection, and wear leveling.

[0011] Furthermore, the preset maximum number of retries is determined by at least one of the firmware configuration items, platform configuration database, compilation configuration, device description table, and startup strategy; the firmware does not trigger a soft reset retry when the operation condition command polling is successful, but only enables a soft reset retry when the operation condition command polling times out, and only returns the device error status to the upper layer after the number of executed soft reset retries reaches the preset maximum number of retries.

[0012] Furthermore, the subsequent device identification phase includes at least one of reading device identification information, allocating device address, configuring transmission bus, adjusting working clock, and completing block device registration; the firmware records at least one of the following each time a soft reset retry is triggered: retry sequence, timeout reason, polling time, operation condition information, time stamp, and recovery result, and records the information through at least one of serial port log, non-volatile storage log, and debug log to locate initialization compatibility issues of the embedded storage device.

[0013] Furthermore, the firmware includes basic input / output system firmware, unified extensible firmware interface firmware, and boot firmware developed based on the unified extensible firmware interface framework; the electronic device includes one of a server, embedded terminal, industrial control equipment, and computer; when adapting to a storage device based on the Secure Digital Input / Output Protocol (SDIP), the method replaces the operation condition command with the application operation condition command in the SIP used to query working conditions and busy status, and maintains the same fault-tolerant process consisting of the idle status command, the host controller soft reset, the reconfiguration, and the preset waiting conditions.

[0014] Furthermore, the operation condition command polling timeout occurs during the initialization phase when the embedded storage device is powered off and powered on again after completing the preset data writing amount. When the firmware detects that the busy state indicator is not set, it determines that the embedded storage device is in a delayed reset state caused by incomplete internal background processing, and triggers the soft reset retry.

[0015] The technical solution of the present invention has the following beneficial effects: This invention improves the handling of timeouts in the operation condition command polling process of embedded storage devices by changing the approach from direct error reporting and exit to a limited number of soft reset retry processes. This allows the host controller to clear the erroneous state generated during the previous round of initialization after an abnormal polling and restore it to an initial working state suitable for device identification. Combined with idle state commands and waiting conditions, it then provides the storage device with a new internal reset and state recovery window. Therefore, when the storage device is temporarily unable to complete initialization due to internal background processing, temperature conditions, or individual device differences, the firmware can automatically attempt recovery, reducing the probability of startup failure. Furthermore, this invention is limited to triggering only when polling timeouts occur; it does not add extra startup procedures when initialization is successful normally, and it does not require changes to the storage device's power supply circuit or the addition of hardware components. It has the advantages of low implementation cost, good compatibility, transparency to users, and ease of firmware upgrade and deployment. By setting a maximum number of retries, it also prevents the firmware from remaining in the initialization phase for extended periods when the storage device experiences a real failure, thus balancing startup reliability and abnormal exit efficiency. Attached image description; Figure 1 This is a flowchart of the soft reset retry method in the embodiments of this specification. Detailed Implementation

[0017] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, systems, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0018] Furthermore, the accompanying drawings are merely illustrative of this disclosure. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor systems and / or microcontroller systems.

[0019] This invention provides a soft reset retry method. (Refer to...) Figure 1 The diagram shown is a flowchart of a robot dispensing control method according to an embodiment of the present invention. This method is applied to an electronic device including firmware, a host controller, and an embedded storage device. Specifically, the method may include the following steps S101-S107: In step S101, when the firmware starts initializing the embedded storage device, hardware initialization is performed on the host controller, and the host controller is configured to an initial operating state suitable for the device identification phase.

[0020] In this step, the firmware can be BIOS firmware, UEFI firmware, or boot firmware developed based on the UEFI framework, and the host controller can be an eMMC Host Controller. After the electronic device is powered on or restarted, the eMMC Host driver in the firmware first establishes the controller infrastructure environment required for communication with the embedded storage device, enabling the host controller to enter a state where it can send initialization commands from an unconfigured state. This hardware initialization may include enabling the controller clock, initializing the controller registers, clearing historical interrupt and error states, configuring the command sending channel and response receiving channel, etc. To accommodate the low-speed, stable communication requirements of the device identification phase, the host controller can be configured with conservative parameters for the initialization phase, such as configuring the initialization clock to 400kHz, configuring the bus width to 1 bit, and maintaining power states, command sending parameters, and data receiving parameters that match those of the device identification phase. Through this process, the firmware can ensure that the host controller is in a stable, controllable initial operating state that meets the initialization timing requirements before subsequently sending the GO_IDLE_STATE and SEND_OP_COND commands to the embedded storage device.

[0021] In step S102, the host controller sends an idle state command defined by the protocol to the embedded storage device, causing the embedded storage device to enter an idle state.

[0022] Among them, the embedded storage device is an embedded multimedia memory. The idle state command is a protocol command used to put the embedded multimedia memory into an idle state and trigger the internal reset process. The operation condition command is a protocol command used to make the embedded multimedia memory return the operation condition register information. The operation condition information includes host supported voltage range confirmation information and busy state indication. The firmware determines whether the embedded multimedia memory has completed internal power-on initialization by whether the busy state indication is set.

[0023] For example, the embedded storage device can be an eMMC, or embedded Multi Media Card. After the firmware completes the basic configuration of the host controller, the host controller sends a CMD0 command to the eMMC. CMD0 corresponds to GO_IDLE_STATE, which resets the eMMC from its power-on indeterminate state to the Idle state, establishing the initial state basis for subsequent device identification procedures. Through this command, the eMMC enters the protocol-defined idle state, the internal reset procedure is triggered, and the device begins preparing for subsequent operational condition queries and identification responses.

[0024] After the eMMC enters the Idle state, the subsequent operation conditions will be queried via the CMD1 command. CMD1 corresponds to SEND_OP_COND, which is used to make the eMMC return OCR register information, i.e., the Operating Conditions Register. The OCR register information contains host supported voltage range confirmation information and the Busy bit. The Busy bit is usually located at bit 31 of the OCR register and is used to indicate whether the eMMC's internal power-on initialization is complete. When the Busy bit is not set, it means that the eMMC is still in the process of power-on initialization or reset preparation, and the host controller needs to continue to wait and perform subsequent polling. When the Busy bit is set, it means that the eMMC has completed internal initialization and can enter the subsequent device identification stage. Therefore, this step uses CMD0 to return the eMMC to the Idle state, providing a protocol basis for subsequent initialization status judgment based on CMD1 and the OCR Busy bit.

[0025] In step S103, the host controller sends the operation condition command defined by the protocol to the embedded storage device according to the preset polling rules, receives the operation condition information returned by the embedded storage device, and determines whether the embedded storage device has completed internal initialization based on the busy status indication in the operation condition information.

[0026] The preset polling rules include: continuously sending operation condition commands after establishing the polling timer start point; determining whether the command response is successful after each operation condition command is sent; parsing the operation condition information when the command response is successful; continuing to send operation condition commands when the busy status indicator is not set and the preset timeout window is not met; and determining that the operation condition command polling has timed out when the command response is abnormal and the busy status indicator is not set for a period of time, resulting in the preset timeout window being met.

[0027] As an example, after the embedded storage device enters the Idle state, the host controller establishes a polling timer start point and cyclically sends the CMD1 command according to the initialization process. CMD1 corresponds to SEND_OP_COND and is used to query the operating condition status of the eMMC. When sending CMD1, the host controller can carry the voltage range parameter supported by the host. When the embedded storage device can respond, it returns OCR register information, which stands for Operating Conditions Register. After receiving the OCR register information, the firmware parses the Busy bit, which can be bit 31 of the OCR register, to indicate whether the internal power-on initialization of the eMMC is complete.

[0028] After each CMD1 transmission, the firmware first checks if the command response was successful. If the command response is successful, it parses the returned OCR register information and further checks if the Busy bit is set. If the Busy bit is set, it indicates that the eMMC internal initialization is complete, and the current polling has obtained a valid device ready result. If the Busy bit is not set, it indicates that the eMMC is still in the process of reset or power-on initialization, and may not have completed internal state organization. The firmware continues to check if the current polling time has exceeded the preset timeout window. If the preset timeout window has not been exceeded, the host controller continues to send CMD1 and waits for the next OCR return result.

[0029] If CMD1 responds abnormally, or if the Busy bit remains unset within the preset timeout window, the firmware can determine that CMD1 polling has not yielded a device readiness result, thus triggering an operation condition command polling timeout. The preset timeout window can be determined based on eMMC initialization timing requirements, such as the waiting time limit used for device identification mode in the JEDEC standard. This polling rule allows the firmware to distinguish between normal delayed eMMC initialization and abnormal timeout states, preventing premature exit from the initialization process when the Busy bit is not yet set but is still within the allowable waiting range.

[0030] In step S104, when the busy state indicator indicates that the embedded storage device has completed internal initialization, the firmware enters the device identification stage.

[0031] The subsequent device identification stage includes at least one of the following: reading device identification information, assigning device address, configuring transmission bus, adjusting working clock, and completing block device registration.

[0032] Once the firmware parses the operation condition information and determines that the Busy bit is set, it can be concluded that the internal power-on initialization of the embedded storage device has been completed, and the device has transitioned from the waiting-for-reset-complete state to the recognizable state. For eMMC, this result indicates that the SEND_OP_COND polling corresponding to CMD1 has obtained the eMMC Ready result. The host controller does not need to trigger a soft reset retry, nor does it need to continue executing CMD1 polling. It can proceed to the subsequent device recognition stage according to the standard initialization process.

[0033] The device identification phase can include processes such as reading device identification information, allocating device addresses, configuring the transmission bus, adjusting the operating clock, and completing block device registration. For example, in the eMMC initialization process, the firmware can continue to read device identification information such as the CID, and perform RCA allocation, bus width configuration, and operating clock adjustment based on the device identification results, enabling the embedded storage device to gradually transition from the initialization identification state to a block device state accessible to the system. Since this step is only executed when Busybit indicates that the device has completed internal initialization, it ensures that subsequent operations such as reading the CID, allocating RCA, configuring the bus width, and adjusting the clock are based on the device being ready, avoiding command failures or initialization anomalies caused by prematurely entering the identification process before the device's internal reset is complete.

[0034] In step S105, when the busy status indicator continues to indicate that the embedded storage device has not completed internal initialization within the preset timeout window, it is determined that the operation condition command polling timeout has occurred, and it is determined whether the number of soft reset retries executed has reached the preset maximum number of retries.

[0035] The operation condition command polling timeout occurs during the initialization phase of the embedded storage device after power-off and power-back following the completion of a preset data write. When the firmware detects that the busy state indicator remains unset, it determines that the embedded storage device is in a delayed reset state due to incomplete internal background processing and triggers a soft reset retry. The preset maximum number of retries is determined by at least one of the firmware configuration items, platform configuration database, compilation configuration, device description table, and startup strategy. The firmware does not trigger a soft reset retry when the operation condition command polling is successful; it only enables a soft reset retry when the operation condition command polling times out, and returns a device error status to the upper layer only after the number of executed soft reset retries has reached the preset maximum number of retries.

[0036] Specifically, the firmware continuously monitors the Busy bit in the OCR register during the SEND_OP_COND polling process corresponding to CMD1. If the Busy bit remains unset within the preset timeout window, it indicates that the eMMC has not completed its internal power-on initialization within the allowed waiting time, and the firmware can determine this state as an operation condition command polling timeout. This timeout does not necessarily indicate a permanent failure of the eMMC; it may also be a temporary unavailability state caused by an extended internal device reset time. Therefore, before directly returning a Device Error to the upper layer, the firmware first enters the soft reset retry count determination process.

[0037] In a typical scenario, the eMMC experiences a power outage after writing a large amount of data and then quickly re-energizes to enter the initialization phase. Because the writing process may cause the device temperature to rise, and background processes such as Garbage Collection or Wear Leveling may still be incomplete within the eMMC, the time required for internal reset and state preparation after power-on may be longer than the normal waiting window. In this situation, the Busy bit returned by the OCR during CMD1 polling may remain unset. Based on this, the firmware can determine that the eMMC is in a delayed reset state caused by incomplete internal background processing and use this state as an abnormal condition to trigger a soft reset retry.

[0038] Before triggering a soft reset retry, the firmware needs to read or determine the current number of retries already performed and compare it with the preset maximum number of retries. The preset maximum number of retries can be derived from firmware configuration items, platform configuration database, compilation configuration, device description table, or boot strategy, or it can be set according to the device platform's requirements for boot speed and reliability. For example, a smaller number of retries can be set for platforms sensitive to boot speed, while a larger number can be set for scenarios that prioritize boot reliability, such as servers and industrial control equipment. This limitation allows the firmware to provide a recovery opportunity when the eMMC is in a temporary delayed reset state, while avoiding indefinite waiting when the eMMC is actually damaged or unresponsive for an extended period.

[0039] Soft reset retries are enabled only after CMD1 polling times out. If the Busy bit is already set during CMD1 polling, indicating eMMC Ready, the firmware directly enters the device identification stage without triggering a soft reset retries, thus not increasing the time consumed by the normal startup path. Only when CMD1 responds abnormally or the Busy bit remains unset and the preset timeout window is reached will the firmware determine whether to allow further retries. If the number of soft reset retries already executed has not reached the preset maximum number of retries, the subsequent soft reset recovery process will begin. If the number of soft reset retries already executed has reached the preset maximum number of retries, it can be confirmed that initialization cannot be completed through limited recovery, and the firmware will then return the device error status to the upper layer, thus balancing abnormal recovery capabilities and initialization exit efficiency.

[0040] In step S106, when the number of soft reset retries performed has not reached the preset maximum number of retries, the number of soft reset retries performed is updated, a soft reset is performed on the host controller, the host controller is reconfigured to the initial working state, an idle state command is sent to the embedded storage device again, and after a preset waiting condition is met, the polling of the operation condition command is returned.

[0041] The soft reset of the host controller includes: performing software reset processing on the host controller's command sending circuit, data receiving circuit, control state machine and error status register, clearing the command error status, data error status and interrupt pending status generated by the host controller in the previous round of initialization polling, so that the host controller can recover from the abnormal polling state to a controllable state that can re-initiate the initialization command; the soft reset does not perform a power-off reset on the power supply circuit of the embedded storage device.

[0042] Furthermore, reconfiguring the host controller to its initial operating state includes: reconfiguring the host controller to the conservative parameter set corresponding to the device identification phase. The conservative parameter set includes initialization clock parameters, initial bus transmission parameters, command sending parameters, data receiving parameters, and controller power status parameters, so that the host controller can regain stable operating conditions to send idle state commands and operating condition commands after performing a soft reset.

[0043] The preset waiting conditions include: after sending an idle state command to the embedded storage device again, waiting until the preset delay policy is met. The preset delay policy adopts at least one of the following: a fixed waiting policy, a waiting policy that increases with the number of retries, and an adaptive waiting policy. The adaptive waiting policy determines the waiting time based on at least one of the following: the time taken for the previous round of polling, the current retry order, the device operating temperature, historical initialization failure records, and the platform startup reliability policy, so as to provide the embedded storage device with a recovery window to complete the background processing of internal reset, garbage collection, and wear leveling.

[0044] As an example, after confirming that the number of soft reset retries performed has not reached the preset maximum number of retries, the firmware first updates the retry count, for example, by incrementing RetryCount by one, so as to determine whether to allow the recovery process to continue. This process ensures that soft reset retries are performed within a limited range, avoiding repeated pauses in the initialization phase when the embedded storage device remains unresponsive or experiences an unrecoverable failure.

[0045] Subsequently, the firmware performs a soft reset on the host controller. This soft reset is performed on the host controller side and can correspond to the software reset processing of SDHCI or eMMC Host Controller. It is primarily used to restore the controller's own command sending, response receiving, and state control capabilities. Specifically, it can perform a software reset on the command sending circuit, data receiving circuit, control state machine, and error status register, clearing command error states, data error states, interrupt pending states, and internal abnormal states that may have occurred during the previous CMD1 polling process. This allows the host controller to recover from an abnormal polling state to a controllable state capable of re-initiating initialization commands. This soft reset does not perform a power-off reset on the embedded storage device's power supply circuit, nor does it forcibly reset the eMMC through a power-on process. This avoids introducing additional power-on timing issues and maintains the speed of the recovery process and the controllability of the firmware side.

[0046] After the host controller completes a soft reset, the firmware reconfigures the host controller to the initial operating state required for the device identification phase. This reconfiguration may include restoring initialization clock parameters, initial bus transmission parameters, command transmission parameters, data reception parameters, and controller power state parameters. In eMMC initialization scenarios, the host controller can be reconfigured to conservative parameters for the initialization phase, such as a 400kHz clock and a 1-bit bus width, restoring the basic conditions for stable transmission of CMD0 and CMD1. This configuration avoids the host controller being in a state of incomplete register states, mismatched bus parameters, or unrestored command channels after a soft reset, thus ensuring that subsequent initialization commands can be re-initiated under the low-speed, stable conditions of the device identification phase.

[0047] Afterwards, the host controller sends an idle state command to the embedded storage device again. For eMMC, this idle state command can be CMD0, i.e., GO_IDLE_STATE, used to put the eMMC back into the Idle state and trigger the internal reset procedure again. This process does not involve powering off and then powering on the eMMC, but rather, at the protocol level, it returns the eMMC to a state suitable for restarting the identification process, thus providing the starting conditions for subsequent execution of CMD1 polling.

[0048] After resending CMD0, the firmware waits until a preset waiting condition is met. This wait provides the eMMC with an internal reset and state recovery window, allowing it time to complete background processing such as internal reset, Garbage Collection, and WearLeveling. The preset delay strategy can be a fixed wait strategy or a wait strategy that increases with the number of retries, such as waiting a short time on the first retry and appropriately extending the wait time in subsequent retries. The preset delay strategy can also be an adaptive wait strategy, determining the wait time based on at least one of the following: the time taken for the previous round of CMD1 polling, the current retry order, the device operating temperature, historical initialization failure records, and the platform startup reliability strategy. For eMMCs with uncertain internal reset times or those significantly affected by temperature and background operations, this wait can reduce the probability that the Busybit is still not set when polling again.

[0049] After the preset waiting conditions are met, the firmware returns to polling the operation condition command, that is, the host controller resends the SEND_OP_COND command corresponding to CMD1, receives the OCR register information, and again determines whether the eMMC has completed internal initialization based on the Busy bit in the OCR. Through continuous processing of updating the retry count, resetting the host controller, restoring conservative parameters, sending CMD0, waiting for the delay, and re-executing the CMD1 polling, the firmware can transform the CMD1 timeout exception, which originally returned DeviceError directly, into a recoverable initialization exception, improving the boot success rate of embedded storage devices in scenarios such as power failure and restart after high load writes, high temperature, or incomplete internal background processing.

[0050] In step S107, when the number of soft reset retries reached the preset maximum number of retries, the firmware returned a device error status to the upper layer and ended the initialization of the embedded storage device.

[0051] The firmware records at least one of the following each time a soft reset retry is triggered: retry sequence, timeout reason, polling time, operation condition information, time stamp, and recovery result. It also records the information through at least one of the following outputs: serial port log, non-volatile memory log, and debug log, in order to locate initialization compatibility issues of the embedded storage device.

[0052] Specifically, after the operation condition command polling times out, if the firmware determines that the number of soft reset retries already executed has reached the preset maximum number of retries, it will not continue the soft reset retry process. Instead, it will return a device error status to the upper layer and end the initialization of the embedded storage device. For eMMC initialization scenarios, this device error status can correspond to Device Error or EFI_DEVICE_ERROR, indicating that within the allowed number of retries, the firmware has still not obtained the result of setting the Busy bit in the OCR through the SEND_OP_COND polling corresponding to CMD1, and the embedded storage device has failed to enter the Ready state.

[0053] This process defines the exit boundary of the soft reset retry procedure. In other words, the firmware does not immediately terminate initialization upon the first CMD1 polling timeout. Instead, it reports an initialization failure to the upper layer only after a limited number of Host controller soft resets, CMD0 re-idleization, preset waits, and CMD1 re-pollings, if it still cannot confirm that the embedded storage device has completed internal initialization. This approach provides a recovery opportunity for temporary delayed reset states while avoiding prolonged blocking of the boot process in cases of actual embedded storage device failure, prolonged unresponsiveness, or inability to complete internal power-on initialization.

[0054] Each time a soft reset retry is triggered, the firmware can synchronously record information related to the recovery from this anomaly. The recorded information may include the retry order corresponding to RetryCount, the timeout reason (such as CMD1 polling timeout or command response anomaly), the polling time calculated from TimerStart, the OCR register return value or its Busy bit status, the current time indicator, and the recovery result after this retry. The recovery result may include subsequent CMD1 polling success, continued timeout, or failure to exit after reaching MaxRetry. By saving this information, a basis for analyzing eMMC initialization compatibility issues can be provided after device startup failure or recurrence of probabilistic anomalies.

[0055] Information can be recorded through at least one of the following outputs: serial port log, non-volatile memory log, and debug log. For example, during the debugging phase, the number of retries, CMD1 timeout duration, and OCR status can be printed via serial port, making it easier for field engineers to determine whether the soft reset retry mechanism has been triggered. In scenarios requiring long-term tracking, key anomaly information can also be written to the non-volatile memory log for subsequent statistical analysis of initialization failure characteristics under different eMMC chips, different temperature environments, or different boot strategies. Through this logging method, the firmware can not only explicitly exit the initialization process when the maximum number of retries is reached, but also provide traceable data for subsequent troubleshooting of device-specific differences, background GC, or wear leveling-related delayed reset issues.

[0056] In one embodiment, the firmware includes basic input / output system firmware, unified extensible firmware interface firmware, and boot firmware developed based on the unified extensible firmware interface framework; the electronic device includes one of a server, an embedded terminal, an industrial control device, and a computer; when adapting to a storage device based on the Secure Digital Input / Output Protocol (SDIP), the method replaces the operating condition commands with application operating condition commands in the SIP used to query operating conditions and busy status, and maintains the same fault-tolerant process consisting of idle status commands, host controller soft reset, reconfiguration, and preset waiting conditions.

[0057] In this implementation, the firmware can run in different types of boot environments, such as BIOS firmware, UEFI firmware, or boot firmware developed based on the UEFI framework. The initialization driver corresponding to the host controller can complete the identification and registration of the embedded storage device before the operating system loads. The electronic device can be a server, embedded terminal, industrial control equipment, or computer, etc., equipped with embedded storage media. All of these platforms rely on the firmware to complete the storage device initialization during power-on or restart. Therefore, when the storage device experiences initialization response delays due to individual differences, temperature conditions, or incomplete internal background processing, the same soft reset retry process can be used to improve boot reliability.

[0058] When adapting to eMMC, the operation condition command can be CMD1, i.e., SEND_OP_COND. The firmware determines whether the device is ready based on the Busy bit in the OCR register. When adapting to storage devices based on the SDIO protocol, the operation condition command can be replaced with the application operation condition command used in that protocol to query operating conditions and busy status, such as ACMD41, i.e., SD_SEND_OP_COND. The busy status bit in the returned information is used to determine whether the device has completed internal initialization. This replacement only changes the protocol command used to query operating conditions and busy status, and does not change the basic process of exception recovery.

[0059] In other words, during the initialization of SDIO protocol storage devices, the host controller can still send an idle state command to put the storage device into the Idle state. When the application operation condition command polling times out or the busy state fails to indicate that the device is ready, the firmware can still perform a soft reset on the host controller, reconfigure it to the conservative parameters corresponding to the device identification stage, send the idle state command again, and re-execute the application operation condition command polling after the preset waiting conditions are met. In this way, the soft reset retry process can be extended from the eMMC initialization scenario to the initialization scenario of storage devices with similar working condition query and busy state judgment mechanisms, while maintaining the consistency of firmware-side fault tolerance processing.

[0060] As described in the above embodiments, this invention improves the handling of operation condition command polling timeout during firmware initialization of embedded storage devices from direct error reporting and exit to a limited number of soft reset retry processes. This allows the host controller to clear the erroneous state generated in the previous round of initialization after abnormal polling and restore it to the initial working state suitable for the device identification stage. Furthermore, the idle state command and waiting conditions provide a new internal reset and state recovery window for the storage device. Therefore, when the storage device temporarily fails to complete initialization due to internal background processing, temperature conditions, or individual device differences, the firmware can automatically attempt recovery, reducing the probability of startup failure. Simultaneously, this invention is limited to triggering only when polling timeout occurs; it does not add an extra startup process when initialization is successful normally, and it does not require changes to the storage device's power supply circuit or the addition of hardware components. It has the advantages of low implementation cost, good compatibility, transparency to users, and ease of firmware upgrade and deployment. By setting a maximum number of retries, it also avoids the firmware remaining in the initialization stage for an extended period when the storage device experiences a real failure, thus balancing startup reliability and abnormal exit efficiency. Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0061] It should be understood that this disclosure is not limited to the precise process described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A soft reset retry method, characterized by, The method, applied to an electronic device comprising firmware, a host controller, and an embedded storage device, includes, When the firmware initiates the initialization of the embedded storage device, it performs hardware initialization on the host controller and configures the host controller to an initial operating state suitable for the device identification phase. The host controller sends a protocol-defined idle state command to the embedded storage device, causing the embedded storage device to enter an idle state; The host controller sends a protocol-defined operation condition command to the embedded storage device according to a preset polling rule, receives the operation condition information returned by the embedded storage device, and determines whether the embedded storage device has completed internal initialization based on the busy status indication in the operation condition information. When the busy status indicator indicates that the embedded storage device has completed internal initialization, the firmware enters the device identification phase. When the busy status indicator continues to indicate that the embedded storage device has not completed internal initialization within the preset timeout window, it is determined that the operation condition command polling timeout has occurred, and it is determined whether the number of soft reset retries executed has reached the preset maximum number of retries. When the number of soft reset retries performed has not reached the preset maximum number of retries, the number of soft reset retries performed is updated, a soft reset is performed on the host controller, the host controller is reconfigured to the initial working state, the idle state command is sent to the embedded storage device again, and after a preset waiting condition is met, the polling for executing the operation condition command is returned. When the number of soft reset retries reached the preset maximum number of retries, the firmware returned a device error status to the upper layer and ended the initialization of the embedded storage device.

2. The soft reset retry method of claim 1, wherein, The embedded storage device is an embedded multimedia memory. The idle state command is a protocol command used to put the embedded multimedia memory into an idle state and trigger an internal reset process. The operation condition command is a protocol command used to make the embedded multimedia memory return operation condition register information. The operation condition information includes host supported voltage range confirmation information and the busy state indicator. The firmware determines whether the embedded multimedia memory has completed internal power-on initialization by whether the busy state indicator is set.

3. The soft reset retry method according to claim 1, characterized in that, The preset polling rules include: After establishing the polling timing start point, continuously send the operation condition commands; After each sending of the operation condition command, determine whether the command response was successful. The operation condition information is parsed when the command response is successful. Continue sending the operation condition command when the busy status indicator is not set and the preset timeout window is not met; When the command response is abnormal and the busy status indicator remains unset, resulting in the preset timeout window being met, the operation condition command polling timeout is determined to have occurred.

4. The soft reset retry method according to claim 1, characterized in that, Performing a soft reset on the host controller includes: A software reset is performed on the command sending circuit, data receiving circuit, control state machine, and error status register of the host controller to clear the command error status, data error status, and interrupt pending status generated by the host controller in the previous round of initialization polling, so that the host controller recovers from the abnormal polling state to a controllable state that can re-initiate the initialization command; wherein, the software reset does not perform a power-off reset on the power supply circuit of the embedded storage device.

5. The soft reset retry method according to claim 1, characterized in that, Reconfiguring the host controller to the initial operating state includes: The host controller is reconfigured to the conservative parameter set corresponding to the device identification phase. The conservative parameter set includes initialization clock parameters, initial bus transmission parameters, command sending parameters, data receiving parameters, and controller power status parameters, so that the host controller can regain stable operating conditions to send the idle state command and the operating condition command after performing the soft reset.

6. The soft reset retry method according to claim 1, characterized in that, The preset waiting conditions include: After sending the idle state command to the embedded storage device again, the device waits until a preset delay strategy is met. The preset delay strategy adopts at least one of a fixed waiting strategy, a waiting strategy that increases with the number of retries, and an adaptive waiting strategy. The adaptive waiting strategy determines the waiting time based on at least one of the following: the polling time of the previous round, the current retry order, the device operating temperature, historical initialization failure records, and the platform startup reliability strategy, so as to provide the embedded storage device with a recovery window to complete the background processing of internal reset, garbage collection, and wear leveling.

7. The soft reset retry method according to claim 1, characterized in that, The preset maximum number of retries is determined by at least one of the firmware configuration items, platform configuration database, compilation configuration, device description table, and startup strategy; the firmware does not trigger a soft reset retry when the operation condition command polling is successful, but enables a soft reset retry when the operation condition command polling times out, and only returns the device error status to the upper layer after the number of executed soft reset retries reaches the preset maximum number of retries.

8. The soft reset retry method according to claim 1, characterized in that, The subsequent device identification phase includes at least one of reading device identification information, allocating device address, configuring transmission bus, adjusting working clock, and completing block device registration; the firmware records at least one of the following each time a soft reset retry is triggered: retry sequence, timeout reason, polling time, operation condition information, time stamp, and recovery result, and records the information through at least one of serial port log, non-volatile memory log, and debug log to locate the initialization compatibility problem of the embedded storage device.

9. The soft reset retry method according to claim 1, characterized in that, The firmware includes basic input / output system firmware, unified extensible firmware interface firmware, and boot firmware developed based on the unified extensible firmware interface framework; the electronic device includes one of a server, embedded terminal, industrial control equipment, and computer; when adapting to a storage device based on the Secure Digital Input / Output Protocol (SDIP), the method replaces the operation condition command with the application operation condition command in the SIP used to query working conditions and busy status, and maintains the same fault-tolerant process consisting of the idle status command, the host controller soft reset, the reconfiguration, and the preset waiting conditions.

10. The soft reset retry method according to claim 1, characterized in that, The operation condition command polling timeout occurs during the initialization phase of the embedded storage device after power-off and power-on following the completion of a preset data write amount. When the firmware detects that the busy state indicator is not set, it determines that the embedded storage device is in a delayed reset state caused by incomplete internal background processing and triggers the soft reset retry.

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