An improved single event upset hardened d flip flop and method of implementation thereof

Abstract

The application discloses a kind of anti-single event upset DICE flip-flop reinforcement structures based on clocked gate. In view of the defect that the transmission gate in the conventional DICE flip-flop easily leads to the cross-loop propagation of single particle interference signal at the clock edge, the first stage transmission gate is optimized as an inverter combined with a clocked gate structure, which is composed of two series PMOS tubes (gates connected with clock CK and inverted signal respectively) and two series NMOS tubes (gates connected with clock CKN and inverted signal respectively). The overall structure includes a redundant clock input part, a data input control part, a main DICE structure latch loop, a main-slave loop connection control part, a slave DICE structure latch loop and an output driving part. This design can effectively block the conduction of interference signals between the double interlocking loops, while ensuring that the signal phase remains unchanged, greatly improving the radiation tolerance of the flip-flop. It is suitable for high-reliability integrated circuits in aerospace, nuclear power and other fields, with low cost and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology, specifically relating to a single-event flip-flop D trigger based on a clock gate and DICE structure. Background Technology

[0002] In the space radiation environment, high-energy particles (such as protons and heavy ions) can cause single-event effects (SEE), among which single-event upsets (SEUs) are one of the main threats to the reliability of integrated circuits. When an SEU occurs, a particle impacts a sensitive node, generating a charge that causes the logic state to flip, particularly in sequential circuits such as D flip-flops, easily leading to functional failure. Traditional D flip-flops employ a master-slave structure, consisting of a master latch and a slave latch connected in series. To improve SEU resistance, dual-interlocked cells (DICEs) are widely used. DICEs form dual-loop redundancy through four interlocked inverters; when a single node is disturbed, it can self-recover to the correct state through the interlocking mechanism.

[0003] However, traditional DICE structures have limitations: at the rising / falling edge of the clock, if the signal encounters a Single Event Detection (SEU) after the Transmission Gate, and the Transmission Gate is at its closing critical moment, the interference signal will be locked to the first latch; since both loops use transmission gates, the erroneous signal can propagate to the other loop through the second transmission gate, causing both loops to flip and ultimately outputting an error. Especially when the flip-flop operates at a high-frequency clock, the probability of a single event interference coinciding with the clock edge arrival time will be greatly increased, significantly reducing the SEU immunity of ordinary DICE structures.

[0004] Existing technologies include design methods that strengthen master-slave latches through dual-mode redundancy and separate pull-up PMOS and pull-down NMOS in CMOS circuits to improve SEU resistance. However, these methods still use transmission gates in the feedback loop, resulting in low noise margins and weak feedback capabilities, making them prone to failure when the circuit operates under high-frequency clocks and high LET (Linear Energy Transfer) particles. Furthermore, some technologies emphasize layout-level hardening, such as increasing the distance between sensitive nodes (master node > 11 μm, slave node > 5 μm), combined with circuit redundancy, to optimize area and power consumption. However, these methods still rely on transmission gates and ignore the propagation path of clock along critical interference.

[0005] The shortcomings of the existing technology are: (1) the transmission gate structure has low noise tolerance and is easily affected by high LET particles; (2) the interference conduction between the two loops is not effectively isolated, resulting in a high overall flip probability when the circuit is operating at a high frequency clock; (3) although there are auxiliary measures such as delay filtering, the protection against transient interference under dynamic clock is limited. The present invention aims to solve the above problems and provide a new type of clock gate optimization structure to enhance the anti-SEU performance of DICE flip-flops while maintaining low overhead. Summary of the Invention

[0006] The purpose of this invention is to provide a robust DICE trigger structure based on a clock gate, which is designed to resist single-event upsets. By optimizing the first-stage transmission gate to be a combination of an inverter and a clock gate, interference signals are prevented from propagating across the loop, thereby improving SEU resistance.

[0007] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0008] An improved D flip-flop hardened to resist single-event upsets includes: a data input module, a master latch loop, a master-slave connection control module, a slave latch loop, and a data output module connected in sequence, and also includes a redundant clock input module connected to the data input module, the master latch loop, the master-slave connection control module, and the slave latch loop respectively.

[0009] The data input module consists of two parallel, identical improved control structures, which are composed of an inverter and a clock gate connected in series.

[0010] The clock gate consists of two PMOS transistors connected in series and two NMOS transistors connected in series. The gates of the two PMOS transistors are respectively connected to the output signal CK of the redundant clock input module and the output signal of the inverter of the previous stage. The gates of the two NMOS transistors are respectively connected to the output signal CKN of the redundant clock input module and the output signal of the inverter of the previous stage.

[0011] The redundant clock input module consists of two parallel clock branches with identical structures. Each branch is composed of two inverters connected in series. The first inverter outputs signal CK, and the second inverter outputs signal CKN.

[0012] The data output module consists of a driver BUFFER B1, whose input is connected to two signals output from the latch loop, and whose output is connected to the output data terminal Q.

[0013] An improved method for implementing a single-event upset-resistant hardened D trigger is as follows:

[0014] The inverter in the data input module keeps the phase of the input signal D unchanged and is connected in series with the clock gate to block the propagation of erroneous signals caused by single-event interference across the loop;

[0015] In the initial state of the master-slave latch loop, if the logic level stored in the first input node and the second input node of the two paths is 1, the logic level stored in the first output node and the second output node is 0. When the logic level of the input or output storage node is flipped by a single event disturbance, the cross-coupled feedback path in the master-slave latch loop will continuously apply a recovery drive to the flipped node, so that the circuit returns to its original state.

[0016] The output signals CK1, CK2, CKN1, and CKN2 of the redundant clock input module are used as clock control signals for the transmission gate in the master-slave latch loop and the clock gate in the improved control structure, respectively, to improve the circuit's resistance to single-event interference.

[0017] The present invention has the following beneficial effects and advantages:

[0018] 1. Enhanced isolation: The clock gate structure blocks the propagation path of erroneous signals, reducing the probability of the circuit flipping due to single-event effects when operating at high-frequency clock speeds.

[0019] 2. Low overhead: Limited increase in transistor count, resulting in a small area overhead percentage.

[0020] 3. Compatibility: Applicable to various CMOS processes without the need for special components; it is also applicable to various types of trigger structures, making it a universal DICE structure improvement method.

[0021] 4. Comprehensive protection: Effective against both SEU and SET. Attached Figure Description

[0022] Figure 1 The circuit diagram of the improved ordinary DICE structure trigger.

[0023] Figure 2 The figure shows the simulation results of a standard DICE trigger when a single-event disturbance is applied to a specific node of the circuit.

[0024] Figure 3 The circuit diagram for the improved control structure.

[0025] Figure 4 The structure diagram of the improved DICE structure trigger.

[0026] Figure 5 The simulation results of the improved DICE structure trigger under single-event disturbance are shown in the figure.

[0027] Figure 6 This is a schematic diagram of the structure of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0029] likeFigure 6 As shown, an improved D flip-flop hardened to resist single-event upsets includes a data input section, a redundant clock input section, a master latch loop, a master-slave connection control section, a slave latch loop, and a data output section.

[0030] Compared to a standard DICE trigger, the first-stage transmission gate in the data input section is replaced with a control structure consisting of an inverter and a clock gate connected in series.

[0031] The clock gate consists of two PMOS transistors connected in series and two NMOS transistors connected in series. The gates of the two PMOS transistors are respectively connected to the output signal CK of the redundant clock module and the output signal of the inverter of the previous stage. The gates of the two NMOS transistors are respectively connected to the output signal CKN of the redundant clock module and the output signal of the inverter of the previous stage.

[0032] The inverter is used to keep the signal phase unchanged and is connected in series with the clock gate to block the propagation of erroneous signals caused by single-event interference across the loop.

[0033] A redundant clock design is adopted, which optimizes the single clock output into a dual clock output with output signals CK1, CK2, CKN1, and CKN2. These output signals are used as clock control signals for the transmission gates in the two cross-coupled paths, namely the DICE loop and the clock gates in the improved control structure, respectively, to further enhance the structure's resistance to single-event interference.

[0034] The data input control section consists of data input D and an improved control structure. Specifically, the data signal D is divided into two independent paths that are connected to the gates of the inverters in the improved control structures C0 and C1, respectively.

[0035] The main latch loop structure consists of two paths: ①. The output of the C0 control structure is connected to the gate of P2, the gate of N3, and the transmission gate G3. The source of P2 is connected to the power supply. The drains of P2 and N2 are connected and their outputs are connected to the gates of P1 and N4. The source of N4 is connected to ground. The source of P1 is connected to the power supply. The drains of P1 and N1 are connected and their outputs are connected to the transmission gate G2. The source of N1 is connected to ground. The clock control signal of G2 is connected to the output signals CK2 and CKN2 of the redundant clock. ②. The output of the C1 control structure is connected to the gate of N2, the gate of P3, and the transmission gate G2. The source of P3 is connected to the power supply. The drains of P3 and N3 are connected and their outputs are connected to the drains of N1 and P4. The source of P4 is connected to the power supply. The drains of P4 and N4 are connected and their outputs are connected to the transmission gate G3. The clock control signal of G3 is connected to the output signals CK1 and CKN1 of the redundant clock.

[0036] The master-slave loop connection control section consists of two transmission gates, G4 and G5. The clock control signal of G4 is connected to the output signals CK1 and CKN1 of the redundant clock, and the input part of G4 is connected to the drain outputs of P2 and N2 in the master latch loop. The clock control signal of G5 is connected to the output signals CK2 and CKN2 of the redundant clock, and the input part of G5 is connected to the drain outputs of P3 and N3 in the master latch loop.

[0037] The latching loop structure consists of two paths: ①. The output of transmission gate G4 is connected to the gates of P6, N7, and transmission gate G7. The source of P6 is connected to the power supply. The drains of P6 and N6 are connected and their outputs are connected to the gates of P5 and N8. The source of N8 is connected to ground. The source of P5 is connected to the power supply. The drains of P5 and N5 are connected and their outputs are connected to transmission gate G6. The source of N5 is connected to ground. The clock control signal of G6 is connected to the output signals CK2 and CKN2 of the redundant clock. ②. The output of transmission gate G5 is connected to the gates of N6, P7, and transmission gate G6. The source of P7 is connected to the power supply. The drains of P7 and N7 are connected and their outputs are connected to the drains of N5 and P8. The source of P8 is connected to the power supply. The drains of P8 and N8 are connected and their outputs are connected to transmission gate G7. The clock control signal of G7 is connected to the output signals CK1 and CKN1 of the redundant clock.

[0038] The output drive section consists of a drive buffer B1. The input of B1 is connected to two signals output from the latch loop, and the output of B1 is connected to the output data terminal Q.

[0039] Specifically, the core improvements to this structure are as follows:

[0040] First-level optimization: The transmission gate in the data input control section is replaced with an inverter and a clock-controlled gate. The inverter receives the data input signal and ensures phase correction; the clock-controlled gate serves as the subsequent transmission unit, blocking the reverse transmission of the subsequent stage error signal in the event of a single-event interference.

[0041] Clock gate design: The upper branch consists of two series-connected PMOS transistors, with the gate of the first PMOS transistor connected to the inverter output and the gate of the second PMOS transistor connected to the signal CK; the lower branch consists of two series-connected NMOS transistors, with the gate of the first NMOS transistor connected to CKN and the gate of the second NMOS transistor connected to the inverter output.

[0042] DICE loop integration: The master and slave latches adopt a standard DICE double interlock structure with four interlocked nodes. The master node stores the same logic, and the slave node stores the same logic. After the improvement, interference from the first loop cannot be transmitted to the second loop through the clock gate.

[0043] Phase preservation: The inverter ensures that the overall signal phase remains unchanged, avoiding timing problems introduced by additional inversion.

[0044] Performance improvements: This design prevents clock edge interference lock-in, and the SEU toggle rate is significantly reduced under high-frequency clock conditions, with latency increase of <10 ps and power consumption increase of <10%.

[0045] It is worth noting that only the first-stage transmission gate was improved here; the transmission gate at the master-slave latch loop connection was not replaced with the improved structure. This is because there is no directly connected interconnected loop between the inputs of the transmission gates at the connection points of the two paths. Therefore, in order to minimize the risk of single-event upsets while maintaining the original flip-flop structure, only the first-stage transmission gate was improved. Although replacing the transmission gate at the connection point with the improved structure could further improve the circuit's SEU resistance, it would increase area overhead, power consumption, and timing delay. A balance needs to be struck between these three factors based on the specific application scenario, requiring targeted improvements. This invention introduces a general improvement method and design concept.

[0046] Example

[0047] like Figure 1 The diagram shows a traditional flip-flop circuit and a flip-flop circuit after DICE hardening. The dual-loop transmission gate structure has potential interference paths. At the same time, due to the use of a single-path clock input structure, it cannot effectively avoid the risk of the clock signal receiving single-event interference.

[0048] like Figure 2 As shown, the potential risk principle of dual-loop transmission gates will be explained in detail with the simulation diagram. In the SPICE simulation, a single-event bombardment scenario is simulated, and the instantaneous current interference intensity is 30mA. Interference is applied to node M1 at 9.16us, and the timing of the single-event interference is controlled to overlap with the rising edge of the clock. At this time, transmission gate G0 is in a critically closed state. The signal line of node M1 originally transmits a level of 1, which becomes 0 after being affected by the single-event interference. If the driving capability of the data input signal D is not strong enough, since transmission gate G0 is not completely closed at this time, the erroneous level signal 0 after being affected by the interference will be transmitted to transmission gate G1 through transmission gate G0 along the signal input line D, thereby affecting the level signal of the second loop. At the next moment, transmission gates G0 and G1 are completely closed. At this time, the signals of both paths become erroneous level signals 0, and both loops flip simultaneously, causing the output Q result to be incorrect. The dashed part in the Q output curve in the figure is the correct level that should be output.

[0049] like Figure 3As shown, the improved control structure of transmission gates G0 and G1 consists of an inverter and a clock gate. The clock gate comprises two PMOS transistors and two NMOS transistors connected in series. The gates of the two PMOS transistors are connected to the output signal CK of the redundant clock module and the output signal of the inverter from the previous stage, respectively. The gates of the two NMOS transistors are connected to the output signal CKN of the redundant clock module and the output signal of the inverter from the previous stage, respectively. The inverter is used to maintain the signal phase and, in series with the clock gate, blocks single-event interference from propagating across the loop.

[0050] like Figure 4 As shown, this is a schematic diagram of the improved DICE structure hardened trigger circuit. Compared with the original structure, the transmission gates G0 and G1 in the circuit input section are replaced with the improved control structure, and the clock input section is improved to a dual-redundant structure, further enhancing the circuit's ability to resist single-event interference. The specific radiation protection working principle is as follows: Taking the main latching loop as an example, assuming that in the initial state, nodes M1 and M2 store logic level 1, while M3 and M4 store logic level 0. When node M1 is subjected to single-event interference, the logic level changes from 1 to 0, and P2 is turned on. Since the logic level of node M2 ​​remains unchanged at 1, node M3 will be in an indeterminate state (P2 and N2 are turned on simultaneously), while P3 and N3 will be turned off simultaneously, causing node M4 to be in a high-impedance state, and the stored logic level remains unchanged at 0. Since the logic level of M3 is uncertain, the state of transistor N4 is also in an indeterminate state, but P4 is turned on, so the logic level of node M1 will be pulled back to logic level 1, restoring the circuit to its original state. In this process, since the transmission gate connecting the two loops is replaced with an inverter plus clock gate structure, the error signal is blocked after the clock gate, so the error signal of node M1 cannot be transmitted to node M2 ​​at the clock edge, effectively improving the circuit's SEU resistance performance.

[0051] like Figure 5 As shown in the figure, the improved DCIE structure is simulated under single-event interference. The same simulation conditions and environment were used as before the improvement. At the same time (9.16us), a single-event interference was applied to node M1. It can be observed that the influence on node M1 did not affect the logic level value stored in node M2, and the final output Q result was correct.

Claims

1. An improved D trigger hardened to resist single-event upsets, characterized in that, include: The system consists of a data input module, a master latch loop, a master-slave connection control module, a slave latch loop, and a data output module connected in sequence. It also includes a redundant clock input module that is connected to the data input module, the master latch loop, the master-slave connection control module, and the slave latch loop, respectively.

2. The improved single-event upset-resistant D trigger according to claim 1, characterized in that, The data input module consists of two parallel, identical improved control structures, which are composed of an inverter and a clock gate connected in series.

3. An improved D trigger with single-event upset hardening according to claim 2, characterized in that, The clock gate consists of two PMOS transistors connected in series and two NMOS transistors connected in series. The gates of the two PMOS transistors are respectively connected to the output signal CK of the redundant clock input module and the output signal of the inverter of the previous stage. The gates of the two NMOS transistors are respectively connected to the output signal CKN of the redundant clock input module and the output signal of the inverter of the previous stage.

4. An improved D trigger with single-event upset hardening according to claim 1, characterized in that, The redundant clock input module consists of two parallel clock branches with identical structures. Each branch is composed of two inverters connected in series. The first inverter outputs signal CK, and the second inverter outputs signal CKN.

5. An improved D trigger with single-event upset hardening according to claim 1, characterized in that, The data output module consists of a driver BUFFER B1, whose input is connected to two signals output from the latch loop, and whose output is connected to the output data terminal Q.

6. The method for implementing an improved D trigger with single-event upset hardening according to claim 1, characterized in that, Specifically: The inverter in the data input module keeps the phase of the input signal D unchanged and is connected in series with the clock gate to block the propagation of erroneous signals caused by single-event interference across the loop; In the initial state of the master-slave latch loop, if the logic level stored in the first input node and the second input node of the two paths is 1, the logic level stored in the first output node and the second output node is 0. When the logic level of the input or output storage node is flipped by a single event disturbance, the cross-coupled feedback path in the master-slave latch loop will continuously apply a recovery drive to the flipped node, so that the circuit returns to its original state. The output signals CK1, CK2, CKN1, and CKN2 of the redundant clock input module are used as clock control signals for the transmission gate in the master-slave latch loop and the clock gate in the improved control structure, respectively, to improve the circuit's resistance to single-event interference.

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