A homogenous multi-channel thin film transistor and a method of manufacturing the same

Abstract

The application provides a homogenous multi-channel thin film transistor and a preparation method thereof. The preparation method comprises the following steps: preparing a gate electrode and a gate dielectric layer on a substrate in sequence; using an atomic layer deposition process to deposit at least two InGaO sub-channel layers on the gate dielectric layer in a direction away from the gate dielectric layer in sequence, and stacking the InGaO sub-channel layers to form a channel layer; during the deposition of each InGaO sub-channel layer, the same type of Ga precursor source and different types of In precursor source are used, or the same type of In precursor source and different types of Ga precursor source are used, so that each InGaO sub-channel layer has different carrier concentrations; during the deposition of each InGaO sub-channel layer, the sub-cycle periods are the same; performing a patterning treatment on the channel layer; preparing a source electrode and a drain electrode on the patterned channel layer to obtain the homogenous multi-channel thin film transistor. The application can simplify the preparation process, improve the interlayer interface quality, and does not need high-temperature annealing treatment.

Description

Technical Field

[0001] This invention relates to the field of oxide thin-film transistor technology, and in particular to a homogeneous multi-channel thin-film transistor and its fabrication method. Background Technology

[0002] In related technologies, a thin-film transistor with a dual-channel structure includes two channel layers with different carrier concentrations. The front channel uses a higher carrier concentration to act as an on-channel and transport carriers, achieving higher mobility. The back channel uses a relatively lower carrier concentration to regulate the conduction characteristics of the oxide layer and improve device stability. As a off-channel, the back channel reduces carrier scattering (ionized impurity scattering, interface scattering). The dual-channel structure also provides electrical modulation, enabling the thin-film transistor to exhibit excellent performance characteristics such as low off-state current and high mobility.

[0003] Dual-channel structures include heterostructures and homostructures. Compared to heterostructure dual-channel transistors (e.g., InGaO / ZnO), homostructure dual-channel structures are relatively simpler to fabricate and do not suffer from impurity atom diffusion issues. For example, In... 0.72 Ga 0.28 O / In 0.46 Ga 0.54 O.

[0004] However, methods for fabricating homogeneous dual-channel thin-film transistors include controlling oxygen partial pressure or oxygen content and sputtering power through magnetron sputtering, controlling the sub-cycle period of elements in the dual channels to achieve different elemental contents through atomic layer deposition, or using different oxidants to achieve different carrier concentrations and band structures in the front and rear channel layers. These methods have the following drawbacks: First, controlling oxygen partial pressure or sputtering power through magnetron sputtering requires extremely high stability of process conditions. Even small fluctuations in oxygen partial pressure or power can affect the carrier concentration of the thin film and the consistency of device performance. Furthermore, this method typically requires a high-temperature annealing step to obtain ideal electrical performance, making it difficult to integrate with flexible substrates and hindering applications in flexible electronics. Second, changing the sub-cycle period ratio through atomic layer deposition requires precise control of parameters such as the pulse sequence, cycle number, and deposition temperature of various metal precursors, resulting in complex processes and high control complexity. Third, using different oxidants to adjust the carrier concentration can affect the growth rate and chemical composition of the thin film. This not only increases process variables but may also introduce additional impurities or defect states, reducing the stability and reliability of the device. In summary, the fabrication methods for homogeneous dual-channel thin-film transistors suffer from numerous process parameters, high control difficulty, poor interlayer interface quality, and reliance on high-temperature annealing, making it difficult to meet the requirements of high-performance flexible electronic devices for low-temperature processes and high-quality interfaces. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a homogeneous multichannel thin-film transistor and a method for fabricating the same, which overcomes or at least partially solves the above problems, and can improve the interlayer interface quality while simplifying the fabrication process, without the need for high-temperature annealing.

[0006] Specifically, the present invention provides a method for fabricating a homogeneous multi-channel thin-film transistor, comprising: A gate and a gate dielectric layer are sequentially fabricated on a substrate; Using atomic layer deposition (ALD), at least two InGaO sub-channel layers are sequentially deposited on the gate dielectric layer in a direction away from the gate dielectric layer. Each InGaO sub-channel layer is stacked to form a channel layer. During deposition, each InGaO sub-channel layer uses either the same type of Ga precursor source and different types of In precursor sources, or the same type of In precursor source and different types of Ga precursor sources, to ensure that each InGaO sub-channel layer has a different carrier concentration. The sub-cycle period is the same during the deposition of each InGaO sub-channel layer. The channel layer is patterned to form a patterned channel layer; Source and drain electrodes are fabricated on the patterned channel layer to obtain a homogeneous multi-channel thin-film transistor.

[0007] Optionally, the carrier concentration of each InGaO sub-channel layer decreases layer by layer in the direction away from the gate dielectric layer.

[0008] Optionally, the thickness of each InGaO sub-channel layer increases layer by layer along the direction away from the gate dielectric layer.

[0009] Optionally, the sub-cycle includes: first growing a Ga2O3 sublayer of a first preset number of cycles, and then growing an In2O3 sublayer of a second preset number of cycles; or, first growing an In2O3 sublayer of a third preset number of cycles, and then growing a Ga2O3 sublayer of a fourth preset number of cycles. During the deposition of each InGaO sub-channel layer, the sub-cycle is repeated until each InGaO sub-channel layer reaches a preset thickness.

[0010] The types of Ga precursor sources include: trimethylgallium, tris(dimethylamino)gallium, triethylgallium, and gallium acetylacetonate; The types of In precursors include: cyclopentadienyl indium, [3-(dimethylamino)propyl]dimethyl indium, trimethyl indium, triethyl indium, dimethylbutylaminotrimethyl indium, indium chloride, and tris(2,2,6,6-tetramethyl-3,5-heptadecyl)indium.

[0011] Optionally, the channel layer includes two InGaO sub-channel layers, namely a front channel and a back channel, wherein the front channel is close to the gate dielectric layer and has a high carrier concentration, and the back channel is located above the front channel and has a low carrier concentration. The total thickness of the channel layer is 15 nm to 30 nm; the ratio of the thickness of the front channel to the thickness of the back channel is 0.2 to 1.0.

[0012] Optionally, in the atomic layer deposition process, the deposition temperature is 150–250°C.

[0013] Optionally, the gate dielectric layer includes one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2; The thickness of the gate dielectric layer is 30–50 nm.

[0014] Optionally, the step of patterning the channel layer includes: spin-coating positive photoresist onto the surface of the channel layer, and after drying, exposure, and development, a portion of the channel layer is covered by photoresist and a portion is exposed; etching the exposed area of ​​the channel layer by wet etching, and then removing the remaining photoresist to form a patterned channel layer. The steps of fabricating source and drain electrodes on the patterned channel layer include: spin-coating negative photoresist onto the surfaces of the gate dielectric layer and the patterned channel layer; after drying, exposure, drying again, and development, forming two openings on the negative photoresist corresponding to the source and drain regions, respectively; depositing conductive material such that the conductive material at least covers the patterned channel layer and the gate dielectric layer exposed at the openings; removing the negative photoresist and the conductive material on its surface, retaining the conductive material at the openings, to form the source and drain electrodes.

[0015] On the other hand, the present invention also provides a homogeneous multi-channel thin-film transistor, which is fabricated by the fabrication method described in any one of the above claims; The homogeneous multi-channel thin-film transistor comprises, from bottom to top: a substrate, a gate disposed on the substrate, a gate dielectric layer disposed on the gate, a channel layer disposed on the gate dielectric layer, and a source and a drain disposed on opposite sides of the channel layer, respectively; the channel layer comprises at least two InGaO sub-channel layers stacked sequentially from bottom to top, and the adjacent InGaO sub-channel layers are atomically directly contacted at an interface.

[0016] In the homogeneous multi-channel thin-film transistor and its fabrication method of the present invention, the channel layers are fabricated using atomic layer deposition (ALD). Each sub-channel layer is fabricated by keeping one of the metals, Ga or In, as the precursor source, while differentiating the precursor source of the other metal. Since the molecular structures of different precursors differ, they directly affect the deposition rate and density of the thin film. This allows for differentiated carrier concentration distribution in each sub-channel layer while maintaining the same sub-cycle period. Furthermore, the sub-channel layers are continuously grown through ALD, with atomic-level direct contact at the interface, eliminating the need for subsequent annealing to achieve low interface state defects and high interface quality. This fabrication method is simple, easy to operate, and can directly fabricate the homogeneous multi-channel thin-film transistor on a flexible substrate, enhancing its application in flexible electronics.

[0017] Furthermore, the thickness deposited in each sub-cycle is essentially consistent. By controlling the number of repetitions of the sub-cycle, the thickness of each sub-channel layer can be precisely controlled, eliminating the need to design complex deposition programs for different sub-channel layers. Moreover, the growth sequence and cycle number of each sub-layer within each sub-cycle are identical. After repeating multiple sub-cycles, the composition distribution within each sub-channel layer is uniform, preventing gradual changes in composition along the thickness direction and ensuring the uniformity of film quality for each individual sub-channel layer. Therefore, this invention simplifies process control by setting only three parameters: the sub-cycle period, the number of repetitions of the sub-cycle, and the precursor switching sequence, thus enabling the deposition of sub-channel layers.

[0018] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0019] The following sections will describe some specific embodiments of the invention in a detailed manner by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic flowchart of a method for fabricating a homogeneous multichannel thin-film transistor according to an embodiment of the present invention; Figure 2 This is a schematic structural diagram of a homogeneous multichannel thin-film transistor according to an embodiment of the present invention.

[0020] Figure label: 1. Substrate; 2. Gate; 3. Gate dielectric layer; 4. Front channel; 5. Back channel; 6. Channel layer; 7. Source; 8. Drain. Detailed Implementation

[0021] The following reference Figures 1 to 2 This invention describes a homogeneous multi-channel thin-film transistor and its fabrication method according to embodiments of the present invention. In this description, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature, that is, include one or more of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. When a feature "includes or contains" one or more of the features it encompasses, unless otherwise specifically described, this indicates that other features are not excluded and may be further included.

[0022] Furthermore, in the description of this embodiment, "above" or "below" the second feature can include direct contact between the first and second features, or it can include contact between the first and second features through another feature between them. That is, in the description of this embodiment, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," or "below" of the second feature can mean the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0023] In the description of this embodiment, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] Figure 1 This is a schematic flowchart illustrating a method for fabricating a homogeneous multichannel thin-film transistor according to an embodiment of the present invention, as shown below. Figure 1 As shown, and refer to Figure 2 This invention provides a method for fabricating a homogeneous multi-channel thin-film transistor, which may include the following steps: S100, gate 2 and gate dielectric layer 3 are sequentially fabricated on substrate 1; In S200, at least two InGaO sub-channel layers are sequentially deposited on the gate dielectric layer 3 in a direction away from the gate dielectric layer 3 using atomic layer deposition (ALD). These InGaO sub-channel layers are stacked to form the channel layer 6. During the deposition of each InGaO sub-channel layer, the same type of Ga precursor source and different types of In precursor sources, or the same type of In precursor source and different types of Ga precursor sources, are used to ensure that each InGaO sub-channel layer has a different carrier concentration. The sub-cycle period is the same during the deposition of each InGaO sub-channel layer. S300, patterning the channel layer to form a patterned channel layer; S400, source 7 and drain 8 are fabricated on a patterned channel layer to obtain a homogeneous multi-channel thin-film transistor.

[0025] Specifically, substrate 1 can be a flexible substrate or a rigid substrate. In step S200, an InGaO thin film is prepared on the gate dielectric layer 3 as a channel layer 6 using an atomic layer deposition process. The channel layer 6 is a homogeneous multi-channel structure with different carrier concentrations. The homogeneous multi-channel structure includes at least two InGaO sub-channel layers (e.g., two, three, or more layers) stacked sequentially from bottom to top.

[0026] In this embodiment, the channel layer is prepared using atomic layer deposition (ALD). Each sub-channel layer is prepared by keeping one of the metals, Ga or In, as the precursor source, while different metals are selected for the preparation. Since different precursors have different molecular structures, their steric hindrance, adsorption characteristics, and reactivity vary, directly affecting the deposition rate and film density. Under the same sub-cycle conditions, the gallium doping level and film density differ in InGaO films deposited with different Ga precursors; similarly, the indium doping level and film density differ in InGaO films deposited with different In precursors. Therefore, this embodiment can achieve differentiated carrier concentration distribution in each sub-channel layer while maintaining the same sub-cycle period. Furthermore, the sub-channel layers are continuously grown via ALD, with atomic-level direct contact at the interface, achieving low interface state defects and high interface quality without subsequent annealing. This fabrication method is simple and easy to operate, and can directly fabricate the homogeneous multi-channel thin-film transistor on a flexible substrate, thus enhancing its application in the field of flexible electronics.

[0027] In some optional embodiments of the present invention, in step S200, the sub-cycle includes: first growing a Ga2O3 sublayer of a first preset number of cycles, and then growing an In2O3 sublayer of a second preset number of cycles.

[0028] Preferably, the first preset number of cycles is 1 to 5 cycles, and the second preset number of cycles is 1 to 5 cycles.

[0029] More preferably, the ratio of the first preset number of cycles to the second preset number of cycles is 1:4 or 4:1.

[0030] In some optional embodiments of the present invention, in step S200, the sub-cycle includes: first growing an In2O3 sublayer for a third preset number of cycles, and then regrowing a Ga2O3 sublayer for a fourth preset number of cycles. For example, the third preset number of cycles is 1 to 5 cycles, and the second preset number of cycles is 1 to 5 cycles.

[0031] In some optional embodiments of the present invention, in step S200, during the deposition of each InGaO sub-channel layer, the sub-cycle is repeated until each InGaO sub-channel layer reaches a preset thickness.

[0032] In this embodiment, on the one hand, the sub-cycle is repeated, and the thickness deposited in each sub-cycle is basically consistent. By controlling the number of repetitions of the sub-cycle, the thickness of each sub-channel layer can be precisely controlled, eliminating the need to design complex deposition programs for different sub-channel layers. On the other hand, the growth sequence and number of cycles for each sub-layer are exactly the same within each sub-cycle. After repeating multiple sub-cycles, the composition distribution inside each sub-channel layer is uniform, and there is no problem of gradual changes in composition along the thickness direction, ensuring the uniformity of film quality. Therefore, this embodiment can complete the deposition of sub-channel layers by setting three parameters: the sub-cycle, the number of repetitions of the sub-cycle, and the precursor switching sequence. The process control is simple and easy to transfer between different equipment and production lines.

[0033] In some optional embodiments of the present invention, the carrier concentration of each InGaO sub-channel layer decreases layer by layer along the direction away from the gate dielectric layer. Specifically, the carrier concentration of each InGaO sub-channel layer decreases layer by layer from bottom to top.

[0034] In this embodiment, the InGaO sub-channel layer near the gate has a high carrier concentration, which is beneficial for fully utilizing the turn-on channel and carrier transport functions to achieve high mobility. Conversely, the InGaO sub-channel layer away from the gate has a low carrier concentration, which is beneficial for controlling conduction characteristics, suppressing off-state current, reducing carrier scattering, and improving device stability. Furthermore, by constructing a carrier concentration gradient distribution within the same InGaO material system, both high mobility and high stability can be achieved without the need for heterogeneous material stacking or annealing.

[0035] In some optional embodiments of the present invention, the thickness of each InGaO sub-channel layer increases progressively along the direction away from the gate dielectric layer. Specifically, the thickness of each InGaO sub-channel layer increases progressively from bottom to top.

[0036] In this embodiment, the sub-channel layer closer to the gate dielectric layer is thinner, allowing the gate electric field to penetrate more easily and making channel control more sensitive, thus resulting in crisper switching and faster response of the transistor. The sub-channel layer farther from the gate dielectric layer is thicker, resulting in lower contact resistance between the source / drain electrodes and the channel, smoother current injection, and the thicker layer also provides protection against external factors affecting channel performance, making the device more stable and reliable. The gradual increase in thickness and the gradual decrease in carrier concentration work together to ensure both high drive current and low power consumption and excellent switching characteristics.

[0037] In some alternative embodiments of the present invention, the types of Ga precursor sources include: trimethylgallium, tris(dimethylamino)gallium, triethylgallium, and gallium acetylacetonate.

[0038] Types of In precursors include: cyclopentadienyl indium, [3-(dimethylamino)propyl]dimethyl indium, trimethyl indium, triethyl indium, dimethylbutylaminotrimethyl indium, indium chloride, and tris(2,2,6,6-tetramethyl-3,5-heptadecyl)indium.

[0039] In some alternative embodiments of the present invention, the channel layer includes two InGaO sub-channel layers, namely a front channel and a back channel. The front channel is close to the gate dielectric layer and has a high carrier concentration, providing high mobility; the back channel is located above the front channel and has a low carrier concentration, reducing off-state current and improving stability.

[0040] The total thickness of the channel layer is 15nm to 30nm; the ratio of the thickness of the front channel to the thickness of the back channel is 0.2 to 1.0 to ensure effective control of the front channel by the gate, while the back channel provides sufficient stability.

[0041] In some optional embodiments of the present invention, in step S200, the atomic layer deposition process is carried out at a deposition temperature of 150 to 250°C (e.g., 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C or 250°C).

[0042] In this embodiment, the atomic layer deposition process uses a deposition temperature of 150–250°C. This temperature range falls within the medium-low temperature range, ensuring sufficient precursor reaction and uniform, dense film growth while achieving good electrical performance without the need for subsequent high-temperature annealing. Furthermore, this temperature range matches the temperature tolerance of flexible substrates (such as polyimide), enabling the direct fabrication of homogeneous multi-channel thin-film transistors on flexible substrates, providing a feasible technical solution for flexible electronic devices.

[0043] In some optional embodiments of the present invention, the gate dielectric layer includes one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2. The thickness of the gate dielectric layer is 30–50 nm. The gate dielectric layer is prepared using an atomic layer deposition process.

[0044] In this embodiment, an atomic layer deposition process is used to prepare a gate dielectric layer with a thickness of 30-50 nm, which can ensure good insulation performance and breakdown resistance, avoid thermal damage to the flexible substrate, and provide a high-quality dielectric interface for subsequent deposition of the channel layer.

[0045] In some optional embodiments of the present invention, the step of patterning the channel layer includes: spin-coating positive photoresist onto the surface of the channel layer, and after drying, exposure, and development, a portion of the channel layer is covered by photoresist and a portion is exposed; etching the exposed area of ​​the channel layer by wet etching, and then removing the remaining photoresist to form a patterned channel layer.

[0046] The steps of fabricating source and drain electrodes on the patterned channel layer include: spin-coating negative photoresist onto the surfaces of the gate dielectric layer and the channel layer; after drying, exposure, drying again, and development, forming two openings on the negative photoresist corresponding to the source and drain regions, respectively; depositing conductive material such that the conductive material at least covers the channel layer and the gate dielectric layer exposed at the openings; removing the negative photoresist and the conductive material on its surface, retaining the conductive material at the openings, to form the source and drain electrodes.

[0047] In this embodiment, positive photoresist lithography combined with wet etching can precisely remove unwanted portions of the channel layer, retaining only the pre-defined channel area. This process is simple, highly precise, and causes minimal damage to the channel layer during wet etching. Source and drain electrodes are fabricated using negative photoresist lithography followed by a lift-off process, enabling high-precision transfer of the electrode pattern. After lift-off, the electrode edges are neat and free of residual metal, ensuring good electrical contact between the source / drain electrodes and the channel layer. Simultaneously, the lift-off process avoids secondary damage to the channel layer caused by etching.

[0048] This invention also provides a homogeneous multi-channel thin-film transistor, which is fabricated by any of the methods described above.

[0049] The homogeneous multi-channel thin-film transistor comprises, from bottom to top: a substrate 1, a gate 2 disposed on the substrate 1, a gate dielectric layer 3 disposed on the gate 2, a channel layer 6 disposed on the gate dielectric layer 3, and a source 7 and a drain 8 disposed on opposite sides of the channel layer 6, respectively; the channel layer 6 includes at least two InGaO sub-channel layers stacked sequentially from bottom to top, and the interfaces between adjacent InGaO sub-channel layers are atomically directly contacted.

[0050] In some embodiments of the present invention, one end of the source 7 and the drain 8 are in contact with the channel layer 6, and the other end extends to the surface of the gate dielectric layer 3.

[0051] The fabrication method of the homogeneous multichannel thin-film transistor of the present invention will be further described in detail below with reference to specific embodiments.

[0052] Example 1 A method for fabricating a homogeneous multi-channel thin-film transistor includes the following steps: S11, substrate 1 is a glass substrate; a 100nm thick ITO (Indium Tin Oxide) is prepared on substrate 1 by magnetron sputtering as gate 2; a 40nm thick Al2O3 is prepared on gate 2 at a growth temperature of 200℃ by atomic layer deposition as gate dielectric layer 3.

[0053] In step S12, a 20 nm thick InGaO thin film is prepared on the gate dielectric layer 3 using atomic layer deposition (ALD) at a growth temperature of 200 °C as the channel layer 6. Channel layer 6 is a homogeneous dual-channel structure, comprising a front channel 4 and a back channel 5. The front channel has a thickness of 7 nm and a high carrier concentration, while the back channel has a thickness of 13 nm and a low carrier concentration. The front and back channels are prepared using the same type of Ga precursor source and different types of In precursor sources. Specifically, the Ga precursor source is trimethylgallium (TMGa), the In precursor source for the front channel is cyclopentadienyl indium (InCP), and the In precursor source for the back channel is [3-(dimethylamino)propyl]dimethyl indium (DADI). The sub-cycle periods are the same during the preparation of the front channel 4 and the back channel 5.

[0054] The ALD sub-cycle first grows one cycle of Ga2O3 sublayer, then grows four cycles of In2O3 sublayer, and repeats this large cycle until the preset thickness of each sub-channel layer is reached.

[0055] The single-cycle growth of the Ga2O3 sublayer is as follows: Ga precursor is introduced for 0.3 s, inert gas high-purity argon is purged for 12 s, oxygen plasma is introduced for 20 s, and inert gas high-purity argon is purged for 10 s.

[0056] The single-cycle growth of the In2O3 sublayer is as follows: In precursor is introduced for 0.3 s, inert gas high-purity argon is used for 12 s cleaning, oxygen plasma is introduced for 20 s, inert gas high-purity argon is used for 10 s cleaning, and the In2O3 sublayer is grown in this cycle 4 times.

[0057] S13, pattern the channel layer 6 to form a patterned channel layer.

[0058] Positive photoresist S1813 was spin-coated onto the surface of channel layer 6 under the following conditions: spin-coating at 600 r / min for 6 s, followed by spin-coating at 4000 r / min for 60 s, and then baked at 115°C for 1 min on a hot stage. Exposure was performed using a UV exposure machine, followed by development and etching in phosphoric acid for 20 s to etch excess InGaO film. The positive photoresist was then cleaned with acetone to form a patterned channel structure with a cross-sectional dimension of 50 μm in length and 200 μm in width.

[0059] S14, source 7 and drain 8 are fabricated on patterned channel layer 6.

[0060] Negative photoresist N4340 was spin-coated onto the surfaces of the gate dielectric layer 3 and the channel layer 6 under the following conditions: spin-coating at 600 rpm for 6 seconds and spin-coating at 4000 rpm for 60 seconds, followed by baking at 95°C for 1 minute on a hot stage. Exposure was then performed using a UV exposure machine, followed by baking at 90°C for 1.5 minutes on a hot stage, and finally development in a 1:1 mixture of positive photoresist developer and deionized water for 1 minute. The development was observed under a microscope to ensure complete development.

[0061] A 50nm Au / 10nm Cr electrode was deposited using a thermal evaporation process as the conductive material for the source and drain electrodes. The negative photoresist and its metal were removed using acetone via a stripping method to form the source and drain electrodes, resulting in a homogeneous multi-channel thin-film transistor.

[0062] Example 2 A method for fabricating a homogeneous multi-channel thin-film transistor includes the following steps: S21, substrate 1 is a SiO2 / Si composite substrate; 50nm Au / 10nm Cr is deposited on substrate 1 as gate 2 using thermal evaporation process; 40nm thick Al2O3 is prepared on gate 2 as gate dielectric layer 3 using atomic layer deposition process at a growth temperature of 200℃.

[0063] S22, a 20 nm thick InGaO thin film is prepared on the gate dielectric layer 3 using atomic layer deposition at a growth temperature of 200 °C as the channel layer 6. The channel layer 6 is a homogeneous dual-channel structure, including a front channel 4 and a back channel 5. The front channel has a thickness of 7 nm and a high carrier concentration, while the back channel has a thickness of 13 nm and a low carrier concentration. The front and back channels are prepared using the same type of In precursor source and different types of Ga precursor sources. Specifically, the In precursor source is trimethylindium (In(CH3)3), the Ga precursor source for the front channel 4 is tris(dimethylamino)gallium (Ga(NMe2)3), and the Ga precursor source for the back channel 5 is gallium acetylacetonate (Ga(acac)3). The sub-cycle period is the same during the preparation of the front channel 4 and the back channel 5.

[0064] The ALD sub-cycle first grows four cycles of Ga2O3 sublayers, then grows one cycle of In2O3 sublayers, and repeats this large cycle until the preset thickness of each sub-channel layer is reached.

[0065] The single-cycle growth of the Ga2O3 sublayer is as follows: Ga precursor is introduced for 0.3s, inert gas high-purity argon is used for cleaning for 12s, oxygen plasma is introduced for 20s, inert gas high-purity argon is used for cleaning for 10s, and the Ga2O3 sublayer is grown in this cycle 4 times.

[0066] The single-cycle growth of the In2O3 sublayer is as follows: In precursor is introduced for 0.3 s, inert gas high-purity argon is purged for 12 s, oxygen plasma is introduced for 20 s, and inert gas high-purity argon is purged for 10 s.

[0067] S23, pattern the channel layer 6 to form a patterned channel layer.

[0068] Positive photoresist S1813 was spin-coated onto the surface of channel layer 6 under the following conditions: spin-coating at 600 r / min for 6 s, followed by spin-coating at 4000 r / min for 60 s, and then baked at 115°C for 1 min on a hot stage. Exposure was performed using a UV exposure machine, followed by development and etching in phosphoric acid for 20 s to etch excess InGaO film. The photoresist was then cleaned with acetone to form a patterned channel structure with a cross-sectional dimension of 50 μm in length and 200 μm in width.

[0069] S24, source 7 and drain 8 are fabricated on patterned channel layer 6.

[0070] Negative photoresist N4340 was spin-coated onto the surfaces of the gate dielectric layer 3 and the channel layer 8 under the following conditions: spin-coating at 600 rpm for 6 s and spin-coating at 4000 rpm for 60 s. The surfaces were then baked at 95°C for 1 min on a hot stage. Exposure was performed using a UV exposure machine, followed by baking at 90°C for 1.5 min on a hot stage. The surfaces were then immersed in a 1:1 mixture of positive photoresist developer and deionized water for 1 min. The development effect was observed under a microscope to ensure complete development.

[0071] A 50nm Au / 10nm Cr electrode was deposited using a thermal evaporation process as the conductive material for source 7 and drain 8. The negative photoresist and its metal were removed using acetone via a stripping method to form source 7 and drain 8, thus obtaining a homogeneous multi-channel thin-film transistor.

[0072] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for fabricating a homogeneous multi-channel thin-film transistor, characterized in that, include: A gate and a gate dielectric layer are sequentially fabricated on a substrate; Using atomic layer deposition (ALD), at least two InGaO sub-channel layers are sequentially deposited on the gate dielectric layer in a direction away from the gate dielectric layer. Each InGaO sub-channel layer is stacked to form a channel layer. During deposition, each InGaO sub-channel layer uses either the same type of Ga precursor source and different types of In precursor sources, or the same type of In precursor source and different types of Ga precursor sources, to ensure that each InGaO sub-channel layer has a different carrier concentration. The sub-cycle period is the same during the deposition of each InGaO sub-channel layer. The channel layer is patterned to form a patterned channel layer; Source and drain electrodes are fabricated on the patterned channel layer to obtain a homogeneous multi-channel thin-film transistor.

2. The preparation method according to claim 1, characterized in that, The carrier concentration in each InGaO sub-channel layer decreases layer by layer in the direction away from the gate dielectric layer.

3. The preparation method according to claim 1, characterized in that, The thickness of each InGaO sub-channel layer increases progressively in the direction away from the gate dielectric layer.

4. The preparation method according to claim 1, characterized in that, The sub-cycle includes: first growing a Ga2O3 sublayer of a first preset number of cycles, and then growing an In2O3 sublayer of a second preset number of cycles; or, first growing an In2O3 sublayer of a third preset number of cycles, and then growing a Ga2O3 sublayer of a fourth preset number of cycles. During the deposition of each InGaO sub-channel layer, the sub-cycle is repeated until each InGaO sub-channel layer reaches a preset thickness.

5. The preparation method according to claim 1, characterized in that, The types of Ga precursor sources include: trimethylgallium, tris(dimethylamino)gallium, triethylgallium, and gallium acetylacetonate; The types of In precursors include: cyclopentadienyl indium, [3-(dimethylamino)propyl]dimethyl indium, trimethyl indium, triethyl indium, dimethylbutylaminotrimethyl indium, indium chloride, and tris(2,2,6,6-tetramethyl-3,5-heptadecyl)indium.

6. The preparation method according to claim 1, characterized in that, The channel layer includes two InGaO sub-channel layers, namely a front channel and a back channel. The front channel is close to the gate dielectric layer and has a high carrier concentration, while the back channel is located above the front channel and has a low carrier concentration. The total thickness of the channel layer is 15 nm to 30 nm; the ratio of the thickness of the front channel to the thickness of the back channel is 0.2 to 1.

0.

7. The preparation method according to claim 1, characterized in that, In the atomic layer deposition process, the deposition temperature is 150–250°C.

8. The preparation method according to claim 1, characterized in that, The gate dielectric layer includes one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2; The thickness of the gate dielectric layer is 30–50 nm.

9. The preparation method according to claim 1, characterized in that, The step of patterning the channel layer includes: spin-coating positive photoresist onto the surface of the channel layer, and after drying, exposure, and development, a portion of the channel layer is covered by photoresist and a portion is exposed; etching the exposed area of ​​the channel layer by wet etching, and then removing the remaining photoresist to form a patterned channel layer. The steps of fabricating source and drain electrodes on the patterned channel layer include: spin-coating negative photoresist onto the surfaces of the gate dielectric layer and the patterned channel layer; after drying, exposure, drying again, and development, forming two openings on the negative photoresist corresponding to the source and drain regions, respectively; depositing conductive material such that the conductive material at least covers the openings; removing the negative photoresist and the conductive material on its surface, retaining the conductive material at the openings, to form the source and drain electrodes.

10. A homogeneous multi-channel thin-film transistor, characterized in that, The homogeneous multichannel thin-film transistor is fabricated by the fabrication method according to any one of claims 1 to 9; The homogeneous multi-channel thin-film transistor comprises, from bottom to top: a substrate, a gate disposed on the substrate, a gate dielectric layer disposed on the gate, a channel layer disposed on the gate dielectric layer, and a source and a drain disposed on opposite sides of the channel layer, respectively; the channel layer comprises at least two InGaO sub-channel layers stacked sequentially from bottom to top, and the adjacent InGaO sub-channel layers are atomically directly contacted at an interface.

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