Dynamic random access memory, semiconductor structure and manufacturing method and packaging structure
By designing alternating stacked conductive and dielectric layers in 3D DRAM and setting optimized extension structures in between, the problems of storage density and capacitance uniformity are solved, thereby improving the performance and stability of the memory.
CN122641005APending Publication Date: 2026-08-25YANGTZE MEMORY TECHNOLOGIES HOLDING CO LTD
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Patent Information
- Application Number
- CN202510162191.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2026-08-25
AI Technical Summary
Technical Problem
There is still room for improvement in the storage density and capacitance uniformity of existing 3D DRAM memories.
Method used
The design employs a semiconductor substrate and a stacked structure, forming first and second extension structures by alternating stacking of conductive and dielectric layers. These extension structures are electrically connected to or insulated from the conductive or bit line layers, respectively. The size and arrangement of the extension structures are optimized to reduce the non-uniformity of coupling capacitance between adjacent layers.
Benefits of technology
This improves the uniformity of coupling capacitance and resistance between adjacent conductive layers, thereby enhancing the memory's storage density and performance stability.
✦ Generated by Eureka AI based on patent content.
Abstract
Embodiments of the present disclosure provide a dynamic random access memory, a semiconductor structure and a manufacturing method and a packaging structure. The dynamic random access memory comprises: a semiconductor body extending along a first direction; a stack structure disposed on one side of the semiconductor body along the first direction, the stack structure comprising a plurality of conductive layers and a plurality of first dielectric layers alternately stacked along a second direction, the semiconductor body being coupled to the conductive layers, the first direction and the second direction intersecting; a first extension structure and a second extension structure, both of which extend through part of the stack structure along the second direction, the first extension structure comprising opposite first and second ends along the second direction, the second extension structure comprising opposite third and fourth ends along the second direction, the first and third ends being respectively disposed on opposite sides of the stack structure along the second direction, and the conductive layers being coupled to at least one of the second and fourth ends.
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