Method and system for electrical transmission of symbols

Abstract

The invention also relates to a method and a system for electrically transmitting a symbol from a first user to a second user, the first user and the second user being connected via a common multi-conductor device having at least a first electrical conductor, a second electrical conductor and a third electrical conductor, wherein in the first user at least three series circuits are operated, each consisting of an upper electronic switch and a lower electronic switch, wherein the electrical conductors are connected on the respective series circuit between the upper electronic switch and the lower electronic switch.

Description

Technical Field

[0001] The problem upon which this invention is based is the electrical transmission of information between two or more users connected by a common set of electrical conductors (bus). A particular challenge here is to increase the achievable transmission rate while maintaining robustness against both self-interference and external interference during operation.

[0002] The present invention relates to a system for transmitting symbols between a first user and a second user via a common multiconductor device.

[0003] The present invention also relates to a method for electrical transmission from a first user to a second user symbol, the first user and the second user being connected via a common multiconductor device having at least a first electrical conductor, a second electrical conductor and a third electrical conductor, wherein at least three series circuits consisting of an upper electronic switch and a lower electronic switch operate in the first user, wherein an electrical conductor is connected between the upper electronic switch and the lower electronic switch in the respective series circuit. Background Technology

[0004] Currently, there are several schemes for wired information transmission. In traditional parallel buses, multiple asymmetric lines are bundled together, with each line carrying information in its potential difference relative to a common reference signal; typically, each line uses a binary level system to carry 1 bit. Receivers usually evaluate this information using a hard-decision threshold. Combined with often uncontrolled line adaptation, this transmission method is highly sensitive to self-interference and external interference, and due to various high-frequency effects (reflection, limited signal power, crosstalk, EMC interference, etc.), it can usually only operate at low baud rates.

[0005] Differential line systems, such as LVDS, CML, or PECL, typically do not have these signal integrity issues and allow operation at very high baud rates. However, these systems are less efficient in terms of data transmission, cost, and current consumption. Typically, one bit of data can be transmitted via a coupled two-wire line, corresponding to an efficiency of 0.5 bits per line.

[0006] This problem was addressed in the ET200SP system, Siemens' distributed automation system, which employed a special backplane bus system. By utilizing a special encoding method, many signal integrity issues were successfully eliminated from traditional parallel buses, thus achieving considerable data rates on a reliable bus with significant length and numerous users. However, this system no longer allowed for further (significant) performance improvements.

[0007] EP 1 038 232 B1 describes a communication interface for serial transmission of digital data or a serial data transmission method for transmitting digital data bit by bit.

[0008] This solution addresses the susceptibility to interference and synchronization issues in serial data transmission. It comprises a communication interface and a data transmission method that enables interference-resistant and efficient digital data transmission. This innovation utilizes at least three signal lines, each capable of applying a "high" or "low" level. Data bits are encoded by level changes on two of the three lines, with the transitions between level states determined within the encoding scheme. This enables rapid synchronization and high data rates, comparable to synchronous transmission, without the drawbacks of clock recovery or asynchronous transmission. Start / stop synchronization is achieved by inverting all levels, which is particularly efficient for short data packets. This invention is particularly suitable for use in automated equipment for controlling and monitoring processes.

[0009] EP 2 154 590 B1 relates to a method for identifying the plug-in location of a control module in a modularly constructed control device. Patent EP 2 154 590 B1 describes a method for identifying the plug-in location of a control module in a modularly constructed control device, such as a programmable logic controller (PLC). The innovation lies in the explicit and simplified addressing of the control module by its plug-in location. This is achieved through a special data pattern transmitted via a communication bus and permuted at each plug-in location change, such that each plug-in location acquires a unique pattern. The bus lines are divided into multiple groups, and the permutation occurs within these groups, which increases the number of addressable plug-in locations. This method allows modules to be replaced during continuous operation without reconfiguration. Advantages include high availability and modular scalability of the control device, the elimination of active backplane bus components, which improves reliability and minimizes location requirements. Useful data can be transmitted simultaneously with address data, which improves system efficiency.

[0010] The method described in EP 0 150 540 A2 involves data transmission between multiple stations via a common data bus, where signals are associated via OR functions. The core of this solution involves periodically transmitting each data bit within defined sub-cycles, these sub-cycles having specific ratios to each other. A signal transition is generated at the beginning of each cycle, which determines the total cycle duration and the position of the sub-cycle. A signal marking the data bus as "occupied" is sent in the first sub-cycle, the actual data bits are transmitted in the second sub-cycle, and a signal without information content is sent in the third sub-cycle. Stations can derive the cycle duration from the signal transitions and determine the state of the data bus and the value of the transmitted data bits. This enables efficient data transmission even when stations have different internal clock frequencies and supports multi-master operation.

[0011] The disclosure given in EP 0 977 126 A2 relates to an interface circuit for connecting devices via a bidirectional bus, particularly an I2C bus, which uses data lines and clock lines to transmit signals. The innovation therein lies in the splitting of the I2C bus signals into transmit and receive branches and transmitting them via differential lines through differential transmitter / receiver components. This minimizes physical interference through differential signal transmission, enabling interference-resistant data transmission even over long distances. The circuit arrangement on each device includes optocouplers for electrical isolation and to prevent interference caused by level differences. The receiver of the bus driver is always active, while the transmitter is activated only when transmitting a "0", controlled by enable logic. The differential lines are terminated at their ends by resistors representing characteristic impedance to generate a bus potential when the transmitter is deactivated. This interface circuit is particularly suitable for error-free data transmission between devices in microsurgery, such as in the case of a TEM insufflation system, while maintaining the transmission frequency and protocol of the I2C bus. This invention enables improved data communication between medical devices, which is important for precise and reliable functioning.

[0012] DE 60 126 191 T2 discloses a CMOS bus driver circuit specifically designed to address the problem of applying a voltage higher than the supply voltage to the circuit output. This can occur when different integrated circuits with different supply voltages are connected via a bus. The circuit consists of an input stage with two complementary MOS transistors and an output stage with two complementary MOS transistors. A key feature of this invention is the integration of an additional MOS transistor between the circuit output and the gate junction of the transistors in the output stage. This transistor is controlled by the supply voltage and protects the circuit by switching to the on state and thus turning off the corresponding output transistor when the voltage at the output is too high. A diode in the input stage blocks current to the transistor connected to the supply voltage and thus prevents reverse current. An additional MOS transistor connected in parallel with the diode ensures that the diode is bypassed during normal operation, allowing the circuit to quickly switch to the off state. A cutoff circuit consisting of the additional MOS transistor, an inverter, and a NOR circuit places the output stage in a high-ohm state when no enable signal is applied, thus preventing current from flowing into the circuit from the bus. This solution enables the circuit to operate reliably even within a narrow supply voltage range and protects it from damage caused by voltages higher than the supply voltage.

[0013] EP 4 226 254 A1 discloses a method and apparatus for data communication via a serial three-wire bus interface, particularly relevant to the MIPI Alliance's C-PHY interface. The invention relates to generating multiple differential signals, each representing a voltage difference between a pair of wires in a three-wire bus. A key feature of the invention is the identification of the differential signal with the maximum voltage amplitude within a specific time interval (i.e., the so-called unit interval UI) and the determination of the signal state of the three-wire bus of the UI based on the identity of the wire pair providing the first differential signal and the polarity of the signal within that UI. The invention enables the generation of a first edge in a clock signal that responds to a transition in the first differential signal during the UI. This improves clock signal recovery and reliable detection of wire states at higher data rates. The invention also includes calibration circuitry for adapting equalizer circuitry in a differential receiver based on the number of UIs at which the first differential signal has the maximum voltage amplitude during the C-PHY preamble. This invention is particularly important for improving data transmission and processing in mobile devices, such as smartphones and tablets, that connect to cameras and displays via a C-PHY interface.

[0014] US 9,692,555 B2 relates to transmitting information over a multi-wire line, wherein a set of symbols is received. A key aspect of this invention is the use of a first two-input comparator connected to a multi-wire bus to generate a first output signal based on a comparison of a pair of symbols with different values. An arithmetic circuit receives the symbol pair and produces an arithmetic result, which is then used by a second two-input comparator to generate a second output signal. This second output signal represents a comparison of the arithmetic result with a third symbol that does not belong to the symbol pair. This invention enables a reduction in the number of comparators required, resulting in a simpler and less energy-intensive system configuration. The invention can also be applied recursively to design larger sparse comparator units (SCUs) from smaller SCUs, improving system flexibility and scalability.

[0015] The apparatus and method proposed in DE 10 2006 061 651 B4 are used to encode blocks of transform coefficients used in digital image compression methods such as JPEG2000. The coefficients are represented by multiple numerical bits arranged in a bit plane. The encoding device traverses these numerical bits in tuples and encodes them into a data stream. Each numerical bit belongs to one of three traversals. A special feature is the prediction device, which predicts the numerical bits to be encoded in the next tuple. This is based on previous predictions and the state information of the coefficients. The prediction allows the encoding device to efficiently determine which bits should be encoded. The data words are stored in a buffer and subsequently entropy encoded, where the sequence of traversals is maintained.

[0016] This device achieves an efficient hardware implementation for image compression by reducing the number of processing steps and allowing parallel processing of multiple coefficients. This optimizes computational power, which is particularly advantageous for complex coefficient bit modeling.

[0017] EP 3 637 715 B1 relates to a transmitting device and a receiving device designed for efficiently transmitting data streams, particularly image data, through multiple parallel transmission paths (channels). This invention enables training processes to be performed for synchronizing and correcting time differences between channels when specific parameters involving physical layer processing, such as the number of transmission paths or transmission rate, are changed. However, if parameters of the connection layer, such as the bit length per pixel or the number of rows, are changed, the data stream can continue to be transmitted without this training process. This improves efficiency because it avoids unnecessary interruptions. The invention also includes a method for signaling parameter changes by using flags or by directly transmitting the changed parameters in the packet header. This technology is particularly relevant for systems requiring fast and reliable transmission of large amounts of data, such as in medical imaging or endoscopic systems.

[0018] EP 2 683 124 B1 relates to a transmitting / receiving device, particularly for use in automation technology, for digital data transmission according to the Low Voltage Differential Signaling Standard (LVDS). The device includes a transmitting unit, a receiving unit, and protocol devices. The novelty lies in a special circuit arrangement that enables faster signal stabilization at the receiving unit and thus ensures error-free signal transmission even over long data transmission distances. This is achieved by arranging capacitors and resistors in the receiving longitudinal branch, wherein the values ​​of these components are specifically adapted. Furthermore, potential separation is achieved through AC coupling devices, which is advantageous for use with components powered by different voltage sources. Therefore, this invention solves the problems of limited line length and potential difference in conventional LVDS connections and allows for improved and more robust data transmission in automation systems.

[0019] The LVDS (Low Voltage Differential Signal Driver) proposed in DE10 155 526 C2 is designed for use at low supply voltages below 2V, which is particularly relevant for integrated circuits with high structure density. The invention lies in using only PMOS transistors for pull-up and pull-down functions, achieving symmetrical switching behavior and operation in the linear region. By limiting the maximum amplitude of the control signal to a value slightly above the transistor's turn-on threshold voltage, it is ensured that the transistor can efficiently switch between off and on states without compromising switching quality at low supply voltages. Summary of the Invention

[0020] The objective of this invention is to improve known systems and methods for transmitting symbols in order to achieve performance improvements in data transmission with respect to data rate.

[0021] The solution to this task includes, in particular, a system for transmitting symbols between a first user and a second user connected via a common multi-conductor device having a first electrical conductor, a second electrical conductor, and a third electrical conductor. The first user includes a symbol encoder, a current source module, and a control block, wherein the control block has an upper control block and a lower control block. The upper control block is designed to close and open an upper switch, and the lower control block is designed to open and close a lower switch. The upper switch has at least three upper electronic switches, and the lower switch has at least three lower electronic switches. At least three series circuits are arranged, each consisting of an upper electronic switch and a lower electronic switch, with electrical conductors connecting the upper and lower electronic switches to the respective series circuits. The current source module is connected to these series circuits. The task is solved by the symbol encoder being designed to provide a current loop control vector for the control block, wherein the control block is designed to switch the electronic switches by means of a current loop control vector having switch combinations for the electronic switches and thus allowing current to flow into the connected electrical conductors. The symbol encoder is designed to determine the current loop control vector, such that the symbol to be transmitted is determined and thereby encoded by orderly selection of conductor pairs from the set of electrical conductors of the multi-conductor device. The conductor pair here includes one conductor as the outgoing conductor for the current from the first user to the second user and the other conductor as the return conductor. Furthermore, a termination unit is provided, wherein the symbol encoder is designed to provide a termination vector to the termination unit. The termination unit is further designed to connect a termination resistor network to the electrical conductors of the multi-conductor device via termination switches. The second user has a comparator network, wherein the comparator network is designed to detect voltage levels between the two electrical conductors respectively in order to decode the symbol, wherein the symbol is encoded in the different voltage levels between the electrical conductors.

[0022] In the context of this invention, the upper and lower electronic switches should be understood as a half-bridge consisting of two switches connected in series with a voltage or current source. Therefore, in the context of this invention, the upper and lower electronic switches are, for example, semiconductor switches, wherein the upper electronic switch is arranged in the upper circuit relative to the terminating resistor, and the lower electronic switch is arranged in the lower circuit relative to the terminating resistor. They are also referred to as high-side drivers (power supply switch to the first output terminal of the current source module) and low-side drivers (ground switch to the second output terminal of the current source module). In advantageous embodiments, the switches can be manipulated such that the potential of the current or voltage source is not fully switched on, thereby allowing different currents to be applied to the terminating resistor and thus generating signal voltages of different magnitudes, particularly more than two different signal voltages.

[0023] Advantageously, optional configuration of signal paths is now used to encode symbols. The basic idea of ​​this method is to sequentially select one or more conductor pairs from a set of multi-conductor devices to encode transmitted information. The information is encoded within the sequential selection of conductors. This invention is particularly applicable to control and monitoring processes in automated equipment. Conventional digital parallel bus systems provide high information density per bus line but are highly susceptible to signal integrity issues and therefore cannot operate at high signaling rates. Single-point or multi-point differential conductor systems are very robust to their own and external effects but cannot provide high information density. Analog or hybrid transmission methods (e.g., OFDM) address this problem but require complex system components, which significantly impact power consumption during continuous operation. This invention now allows for the elimination of the drawbacks of conventional methods in a low-cost and scalable manner within the system.

[0024] Another design scheme specifies that the symbol encoder is designed to provide multiple current loop control vectors, wherein the control block is designed to operate a common multi-conductor device with multiple current loops.

[0025] Therefore, in a conductor system with N conductors, for the application of the first current loop, there are a total of N (N-1) different feasible schemes are extracted from the transmitted symbol stream by the symbol encoder through the first current loop control vector. The flow of the second current loop can now be selected into a reduced set of conductors in the same pattern, thus opening up (N-2) control vectors for the second current loop. The feasible scheme space is (N-3). This control vector is also extracted from the transmitted symbol stream by the symbol encoder. This method can now be continued for additional current loops, provided the remaining conductor set is large enough. Overall, according to this rule, for L current loops applied to N lines, a feasible scheme space of N! / (N–2L)! symbols is obtained. Therefore, to further encode the symbols to be transmitted, the selection set L of current loops is determined from the number of conductors N, thereby increasing the symbol set.

[0026] To further expand the symbol set, the control block and / or current source module are designed to apply different signal currents to each current loop. When using multiple conductor pairs, it is crucial that their signal currents are of different magnitudes and in reliable ratios to each other.

[0027] During reception, the comparator network is active and continuously records the relative ratios of voltage levels in the multi-conductor device in the (digital) receive vector. The symbol decoder extracts the output symbol stream from this receive vector, and for this purpose, the comparator network is designed to assign the detected voltage levels as elements to the receive vector.

[0028] Another design scheme sets up a symbol decoder, which is designed to receive the received vector and perform maximum and minimum value determination on the sequence of elements of the received vector, and is also designed to provide binary sequences in which the maximum or minimum level is marked as the position in the sequence.

[0029] The system is further improved through progressive "received vector reduction"; for this purpose, the system has a first discriminator, a second discriminator, a first reducer, and a second reducer. The first discriminator is designed as a minimum-maximum conductor pair discriminator and is therefore designed to receive the received vector and detect conductor pairs with maximum and minimum relative levels in a multi-conductor device, and is also designed to provide the detection result as first conductor pair information. The first discriminator is connected to the first reducer and is designed to provide a reduced received vector using the first conductor pair information. The second discriminator is designed as another minimum-maximum conductor pair discriminator and is therefore designed to receive the reduced received vector and detect conductor pairs with maximum and minimum relative levels respectively in a multi-conductor device with identified reduced conductor pairs, and is also designed to provide the detection result as second conductor pair information. The second discriminator is connected to the second reducer and is designed to provide a further reduced received vector using the second conductor pair information.

[0030] This invention allows for the construction of bus-capable multi-conductor devices for information transmission using simple, CMOS chip-integrable components. These devices achieve signal integrity characteristics and transmission rates similar to, for example, LVDS, but with significantly more efficient information encoding while maintaining a relatively low increase in current consumption. This is achieved by the following characteristic: only a few current loops of varying intensities are applied to the conductor system at any given time. Since the current loops are clearly formed at the transmitting end and identified at the receiving end by means of their relative current intensity ratios, information encoding is performed by selecting individual conductors for the corresponding outgoing and return conductors for each individual current loop. The receiver can identify each current loop and determine its flow direction through a rapid iterative process. This requires only a simple pure binary request using a comparator. By using impedance-controlled and low-reflection line-guiding techniques and appropriate termination, the transmission system can achieve the highest signaling rate with relatively low complexity and moderate current consumption.

[0031] The task described at the beginning is also solved by a method for electrical transmission of symbols from a first user to a second user, the first and second users being connected via a common multi-conductor device having at least a first, second, and third conductor. In the first user, at least three series circuits, each consisting of an upper and lower electronic switch, operate, with conductors connected between the upper and lower electronic switches in their respective series circuits. Here, the symbol to be transmitted is encoded by selecting a combination of electronic switches, i.e., performing an ordered selection of conductor pairs from the set of conductors in the multi-conductor device. Current flows from the first user into one conductor in the multi-conductor device as the outgoing conductor via a current source through a closed upper electronic switch. A terminating resistor network is connected to the conductor in the multi-conductor device, thereby switching the current path for the current flowing in the outgoing conductor to another conductor. This other conductor is then used by the first user as the return conductor via a closed lower electronic switch. In the second user, to decode the symbol, voltage levels are detected between two conductors, and the symbol is recovered from the different voltage levels between the conductors. This enables the selective establishment of signal paths. The basic idea of ​​this method is to encode transmitted information by the ordered selection of one or more conductor pairs from a set of multi-conductor devices. The conductor pairs are then used to conduct one or more signal currents.

[0032] In a multi-conductor device with N conductors, the application of a first current loop generates a total of N. There are (N-1) different feasible solutions. For the second current loop, (N-2) solutions are generated. (N-3) feasible schemes. In general, according to this specification, for the method of applying current loops to N lines, a feasible scheme space consisting of N! / (N–2L)! symbols is obtained. Here, L represents the quantity of current loops. Therefore, a common multi-conductor device with N conductors is operated, wherein a current loop is formed between the first user and the second user by means of electronic switches of the conductors and a network of termination resistors, wherein, in order to further encode the symbols to be transmitted, the selection set L of current loops is determined from the number of conductors of the conductors, thereby increasing the symbol set.

[0033] Different signal currents are advantageously applied to each current loop in the selection set L, thereby further increasing the symbol set.

[0034] The voltage levels between electrical conductors are preferably detected using a comparator network, where the detected voltage levels are assigned as elements of a receiving vector. The receiving vector can be formed by sequentially scanning each conductor, where the relative ratios of the voltage levels in the conductor system are recorded sequentially in the receiving vector. One convention, for example, can be seen in chart theory as follows: the conductors are arranged as nodes on a circular line. In a four-conductor system, there would be nodes A, B, C, and D. Edges between nodes can be drawn clockwise, starting from node A. If the starting node is reached again, diagonal or lateral connections can also be drawn as edges. Accordingly, the voltage levels between nodes or conductors A->B, B->C, C->D, D->A, A->C, and B->D are obtained as edges. The receiving vector might look like this: Receive vector = {+1V, +2V, -1V, 1V, 1V, 1V} However, this is not a fixed rule; other rules can also be considered.

[0035] Preferably, the received vector is supplied to the symbol decoder, wherein, on the one hand, a maximum value determination is performed on the element sequence of the received vector, and on the other hand, a minimum value determination is performed, and binary sequences are provided respectively, in which the maximum or minimum level is marked as its position in the sequence. The decoding of symbols in the symbol decoder can be performed in a multi-level iterative process for a non-sparse and fully meshed comparator network. For this purpose, a "minimum-maximum conductor pair discriminator" identifies conductor pairs with the maximum and minimum relative levels in the conductor system and returns this information in the form of conductor pair information.

[0036] For the case where multiple current loops with different signal currents operate between the first user and the second user, the symbols are decoded as follows: In the first step, the voltage level between the electrical conductors is detected using a comparator network, and the detected voltage level is assigned as an element to the receiving vector; In the second step, the received vector is supplied to the symbol decoder, wherein, on the one hand, a maximum value determination is performed on the sequence of elements of the received vector, and on the other hand, a minimum value determination is performed, and binary sequences are provided respectively, in which the maximum level or the minimum level is marked as a position in the sequence; In the third step, the received vector is reduced to the position identified in the second step, wherein the reduced received vector is obtained; the reduced received vector is used to continue in the first step until the reduced received vector or another reduced received vector corresponds to a multi-conductor device with the number of conductors N=3.

[0037] In the preferred implementation with maximum performance, the comparator network includes a comparator for each unique pair of conductors in the conductor system. Using fewer comparators than the number of conductor pairs limits the size of the receive vector and the complexity of the symbol decoder, leading to a reduction in the possible number of symbols and thus limiting the system's throughput. When sparsifying the comparator network, it should be noted that asymmetric sparsification results in the loss of interchange tolerances in multi-conductor devices, potentially rendering the methods known in EP2 154 590 B1 for address resolution and plug position identification unusable. A compromise is to sparsify based on the equal distance between conductors, preserving symmetry and therefore interchange tolerances.

[0038] After the first step, it is now known which conductor pair provides the outgoing and return conductors for the current loop with the maximum loop current. Using this information, these conductors can now be removed from the receiving network or receiving vector during preparation for the second step, i.e., sparsified or reduced.

[0039] This invention enables the construction of a multi-conductor device with strong bus capabilities for information transmission using simple, CMOS chip-integrable components. This multi-conductor device achieves signal integrity characteristics and transmission rates similar to, for example, LVDS, but also features significantly more efficient information encoding with a proportional increase in current consumption. To this end, semiconductor components are designed as line drivers for electrical symbol transmission between a first user and a second user connected via a common multi-conductor device having at least a first, second, and third electrical conductor, wherein the line driver is designed to implement the method according to claim 1. Attached Figure Description

[0040] The accompanying drawings illustrate several embodiments of a system for data transmission between a first user and a second user via a shared multi-conductor device, wherein the method is also illustrated. (The drawings show:) Figure 1 This illustrates the principle of electrical transmission from a first user to a second user symbol via a shared multi-conductor device. Figure 2 This illustrates a four-conductor system with symbol transmission "BC". Figure 3 The diagram shows the symbol transmission "CB". Figure 2 The four-conductor system in the middle; Figure 4 A four-conductor system with two current loops is shown; Figure 5 This illustrates a typical arrangement of transceivers on a multi-conductor device. Figure 6 The diagram shows the block diagram of the transceiver. Figure 7 This illustrates the principle of the control block; Figure 8 The comparator network is shown. Figure 9 A block diagram of a symbol encoder is shown. Figure 10 A block diagram of the termination unit is shown; Figure 11 A diagram showing the comparison of different conductor systems; Figure 12 shows a decoding example that extends to... Figure 12A , 12B 12C and 12D Figure 13 illustrates a method for reducing the receive vector, extending to... Figure 13A , 13B And 13C, Figure 14 This illustrates possible implementations of the comparator. Figure 15 The first step of evaluating the received vector is shown, followed by reduction. Figure 16 The second step of reduction is shown. Figure 17 Showing a reduced table overview, Figure 18 The third step of reduction is shown. Figure 19 The fourth step of reduction is shown. Figure 20 The fifth step of reduction is shown. Figure 21 The diagram illustrates the integration of the unit into a transceiver circuit. Figure 22This illustrates a transceiver circuit on a multi-conductor device. Figure 23 This shows the possible bus topologies. Figure 24 This demonstrates the parallel operation of different conductor systems; Figure 25 This shows the termination during parallel operation; Figure 26 Showing dynamic termination, and Figure 27 This illustrates the hybrid operation between LVDS and multiconductor devices. Detailed Implementation

[0041] according to Figure 1 A first user 1 and a second user 2 are shown, capable of exchanging the symbol Sym via a common multi-conductor device 200 through electrical signal transmission. For this purpose, the first user 1 is connected to the second user 2 via the multi-conductor device 200 using a first electrical conductor 201, a second electrical conductor 202, and a third electrical conductor 203. For electrical signal transmission and thus the transmission of the symbol Sym, at least three series circuits P1, P2, and P3 operate in the first user 1. These series circuits are respectively composed of upper electronic switches A1, B1, and C1 and lower electronic switches A2, B2, and C3. The first electrical conductor 201 is connected between two switches A1 and A2 in a first series circuit P1, which includes a first upper electronic switch A1 and a first lower electronic switch A2. The second electrical conductor 202 or the third electrical conductor 203 is handled in a similar manner in the second series circuit P2 and the third series circuit P3. These electronic switches are, for example, designed as semiconductor components that can be integrated into a CMOS chip.

[0042] The symbol to be transmitted is Sym (see also...) Figure 2 The selection of the switch combination SK for electronic switches A1, B1, C1, A2, B2, C2 is encoded such that, by manipulating the corresponding electronic switches A1, B1, C1, an orderly selection of conductor pairs is performed from the set of electrical conductors 201, 202, 203 in the multi-conductor device 200. Current flows from the first user 1 through the current source Q via the correspondingly manipulated and thus closed upper electronic switches A1, B1, C1 into one of the electrical conductors 201, 202, 203, which then flows into the multi-conductor device 200 as the outgoing conductor HL.

[0043] In or outside of the second user 2, a terminating resistor network 501 is connected to the conductors 201, 202, 203 of the multi-conductor device 200, thereby connecting the current path SW for the current I flowing in the outgoing conductor HL to the other conductors 201, 202, 203 via the star point SP. This other conductor is then used by the first user 1 as the return conductor RL for the current I via closed lower electronic switches A2, B2, C2. To decode the transmitted symbol Sym, voltage levels AB, CB, CA are detected between the two conductors 201, 202, 203 in the second user 2, and the symbol Sym is recovered based on the different voltage levels between the conductors.

[0044] Measure the voltage between conductors 201, 202, and 203 in the terminating resistor network 501.

[0045] With the help of Figure 2 More detailed explanation Figure 1 The transmission principle described in the document is shown, and it demonstrates how the switch combination SK is applied to electronic switches A1, B1, C1, A2, B2, C2, and thus the symbol Sym = "BC" can be transmitted.

[0046] According to the present invention, signal paths are selectively established. The basic concept of this method is to sequentially select one or more conductor pairs from a set of multi-conductor devices 200 to encode transmitted information.

[0047] Figure 2 The diagram shows the first user 1 and its upper and lower electronic switches A1, B1, C1, A2, B2, C2, connected to a terminating resistor network 501, the voltage taps for voltage levels AB, BC, CA, CB, DB, AC, and the coding rules for the switch combination SK.

[0048] The upper electronic switches A1, B1, and C1 are designed to connect the electrical conductors 201, 202, and 203 to the first output terminal of the current source Q, and the lower switches A2, B2, and C2 are designed to connect the electrical conductors 201, 202, and 203 to the second output terminal of the current source Q.

[0049] Assuming the symbol Sym="BC" is to be transmitted to the multi-conductor device 200, according to the encoding rules of the encoding table, for the symbol Sym="BC" at the fourth position in the encoding table, the switch combination 1011 for "B" and the switch combination SK=0010 for "C" are derived. This encoding table is divided into switch combinations SK for upper electronic switches A1, B1, C1, D1 and switch combinations SK for lower electronic switches A2, B2, C2, D2. This is collectively referred to as control block 300, where upper electronic switches A1, B1, C1 subsequently form upper control block 301 and lower electronic switches A2, B2, C2 subsequently form lower control block 302.

[0050] The symbol Sym="BC" is taken from the encoding table, where column GP1 (positive gate 1) and column GN1 (negative gate 1) indicate the symbols "B" and "C" to be searched, respectively. Therefore, there are switch combinations SK for the upper control block 301 and for the lower control block 302. First, consider the upper control block 301. If the upper control block 301 receives switch combination SK=1011, this means that the first upper electronic switch A1 is operated with "1", the second upper electronic switch B1 is operated with "0", the third electronic switch C1 is again operated with "1", and the fourth electronic switch D1 is also again operated with "1". Since the electronic switches A1, B, C1, and D1 of the upper control block 301 have inverting inputs, only the second electronic switch B1 is operated in such a way that current I can flow from the current source Q into the multi-conductor device 200. Through the closed or operated second upper electronic switch B1, current I flows into the second conductor 202. The second conductor 202 serves as the outgoing conductor HL for the current I to another user or the terminating resistor network 501. The current I now flows into the terminating resistor network 501 and can return to the first user 1 via the current path SW through the third conductor 203 via a resistor connected in a star configuration there. Since the switch combination SK=0010 was selected for the lower control block 302 in the first user 1, the third lower electronic switch C2 is now manipulated in the lower control block 302 such that the current I can flow back to the current source Q.

[0051] To decode the transmitted information, for example in the second user 2 or elsewhere, voltage levels AB, BC, CA, etc., are generated and detected between two electrical conductors 201, 202, and 203 via a terminating resistor network 501. Based on the different voltage levels AB, BC, and CA between conductors 201, 202, and 203, the symbol Sym = "BC" can be recovered. Figure 2The diagram for a four-conductor system N=4 is shown in the middle as an example. This diagram for a corresponding four-conductor system N=4 has four nodes: node A, node B, node C, and node B. The dashed line from the diagram to the multi-conductor device 200 symbolizes taps used for voltage levels.

[0052] Voltage level AB can be measured between the first node A and the second node B. Here, the first node A is connected to the first conductor 201 and the second node B is connected to the second conductor 202. Voltage level BC can be measured between the second node B and the third node C, for which the third node C is connected to the third conductor 203. Since the fourth node D is connected to the fourth conductor 204, voltage level CD between the two corresponding conductors 203 and 204 can be measured between the third node C and the fourth node D. With the help of this diagram for a four-conductor system n=4, six different voltage levels can therefore be measured between nodes A, B, C, and D. A table with voltage levels as elements is shown on the right side of the diagram. By measuring the voltage levels between conductors 201, 202, 203, and 204, the receiving vector 402 is derived from these elements. Using the switch combination SK=1011 and SK=0010 described above, the voltages AB, BC, CD, DA, AC, and BD between conductors 201, 202, 203, and 204, as marked in the table, are obtained.

[0053] To find which symbol Sym is involved, in symbol decoder 450 (see...) Figure 8 In the process of determining the minimum and maximum values ​​of the sequence of elements in the received vector 402, the maximum and minimum values ​​are determined on the one hand and provided as binary sequences max and min, respectively. The maximum or minimum level is marked as a position according to the sequence of elements. In our example for the symbol "BC", the maximum value is obtained between the two nodes "BC" and the minimum value is obtained between the two nodes "CD". This yields the additional vectors "010000" and "001000". Using these two minimum-maximum vectors, the transmitted symbol Sym can then be read again from the decoding table.

[0054] With the help of Figure 3 The transmission is shown with the symbol Sym="CB". Because the switch combinations SK are now different, SK="1101" and SK="0100", in... Figure 3In the transmission symbol Sym="CB", another conductor 201, 202, 203, 204 is selected as the outgoing conductor HL and the return conductor RL. It is through the targeted selection of the outgoing and return conductors HL and RL that the symbol Sym can be encoded. By using the switch combination SK=1101, the third upper electronic switch C1 in the upper control block 301 is controlled to be on. Current I now flows through the outgoing conductor HL to the terminating resistor network 501 via the third conductor 203, and through the connection configuration of the terminating resistors, forms a current path SW returning via the second conductor 202, which serves as the return conductor RL. Since the second lower electronic switch B2 is now operated in the lower control block 302 based on the switch combination SK=0100, current I can flow back to the current source Q, thus closing the circuit. On the right side of the graph with nodes A, B, C, and D, the voltage levels are shown in a small table, and the maximum and minimum vectors can be read from the received vector 402.

[0055] With the help of Figure 4 This illustrates the principle used to increase the possible set of symbols. According to... Figure 4 A second current loop 122 is applied between the first user 1 and the second user 2 or the terminating resistor network 501 via a first current loop 121. The first user 1 has a first voltage source Q1 and a second voltage source Q2 for this purpose. The electronic switches in the corresponding upper control block 301 and lower control block 302 are dually designed here, with a separate electronic switch for each current source Q1, Q2. In the case where multiple current loops 121, 122 operate between the first user 1 and the second user 2 with different signal currents I1, I2, the following operation is performed to decode the symbol Sym: In the first step, a comparator network 400 is used to detect the voltage levels AB, BC, and CA between conductors 201, 202, 203, and 204, or between nodes A, B, C, and D. Later... Figure 6 and Figure 8 The comparator network 400 is described in more detail below. The detected voltage levels AB, BC, and CA are as follows: Figure 2 and Figure 3 The receiving vector 402 is obtained as described and from the voltage levels AB, BC, and CA, where the voltage levels AB, BC, and CA form the elements of the receiving vector 402.

[0056] In the second step, the received vector 402 is supplied to the symbol decoder 450, wherein, on the one hand, a maximum value determination is performed on the sequence of elements of the received vector 402, and on the other hand, a minimum value determination is performed, providing binary sequences Max and Min respectively. These binary sequences Max and Min (see also...) Figure 2 and Figure 3The maximum or minimum level is described as the position in the sequence.

[0057] In the third step, the received vector 402 is reduced, and the identified positions are eliminated. The reduced received vector 402 is then used to perform maximum and minimum value determination again.

[0058] According to Figure 4 The following advantages are gained from this process: each available conductor pair can be supplied with an additional current loop, thereby increasing the symbol set. By using currents of varying intensities, defined levels are also generated between the corresponding current conductors. These levels allow for incremental encoding and decoding from multiple currents, respectively, with the amount of (still) available conductors. In this way, significant amounts of information can be encoded in a small number of conductors with minimal energy consumption. Encoding and decoding can also be implemented using purely digital and simple circuitry.

[0059] Figure 5 A typical arrangement of transceivers 100 is shown, connected to a common multi-conductor device 200. In the context of this invention, a transceiver should be understood as a transmitter and receiver; advantageously, transceiver 100 is implemented using integrated circuits. This means that the transceiver includes a transmitter, a receiver, a resistor network, and corresponding control logic. Therefore, this invention describes a transceiver 100 that provides access to a multi-conductor system 200 shared with other users, and an encoding method for energy-efficiently transmitting information between two or more transceivers 100 via the multi-conductor device 200. This invention allows the construction of a bus-capable multi-conductor device 200 for information transmission using relatively simple components that can be integrated into a CMOS chip. This multi-conductor device achieves signal integrity characteristics and transmission rates similar to, for example, LVDS, but also has significantly more efficient information encoding with a less-than-proportional increase in current consumption. The following characteristics are crucial for this: 1) At each point in time, only a few current loops of varying intensities are applied to the conductor system.

[0060] 2) Since current loops can be clearly formed at the transmitting end and identified at the receiving end by means of their relative current intensity ratios, information encoding is performed by selecting individual conductors for the corresponding outgoing and return conductors for each individual current loop.

[0061] 3) The receiver can identify each current loop and determine its flow direction through a rapid iterative process. This only requires a simple pure binary request using a comparator.

[0062] 4) By using impedance-controlled and low-reflection line-guided techniques and appropriate termination, the transmission system can achieve the highest signaling rates with relatively low complexity and moderate current consumption.

[0063] Therefore, the encoding method corresponds to the method for electrically transmitted symbols (Sym) claimed herein. Transceiver 100 here directly accesses multi-conductor device 200 and provides an interface for manipulation by an information processing system, in the form of symbol streams in the receiving and transmitting directions, i.e., transmit symbol stream 102 and output symbol stream 103. Control signal 101 is used, for example, to switch between transmit operation, receive operation, termination, and / or dynamic termination. Transceiver 100 includes a control unit having symbol encoder 110, current source module 120, and a corresponding number of control blocks 300 (see...). Figure 6 ).exist Figure 6 A more detailed description is provided in [the text]. Figure 5 The transceiver 100 is schematically illustrated in the figure. A particular advantage of this method is that transmitted information is encoded by the orderly selection of one or more conductor pairs from a set of multi-conductor devices 200, where each individual electrical conductor is used to guide one or more signal currents. When using multiple conductor pairs, the signal currents can be of different magnitudes and thus in a reliable anti-interference relationship with each other.

[0064] Figure 6 A block diagram of transceiver 100 is shown. Symbol encoder 110 receives the transmitted symbol stream 102 as an input parameter and additionally receives control signals 101. Symbol encoder 110 sends a first current loop control vector 111 to control block 300. Furthermore, symbol encoder 110 is capable of sending a second current loop control vector 112 to another control block 300 and, depending on the design, can send up to the xth current loop control vector 11x to another control block 300. The first current loop 121, the second current loop 122, or the xth current loop 12x is then generated by the corresponding current source module 120. The corresponding control block 300, as shown in... Figure 2 and Figure 3 As described, a corresponding signal current is transmitted via a multi-conductor device 200, wherein the voltage level of the electrical conductors of the multi-conductor device 200 is measured in a receiver via a comparator network 400. Therefore, the transceiver 100 has a sign encoder 480 (see [reference]). Figure 9 The control unit, one or more coupled current sources, and a corresponding number of control blocks 300, each control block having an upper control block 301 and a lower control block 302. For receive operation, a comparator network 400 with a symbol decoder 450 is used.

[0065] With the help of Figure 8 The symbol decoder 450 is described in more detail. The symbol decoder 450 produces the output symbol stream 103.

[0066] The unit consisting of a coupled current source (i.e., current source module 120) and a current distributor (i.e., control block 300 and its upper control block 301 and lower control block 302) is called a current loop driver. This current loop driver allows directed currents of defined magnitudes to be applied to the multi-conductor device 200 in various ways. Here, it is possible to freely select not only the outgoing conductor but also the return conductors HL and RL from the N conductors of the multi-conductor device 200 for the current I. Control block 300 (see...) Figure 7 It is possible to form a “differential tuple” using at least n=3 electrical conductors for decoding or encoding. In contrast to the differential pairs known from LVDS technology, it is now possible to encode or decode more information because multiple conductor paths can now be selected via the control circuitry described.

[0067] In contrast to differential pairs, "differential pairs" operate multiple conductor paths via a control circuit, namely control block 300, which manipulates a group of half-bridges to establish a current loop through the selected conductor pair and then takes into account the current intensity. During operation, it should be ensured that lateral currents are eliminated by simultaneously selecting the same line on both the high-side and low-side drivers (upper control block 301 and lower control block 302).

[0068] The minimum structure of the transmission channel consists of two transceivers 100, a multi-conductor device 200, and a star termination 503. Termination is necessary because it forms a current path or current trail SW for the applied current loop, and only the voltage drop across the termination resistor R results in a detectable voltage level difference. In its simplest case, this can be a suitable, persistent, and effective resistor network. However, it is also advantageous to optionally integrate the termination unit 500 into the transceiver 100. This allows for targeted switching of the termination resistor R along the multi-conductor device 200. This enables targeted responses to reflections when operating in extended bus scenarios with many distributed users or transceivers 100. Furthermore, the signal shape can be targeted by briefly switching all or some of the bus lines terminated. For this purpose, the termination unit 500 can be targeted via the termination switch 502 located therein and the termination vector 104 from the symbol encoder 110.

[0069] according to Figure 7Control block 300 is schematically shown. The x-th current loop vector 11x is directed to the upper control block 301 on one side and to the lower control block 302 on the other. The upper control block 301 can also be referred to as a "high-side one hot-encoder" and the lower control block 302 can be referred to as a "low-side one hot-encoder". The upper control block 301 can close and open the upper switch 303 of the half-bridge. The lower control block 302 can open and close the lower switch 304. For seven lines N=7, there are seven upper switches 303 and seven lower switches 304 available. Each conductor 201, ..., 207 is therefore associated with an upper switch 303 or a lower switch 304. The first conductor 201 corresponds to node A and the seventh conductor 207 corresponds to node G in diagrams A, B, C, D, E, F, G.

[0070] Figure 8 A comparator network 400 is shown, in which twenty-one comparators are available in a seven-conductor system N=7. A set of comparators is obtained that can be assigned to the far neighbor 3D. Furthermore, a set of comparators that can be assigned to the intermediate neighbor 2D is obtained, and a set of comparators that can be assigned to the nearest neighbor 1D is obtained. Looking at a graph A, B, C, D, E, F, G with seven nodes, the far neighbor 3D always refers to the distance between two nodes by three edges, the intermediate neighbor 2D refers to the distance between two nodes by two edges, and the nearest neighbor 1D refers to nodes that are direct neighbors.

[0071] Receive operation and symbol recognition

[0072] By utilizing twenty-one comparators to compare voltage levels, the symbol decoder 450 is able to provide an output symbol stream 103. During receive operation, the comparator network 400 is active and continuously detects relative ratios of voltage levels in the multi-conductor device 200; these ratios are then mapped into a digital receive vector 402. The symbol decoder 450 derives the output symbol stream 103 from this receive vector 402. In a preferred embodiment for maximum performance, the comparator network 400 includes a comparator 401 for each unique conductor pair in the multi-conductor device 200. However, it is also possible to reduce the number of required comparators by sparsifying the comparator network 400. This limits the size of the receive vector 402 and the complexity of the symbol decoder 450 and results in a reduction in the number of possible symbols, which limits the system's information throughput. When sparsifying the comparator network 400, it should be noted that asymmetric sparsification leads to a loss of interchangeability tolerances of the lines in the conductor system 200.

[0073] For the unsparsed and fully meshed comparator network 400, symbol decoding in the symbol decoder 450 can be performed in a multi-stage iterative process. For this purpose, the first discriminator 461, operating as a minimum-maximum conductor pair discriminator (see...),... Figure 9 The system identifies conductor pairs in the multi-conductor device 200 that have corresponding maximum and minimum relative levels and returns this information as conductor pair information 451, 454, and 457. In a preferred embodiment, a simple multi-input AND logic gate (see [link to implementation]) is used. Figure 14 This is sufficient; it detects whether the line level is always greater than or less than the levels of all other logic lines. Error signals 452, 455, and 458 are always activated when it is not always exactly identifying a maximum and exactly a minimum value. This may be the case when the bus is stationary or when multiple current loops 12X with the same current intensity are active. In this case, it is impossible to explicitly assign values ​​to each loop.

[0074] according to Figure 9 A block diagram of the symbol encoder 480 is shown. To provide a reduced receive vector 453 or even a further reduced receive vector 456 from the receive vector 402, a first discriminator 461, a second discriminator 462, and a third discriminator 463 are configured, with the aid of which a multi-level iterative process is performed. According to... Figure 8 The symbol decoder 450 thus provides twenty-one values, which are checked by the first discriminator 461, and a first error signal 452 is provided if the minimum and maximum values ​​are not identified. The minimum and maximum value evaluation enables the first conductor pair information 451 to be provided to the symbol encoder 480 via the first discriminator 461. The multi-conductor device 200 with n=7 is reduced to a multi-conductor device with n=5 via the first reducer 471. The reduced receive vector 453 is provided via the first reducer 471. This reduced receive vector 453 is provided to the second discriminator 462 as an input parameter for the minimum-maximum value evaluation. The second discriminator 462 is then able to provide the second conductor pair information 454 to the symbol encoder 480. In the next step, the reduced receive vector 453 is converted into a further reduced receive vector 456 via the second reducer 472. The further reduced receive vector 456 is then checked for minimum and maximum values ​​by the third discriminator 463, which provides the third conductor pair information 457 to the symbol encoder 480. If the first discriminator 461, the second discriminator 462, and / or the third discriminator 463 detects an error in the minimum-maximum value evaluation, a first error signal 452, a second error signal 455, and / or a third error signal 458 are respectively provided to the symbol encoder 480.

[0075] After the first step, it is now known which conductor pair provides the outgoing and return conductors for the current loop with the maximum loop current. With this information, these conductors can now be removed from the receiving network for sparsification during preparation for the second step. Figure 9 In the example, this involves a multi-conductor device 200 with n=7 and a total of L=3 current loops. After the first step of identifying the first current loop via nodes B and F, nodes A, C, D, E, and G remain. In the same step, the comparators connected to the now-removed conductors B and F become redundant and can be removed from the receive vector 402. The block “Reduction of Receive Vector and Network” removes these redundant bits, resulting in a new reduced receive vector 453, which is reduced to a new length of ten bits, now corresponding to the receive vector of a five-conductor system with n=5. Accordingly, the outgoing and return conductors of the remaining maximum current loop can now be found using the additional “Minimum-Maximum Conductor Pair Discriminator”. The reduced receive vector is again calculated based on the obtained conductor pair information 454 when preparing for the final iteration. This vector now corresponds to the vector of a three-conductor system with nodes A, C, and E with n=3.

[0076] The symbol encoder 480 knows the possible diversity of conductor pairs of information 452, 445, and 458 (A, B, and C) and can thus easily obtain the received symbols. An error symbol can be generated accordingly whenever one of the error signals 452, 455, or 458 is activated. For decoding the output symbol stream 103 from the received vector 402, synchronization logic is not required initially, and therefore, in principle, a clock recovery method can be applied to the output symbol stream 103. For this purpose, for example, the least significant error signal can be used selectively, in this example, the third error signal 458. A feasible approach is for the transmitter to periodically interrupt the third current loop control vector 113, thereby inducing a clock signal in the third error signal 458.

[0077] Figure 10 The termination unit 500 is shown as a block diagram. The termination unit 500 receives a termination vector 104 as an input parameter. The termination vector 104 can correspondingly control the termination switch 502, causing the termination resistor network 501 to be connected to the corresponding electrical conductors 201, ..., 207. The termination switch 502 is assigned to nodes A, ..., G of the corresponding graph.

[0078] use Figure 11A diagram is shown for different numbers of electrical conductors in a multi-conductor device 200. For a three-conductor system n=3, a diagram with three nodes A, B, C is used to determine voltage levels AB, BC, CA. For a multi-conductor device 200 with n=4 conductors, a diagram with four nodes A, B, C, D is used, where seven voltage levels have been obtained. For a multi-conductor device 200 with n=5 electrical conductors, a diagram with five nodes A, B, C, D, E is used, where ten voltage levels AB, BC, CA... are now obtained. If the multi-conductor device 200 has n=7 electrical conductors, twenty-one comparison positions are obtained, and twenty-one voltage levels are obtained accordingly. Solid arrows between nodes in the diagram represent the nearest neighbor 1D, dashed arrows represent the middle neighbor 1D, and dotted connecting arrows represent the far neighbor 3D.

[0079] Figure 12 shows a decoding table for different multi-conductor devices 200, which extends to... Figure 12A , 12B 12C and 12D. When creating interactive embodiments of decoding for different designs of multi-conductor devices, tables are generated in which it is not possible or clear enough to draw the accompanying drawings representing the invention on a single page. In particular, the relationships between the various method steps are shown. In this case, the drawings are divided into four pages (12A, 12B, 12C, 12D). The complete figures or drawings can be combined by placing the four drawing pages side by side.

[0080] The leftmost label indicates the number of conductors and the number of currents applied to the system. For example, three conductors and one current, or four conductors and one current, or four conductors and two currents, or seven conductors and one current, or seven conductors and two currents, or seven conductors and three currents. The corresponding symbols to be decoded are also recorded in a column. Above the table with encoding and decoding instructions, the principle is shown according to... Figure 9 The diagram is drawn in a long, thin shape to symbolize where each step is performed.

[0081] Parameters, variants and performance

[0082] The basic parameters of this invention are N, the number of conductors in the multi-conductor device 200, and L, the number of current loops that can be applied simultaneously. For example, the leftmost column "4 conductors, 2 currents" means N=4 and L=2. Accordingly, four conductors and two current loops are used. These parameters are taken into consideration in all the accompanying drawings by showing the corresponding adaptations or presenting implementation examples with specific parameters.

[0083] The symbol set can be estimated from the degrees of freedom in selecting the circuit. In a multi-conductor device 200 with N conductors, a total of N is provided for the application of the first current loop 121. (N-1) different feasible schemes are extracted from the transmitted symbol stream 102 by the symbol encoder 110 via the current loop control vector 111. The flow of the second current loop 122 can now be selected from the reduced set of N-2 conductors according to the same scheme, such that (N-2) current loop control vectors 112 open up. The feasible solution space is (N-3). The current loop control vector 112 is also extracted from the transmitted symbol stream 102 by the symbol encoder 110. This method can now be continued for other current loops, provided that the remaining set of conductors is large enough.

[0084] In general, according to this specification, for the method of applying L current loops to N lines, a feasible scheme space consisting of a total of N! / (N-2L)! symbols is obtained. This is possible because, for example, when current loops 121, 122, ..., 12X are implemented with strictly monotonically decreasing current intensities, complete information about which current flows through which pair of outgoing and return conductors is contained in the receiving vector 402.

[0085] In a preferred implementation, the symbol encoder 110 also ensures that at any given time, each line 20X in the multi-conductor device 200 is selected by at most one control block 300, where overlap of current loops 121, 122, ..., 12X is excluded. Thus, the diversity of possible voltage levels in the multi-conductor device 200 is limited to a maximum of 2. L+1 different amplitudes have a positive impact on the anti-interference capability during operation.

[0086] Encoding and decoding conventionally begin with the current loop 121 carrying the maximum current and continue strictly in a decreasing sequence of current amplitudes 122, ..., 12X. In a preferred implementation, the current source module 120 is accordingly configured to ensure this. Therefore, even with multiple current loops, the detected current path can be correctly assigned using only the level difference in the multi-conductor device 200, further increasing information density. Decoding can also be performed using current loops of equal strength or overlapping current loops when accepting symbol set reduction.

[0087] Figure 13 illustrates the reduction of the receive vector from an eight-conductor system (n=8) to a two-conductor system (n=2). Figures 13A, 13B, and 13C should be viewed side-by-side for this purpose. According to... Figure 13A Assume an eight-conductor system with diagrams A, B, C, D, E, F, G, and H, where N=8. The minimum and maximum voltage levels are displayed in this diagram or in the multi-conductor device 200 using a discriminator. Assume the symbol "CF" has been transmitted. Therefore, the maximum value is identified for C and the minimum value for F. After reducing from N=8 to N=6, the identified nodes C and F are omitted.

[0088] With the help of Figure 13B Further reductions are shown, resulting in diagrams A, B, C, D, E, and F in the existing six-conductor system N=6, on which the maximum and minimum voltage levels MIN and MAX can be identified. Now, in the exemplary symbol transmission, it is determined that the maximum value MAX is now derived from node F (originally H) and the minimum value MIN is now derived from node D (originally E). This produces the symbol "CFHE". When transforming from a six-conductor system N=6 with six conductors to a four-conductor system N=4 or a corresponding reduction according to the method, nodes D and F are omitted. The receive vector has now been reduced to the equivalent of the four-conductor system and diagrams A, B, C, and D exist; see [reference needed] for this. Figure 13C Here, the minimum and maximum values ​​are used to decode another symbol, which is now derived as the complete received symbol "CFHEBG". Finally, the four-conductor system N=4 is reduced to a two-conductor system N=2.

[0089] In summary, the initial point is a conductor system with eight lines, which is exemplarily reduced for three reductions with randomly selected maximum-minimum pairs at each level. The mapping of lines, i.e., the mutual mapping of nodes (lines) from the corresponding larger conductor system to the corresponding reduced conductor system, is shown as an association on the right side of the diagram. According to... Figure 13A Line mapping diagram 603 shows the assignment of lines from N=8 lines to N=6 lines. Reduced mapping diagram 604 shows the assignment of bits or positions of receive vector 402 to bits or positions of reduced receive vector 453.

[0090] At each level, two lines are labeled MIN and MAX in the complete diagram, where the numbered edges (1 to 28) correspond to the bit numbers on the right side of the reduction mapping diagram 604. These two lines, MIN and MAX, are the decoding results of exemplary identifications for the corresponding level, and these decoding results now need to be reduced from the receive vector 402. The names of the identified symbols are listed in boxes (“symbols”), which are extended in each level by the newly identified conductor pair. Figure 13A When N=8: "CF", Figure 13B When N=6: "CFHE", Figure 13B When N=4: "CFHEBG".

[0091] The goal of the reduction is to find a complete graph of size (N-2) again in the next decoding stage of the symbol encoder 480 while maintaining the conductor sequence according to the line mapping diagram 603, so that the entire process can be iteratively performed on an increasingly smaller "virtual" conductor system from now on. Each of the N conductors here corresponds to a node in the complete N graph, and each bit in the receive vector 402 corresponds to a directed edge between two nodes. The graph is reduced by two nodes at each stage, which are equivalent to the identified conductors of the conductor pairs detected in that stage. Conductors or nodes are identified using minimum and maximum values. Accordingly, all edges (bits) originating from or reaching these nodes (conductors) are eliminated. Figure 13A In sections B and C, the conductors or nodes involved are circled and crossed out with an X to indicate elimination or reduction.

[0092] The remaining bits or positions also appear in the new graph and are assigned to the corresponding bits or positions of the new reduced receive vector 453 according to the line mapping diagram 603 shown, so that the receive vector correctly represents the original relationship of the starting graph. It should be noted that a reversal can occur if the conductor sequences are swapped (edge ​​direction reversed). This occurs, for example, when transforming from bit 23 (“GB”) of receive vector 402 in an eight-conductor system N=8 to bit 14 (“BE”) of reduced receive vector 453 in a six-conductor system N=6, because the corresponding mapping specifies the mapping relationship G -> E and B -> B, i.e., “GB” -> “EB”, but the reduced graph specifies the opposite edge direction “BE”.

[0093] According to this regulation, digital circuits can be derived using design methods known to those skilled in the art, such as by using multiplexers and inverters.

[0094] Figure 14 The diagram illustrates possible implementations of the comparators. In a four-conductor system n=4 with diagrams A, B, C, and D, there are six different feasible schemes for measuring voltage levels. Accordingly, six comparators must be integrated into the circuit. These six comparators are represented by comparator network 400. The voltage levels AB, BC, CA, ... between conductors 201, 202, 203, 204 or between nodes are detected by comparator network 400, and the detected voltage levels AB, BC, CA, ... are assigned as elements to receiver vector 402. Receiver vector 402 can be formed in such a way that, conventionally, each conductor is sampled sequentially, and the relative ratios of voltage levels in this conductor system are also detected sequentially in receiver vector 402. One convention, for example, can be referred to in diagram theory as follows: Each conductor is represented by nodes arranged on a circular line. In a four-conductor system, there would be nodes A, B, C, and D. Edges between nodes can be drawn starting from node A in a clockwise direction. If the starting node is reached again, diagonal or lateral connections can be drawn as edges. Accordingly, the voltage levels between nodes or between conductors AB, BC, CD, DA, AC, and BD are obtained as edges. Possible receive vectors are as follows: Receive vector = (+1 Volt, +2 Volt, -1 Volt, +1 Volt, +1 Volt, +1 Volt).

[0095] Maximum and minimum values ​​are determined on the received vector using a simple AND operation. This determination can be achieved using simple AND gates. If the maximum value cannot be explicitly determined, a first error signal 452 is generated. Otherwise, the output is executed, and when one of the AND gates outputs a signal, it is known which line produced the maximum value. The minimum value is determined similarly.

[0096] Similar to the reduction illustrated in Figure 13, using Figures 15 to 20 The diagram illustrates a reduction from a seven-conductor system starting with diagrams A, B, C, D, E, F, and G. In a seven-conductor system with N=7, there exists a diagram with twenty-one edges. This means that twenty-one voltage levels need to be evaluated. The minimum and maximum values ​​can always be detected in receiver vector 402 using a minimum-maximum evaluation.

[0097] use Figure 15 The diagram shown has twenty-one (0 to 20) connections 600, which are shown as edges or interpreted as voltage levels in the diagram. After the first reduction, utilizing... Figure 16 This illustrates the transition from a seven-conductor system (N=7) to a five-conductor system (N=5). The mapping of nodes from the previous larger graph to the current smaller, shrunk graph can be seen in assignment table 601 (which performs the mapping of nodes from the previous larger graph to the current smaller graph). This shows which nodes in the larger graph are now eliminated in the shrunk graph.

[0098] Furthermore, according to Figure 17 This section describes the reduction of the receiver vector 402 from N=7 in a seven-conductor system to N=5 in a five-conductor system. The reduced receiver vector 453 is derived from receiver vector 402. The reduction from 21 bits to 10 bits has been achieved. Based on... Figure 17 The table illustrates this. Edge BC in the seven-conductor system becomes edge A'B' in the five-conductor system. This is achieved by reducing... Figure 18 This generates a five-conductor system N=5; here, the minimum-maximum determination must also be performed again. This is in Figure 19The diagram also shows, here again, the association table 602 for the mapping from a five-conductor system N=5 to a three-conductor system n=3 (see...). Figure 20 ).

[0099] use Figure 21 This describes how to combine the transmitting unit TX, receiving unit RX, and termination unit 500 into a transceiver circuit. This combination allows for implementation as a simple, scalable IP block for application in a semiconductor component 50. An IP block (from the English Intellectual Property Core, also known as an IP core) in microelectronics refers to a reusable prefabricated functional block of a chip design (in the sense of a block diagram or circuit design). This chip design thus implements the method steps according to the invention. A distinction is made between soft IP cores and hard IP cores: soft IP cores exist in the form of source code in a specialized hardware specification language, such as Verilog or VHDL. They can also exist as a textual description of a circuit diagram as a netlist already synthesized by the manufacturer. In this case, it is called a firm-IP core. A hard IP core is a block with a pre-completed layout. Therefore, users can hardly or cannot change the IP and it is process-bound. To protect methodological secrecy, users typically only receive a black-box presentation of the purchased hard IP core. Preferably, the IP block is implemented using complementary metal-oxide-semiconductor (CMOS) technology. The abbreviation CMOS refers to the name of a semiconductor structure element, in which both P-channel and N-channel MOSFETs are used on a common substrate.

[0100] according to Figure 22 Another embodiment of the transceiver unit or transceiver circuit and semiconductor component 50 is disclosed. It can operate for a four-conductor system N=4 with one current source, or it can operate for a four-conductor system N=4 with two current sources to apply different current loops.

[0101] Figure 23 Possible bus topologies are shown. A common feature of all bus topologies is that at least two users are connected to the conductor system, particularly the multi-conductor device 200 (bus). For data transmission according to this method and the invention, at least one three-conductor system is required. At least one user acting as a transmitter and a resistor network acting as a receiver must be connected. This means that in the bus system, at least one terminating resistor must exist in the conductor system (bus), for example, referred to as a mid-terminal (or Thevenin equivalent).

[0102] according to Figure 23 From left to right, the diagram shows a three-conductor system, a four-conductor system, a seven-conductor system, and finally a three-conductor system with an external termination unit.

[0103] Figure 24This illustrates the parallel operation of different conductor systems. It demonstrates that a multi-conductor device with N=7 conductors can connect seven-conductor systems, four-conductor systems, and even three-conductor systems, each with its own transceiver. Therefore, users with different numbers of conductors can operate on a common conductor system (bus). As an advantage, the common large conductor system (bus) is divided into multiple smaller subbuses. Users on independent subbuses can transmit simultaneously without collisions. Users on the main bus can participate in all transmission paths, including those on the subbuses.

[0104] use Figure 25 The text discusses termination in parallel operation. For example, termination can be assigned to a sub-bus. Sufficient termination for users on the main bus can be alternative to individual terminations on the main bus by connecting the midpoint of the sub-bus terminations (see dashed line).

[0105] use Figure 26 This describes dynamic termination. Termination via bus terminating resistors can also be integrated into the user and activated when needed.

[0106] use Figure 27 This presents a hybrid operation of the already known LVDS (Low Voltage Differential System) and the novel MLVDS (Multi-Line Low Voltage Differential System) according to the present invention. The novel semiconductor components can be connected to existing LVDS connections. The transceiver can operate as an LVDS-RX receiver on any conductor pair. An LVDS-TX transmitting unit can be connected to each current loop in the transceiver.

[0107] This invention enables the construction of multi-conductor devices with strong bus capabilities for information transmission using simple, CMOS chip-integrable components. These multi-conductor devices achieve signal integrity characteristics and transmission rates similar to, for example, LVDS, but also have significantly more efficient information encoding with a smaller increase in current consumption.

[0108] Therefore, the following characteristics are crucial: - At each point in time, only a few current loops of varying intensities are applied to the conductor system.

[0109] Since current loops can be clearly formed at the transmitting end and identified at the receiving end by means of their relative current intensity ratios, information encoding is performed by selecting individual conductors for the corresponding outgoing and return conductors for each individual current loop.

[0110] The receiver can identify each current loop and determine its flow direction through a rapid iterative process. This only requires a simple, pure binary request using a comparator.

[0111] - By using impedance-controlled and low-reflection line-guided techniques and appropriate termination, the transmission system is essentially able to achieve the highest signaling rates with relatively low complexity and modest current consumption.

[0112] Other points and advantages are as follows: In a multi-conductor device (bus), at least three conductors are used for data transmission.

[0113] A star impedance (termination) allows current to flow between all conductors.

[0114] Current is applied symmetrically to the bus through any two conductors.

[0115] By using the termination impedance, the current can be detected as the potential difference between the conductors of the bus.

[0116] The information is encoded in the sequential selection of conductors.

[0117] The binary determiner between all conductors allows for decoding symbols from conductor potentials.

[0118] When two or more conductors are not in use, the same conductor potential will occur, which will result in 0 or 1 on the corresponding determiner. Nevertheless, the symbol can still be explicitly assigned.

[0119] The interchange of conductor selection between the high and low sides reverses the potential in the conductor system and thus also reverses the receive vector that constitutes the decision state of the comparator.

[0120] via from to Individual and Freely select from unused conductors to obtain One possible symbol.

[0121] Each available conductor pair can be used to apply an additional current loop.

[0122] By using currents of different intensities, defined levels are also obtained between the conductors carrying the currents.

[0123] These allow for incremental encoding and decoding of multiple currents in the (still) available conductor quantities.

[0124] In this way, significant amounts of information can be encoded in a small number of conductors with minimal energy consumption.

[0125] Encoding and decoding are performed using purely digital and simple circuits.

[0126] Multiple current loops of varying strengths can be achieved not only by using different current sources, but also by doubling the number of high-side and low-side transistors that share a common current source. Figure 21 ) The transmitting unit (Tx), receiving unit (Rx), and termination can be integrated into the transceiver circuit.

[0127] The termination is dynamically enabled as needed to avoid excessively low bus impedance.

[0128] This allows it to be implemented as a easily expandable IP block for use in integrated circuit applications.

[0129] At least one terminating resistor in a conductor system (bus), for example as an intermediate termination (Thevenin equivalent). Figure 26 .

[0130] Users with different numbers of conductors running on a common conductor system (bus), Figure 24 .

[0131] Divide a common large conductor system (bus) into multiple smaller subbuses.

[0132] Users on independent subbuses can send simultaneously without conflict.

[0133] The main bus user can participate in all transmission paths (including sub-buses).

[0134] Termination can be assigned to a sub-bus.

[0135] For users on the main bus, sufficient termination can be provided, alternative to separate termination on the main bus, also achieved by connecting the midpoint of the sub-bus termination (see dashed line). Figure 25 , Figure 26 .

[0136] Termination can also be integrated into the user and activated when needed.

Claims

1. A system for transmitting symbols (Sym) between a first user (1) and a second user (2) via a common multi-conductor device (200), the system having: First electrical conductor (201). The second electrical conductor (202), and Third electrical conductor (201, 202, ..., 207). The first user (1) includes a symbol encoder (110), a current source module (120), and a control block (300), wherein, The control block (300) has an upper control block (301) and a lower control block (302). The upper control block (301) is designed to close and open the upper switch (303) relative to the first output terminal of the current source module (120), and the lower control block (302) is designed to open and close the lower switch (304) relative to the second output terminal of the current source module (120). The upper switch (303) has at least three upper electronic switches (A1, B1, C1), and the lower switch (304) has at least three lower electronic switches (A1, B2, C2). At least three series circuits (P1, P2, P3) are provided, each consisting of an upper electronic switch (A1, B1, C1) and a lower electronic switch (A2, B2, C2). Electrical conductors (201, 202, 203) are connected between the upper electronic switches (A1, B1, C1) and the lower electronic switches (A2, B2, C2) to the corresponding series circuits (P1, P2, P3). The current source module (120) is connected to the series circuits (P1, P2, P3). Its features are, The symbol encoder (110) is designed to provide a current loop control vector (111) for the control block (300), wherein the control block (300) is designed to switch electronic switches (A1, B1, C1, A2, B2, C2) by means of the current loop control vector (111) having a switch combination (SK) for electronic switches (A1, B1, C1, A2, B2, C2), and to allow current to flow into the connected electrical conductors (201, 202, ..., 207) by means of the switch combination (SK) for electronic switches (A1, B1, C1, A2, B2, C2), and to allow current to flow into the connected electrical conductors (201, 202, ..., 207) by means of the switch combination (SK), The symbol encoder (110) is designed to determine the current loop control vector (111) such that the symbol (Sym) to be transmitted is determined by orderly selecting conductor pairs from a set of electrical conductors (201, 202, 203) originating from the multi-conductor device (200), and the symbol to be transmitted is encoded by the determination, wherein the conductor pair includes one of the electrical conductors (201, 202, 203) as the outgoing conductor of the current from the first user (1) to the second user (2). The electrical conductors of the HL and another of the electrical conductors (201, 202, 203) serve as the return conductor (RL), wherein a termination unit (500) is also provided, wherein the symbol encoder (110) is designed to provide a termination vector (104) for the termination unit (500), wherein the termination unit (500) is designed to connect the termination resistor network (501) to the electrical conductors (201, 202, 203) of the multi-conductor device (200) by means of a termination switch (502). The second user (2) has a comparator network (400) designed to detect voltage levels (AB, BC, CA) between two electrical conductors (201, 202, 203) for decoding the symbol (Sym), wherein the encoded symbol (Sym) is contained in the different voltage levels (AB, BC, CA) between the electrical conductors (201, 202, 203).

2. The system according to claim 1, wherein, The symbol encoder (110) is designed to provide multiple current loop control vectors (111, 112, 113, ..., 11x). The control block (300) is designed to operate the common multiconductor device (200) using multiple current loops (121, 122, ..., 127).

3. The system according to claim 2, wherein, The control block (300) and / or the current source module (120) are designed to apply different signal currents (I1, I2, ..., Ix) to each current loop (121, 122, ..., 127).

4. The system according to any one of claims 1 to 3, wherein, The comparator network (400) is designed to assign the detected voltage levels (AB, BC, CA) as elements to the receiving vector (402).

5. The system according to claim 4, having a symbol decoder (450) designed to receive the received vector (402) and perform maximum and minimum value determination on a sequence of elements of the received vector (402), and the symbol decoder is further designed to provide binary sequences (MAX, MIN) respectively, in which the maximum level or the minimum level is marked as a position in the sequence.

6. The system according to claim 5, comprising: First discriminator (461). Second discriminator (462) First reducer (471). Second reducer (472). The first discriminator (461) is designed as a minimum-maximum conductor pair discriminator, and is further designed to receive the reception vector (402) and detect conductor pairs in the multi-conductor device (200) that have the maximum and minimum relative levels, respectively, and the first discriminator is also designed to provide the detection result as first conductor pair information (451). The first discriminator (461) is connected to the first reducer (471) and the first discriminator is designed to provide a reduced reception vector (453) for the information (451) using the first conductor. The second discriminator (462) is designed as an additional minimum-maximum conductor pair discriminator, and is further designed to receive the reduced reception vector (453) and detect conductor pairs with the maximum and minimum relative levels respectively in the multi-conductor device (200) having the detected reduced conductor pairs, and the second discriminator is also designed to provide the detection result as second conductor pair information (454). The second discriminator (462) is connected to the second reducer (472) and the second discriminator is designed to provide a further reduced reception vector (456) to the information (451) using the second conductor.

7. A method for electrically transmitting a symbol (Sym) from a first user (1) to a second user (2), the first user and the second user being connected via a common multi-conductor device (200), the multi-conductor device having at least a first electrical conductor (201), a second electrical conductor (202) and a third electrical conductor (203), wherein, - In the first user (1), at least three series circuits (P1, P2, P3) are operated, each consisting of an upper electronic switch (A1, B1, C1) and a lower electronic switch (A2, B2, C2), wherein electrical conductors (201, 202, 203) are connected between the upper electronic switch (A1, B1, C1) and the lower electronic switch (A2, B2, C2) in the respective series circuit. The upper electronic switches (A1, B1, C1) connect or disconnect the electrical conductors (201, 202, 203) from the first output terminal of the current source (Q), and the lower electronic switches A2, B2, C2 connect or disconnect the electrical conductors 201, 202, 203 from the second output terminal of the current source (Q). Its features are, - The symbol (Sym) to be transmitted is encoded by selecting conductor pairs in an orderly manner from the set of electrical conductors (201, 202, 203) originating from the multi-conductor device (200) and by selecting a switch combination (SK) for electronic switches (A1, B1, C1, A2, B2, C2), wherein current (I) flows from the first user (1) through the closed upper electronic switch (A1, B1, C1) into one of the electrical conductors (201, 202, 203) as the outgoing conductor (HL) into the multi-conductor device (200). - Wherein, the terminating resistor network (501) is connected to the electrical conductors (201, 202, 203) of the multi-conductor device (200), which opens a current path (SW) to the other electrical conductors (201, 202, 203) through the current (I) flowing in the outgoing conductor (HL), and the other electrical conductors (201, 202, 203) are then used as the return conductor (RL) for the current (I) from the first user (1) via the closed lower electronic switch (A2, B2, C2). - In the second user (2), in order to decode the symbol (Sym), the voltage level (AB, BC, CA) is detected between two electrical conductors (201, 202, 203), wherein the symbol (Sym) is retrieved from the different voltage levels (AB, BC, CA) between the electrical conductors (201, 202, 203).

8. The method according to claim 7, wherein, The multi-conductor device (200) operates using a number of conductors (n) of electrical conductors (201, 202, ..., 207), wherein current loops (121, 122, ..., 127) are formed between the first user (1) and the second user (2) by means of electronic switches (A1, B1, C1, A2, B2, C2), electrical conductors (201, 202, ..., 207) and the terminating resistor network (501), wherein, in order to further encode the symbol (Sym) to be transmitted, a selection set (L) of current loops (121, 122, ..., 127) is determined from the number of conductors (N) of electrical conductors (201, 202, ..., 20x) and the symbol set is increased by this determination.

9. The method according to claim 8, wherein, Different signal currents (I1, I2, ..., Ix) of different magnitudes are applied to each current loop (121, 122, ..., 127) of the selection set (L), and the symbol set is further increased by this application.

10. The method according to any one of claims 7 to 9, wherein, The voltage levels (AB, BC, CA) between electrical conductors (201, 202, 203) are detected using a comparator network (400), wherein the detected voltage levels (AB, BC, CA) are assigned as elements to the receiving vector (402).

11. The method according to claim 10, wherein, The received vector (402) is supplied to the symbol decoder (450), wherein a maximum value determination is performed on the one hand and a minimum value determination is performed on the other hand for the sequence of elements of the received vector (402), and binary sequences (MAX, MIN) are provided respectively, in which the maximum level or the minimum level is marked as the position in the sequence.

12. The method according to any one of claims 9 to 11, wherein, In the case of multiple current loops (121, 122, ..., 127) with different signal currents (I1, I2, ..., Ix) operating between the first user (1) and the second user (2), in order to decode the symbol (Sym). a) In the first step, the voltage levels (AB, BC, CA) between the electrical conductors (201, 202, 203) are detected using a comparator network (400), and the detected voltage levels (AB, BC, CA) are assigned as elements to the receiving vector (402). b) In the second step, the received vector (402) is supplied to the symbol decoder (450), wherein a maximum value determination is performed on one hand and a minimum value determination is performed on the other hand for the sequence of elements of the received vector (402), and binary sequences (MAX, MIN) are provided respectively, in which the maximum or minimum level is marked as the position in the sequence. c) In the third step, the receiving vector (402) is reduced by the position detected in the second step, wherein a reduced receiving vector (453) is determined, and the process in the first step is continued using the reduced receiving vector (402) until the reduced receiving vector (453) or another reduced receiving vector (456) corresponds to a multi-conductor device (200) with a conductor number N=3.

13. A semiconductor component (50) is designed as a line driver for electrically transmitting symbols (Sym) between a first user (1) and a second user (2), the first user and the second user being connected via a common multiconductor device (200) having at least a first electrical conductor (201), a second electrical conductor (202) and a third electrical conductor (201, 202, ..., 207). Its features are, The semiconductor component is designed to implement the method according to any one of claims 7 to 12.

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