Anti-interference acquisition circuit of cloud data acquisition unit

Abstract

The utility model relates to the technical field of cloud data acquisition units, and discloses an anti-interference acquisition circuit of a cloud data acquisition unit, which comprises an analog-to-digital conversion circuit, a voltage reference source circuit and a voltage stabilizing circuit, the analog-to-digital conversion circuit comprises an analog-to-digital conversion chip U2, the voltage reference source circuit comprises a voltage reference chip U1 and an amplifier U30, and the voltage stabilizing circuit comprises an analog-to-digital conversion chip U2. A pin 6 of the amplifier U30 is connected to a pin 19 of the analog-to-digital conversion chip U2, and the voltage stabilizing circuit comprises a voltage stabilizing chip U3. Through the design that the analog-to-digital conversion circuit, the voltage reference source circuit and the voltage stabilizing circuit are additionally arranged in the collector, high-frequency noise, electromagnetic radiation and interference signals generated in the data collection process can be effectively filtered out; the influence of an external interference source on the data collection work of the collector is reduced, the data collection precision of the collector is improved, and normal and stable operation of a data collection system program is guaranteed.

Description

Technical Field

[0001] The utility model relates to the technical field of cloud data collectors, in particular to an anti-interference collection circuit for a cloud data collector. Background Art

[0002] A cloud data collector is a tool used to collect and store various data in a cloud environment. It can capture, monitor, and record data from cloud platforms, servers, network devices, and applications on a regular or real-time basis. Cloud data collectors are often used to monitor and analyze performance indicators, log data, security events, etc. in a cloud environment to help users understand and optimize the operation and security of their cloud services.

[0003] After searching, the patent with application number CN201711255480.6 discloses a data acquisition cloud service platform, including a computer, a data network connected to the computer, the data network is connected to several cloud service units, the cloud service unit includes: a cloud server connected to the data network, a communication module and an intelligent mobile terminal connected to the cloud server, the communication module is connected to the reminder unit, and the intelligent mobile terminal includes a data acquisition unit, an identity recognition unit and a wireless communication unit. The data acquisition cloud service platform of the present invention realizes data sharing by connecting multiple cloud servers thereto through a data network, wherein the computer can also analyze and count the collected data; in addition, the cloud server can identify and record the data acquisition information, and when the data acquisition information is different from the data pre-stored in the data network, a reminder message can be sent to the reminder unit, and the location can also be quickly located.

[0004] Some current cloud data collectors collect data by collecting analog input signals and switch input signals, converting the collected analog signals into digital signals, and then performing software filtering. Then, according to the calibrated parameters, the digital signals are transformed into meaningful physical values, and other processing processes can be performed to achieve data collection without loss and mixed access to multiple types of sensors.

[0005] However, during the data collection process, there are external interference sources that affect the collector, such as some high-frequency noise, electromagnetic radiation and interference signals, which affect the data collection accuracy of the collector and the normalization and stabilization of the collection system program. Therefore, we need to propose an anti-interference collection circuit for the cloud data collector. Utility Model Content

[0006] The purpose of the utility model is to provide an anti-interference acquisition circuit for a cloud data collector. By adding an analog-to-digital conversion circuit, a voltage reference source circuit and a voltage stabilizing circuit in the collector, the high-frequency noise, electromagnetic radiation and interference signals generated in the data acquisition process can be effectively filtered out, the influence of external interference sources on the data acquisition work of the collector can be reduced, and the data acquisition accuracy of the collector can be improved, so as to ensure the normal and stable operation of the data acquisition system program, so as to solve the problems raised in the above-mentioned background technology.

[0007] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: an anti-interference acquisition circuit of a cloud data collector, comprising an analog-to-digital conversion circuit, a voltage reference source circuit and a voltage stabilizing circuit, wherein the voltage reference source circuit and the voltage stabilizing circuit are both electrically connected to the analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprises an analog-to-digital conversion chip U2, and a resistor R44 is connected between the connection terminals of the 20th and 22nd pins and the 23rd pin of the analog-to-digital conversion chip U2;

[0008] The voltage reference source circuit includes a voltage reference chip U1 and an amplifier U30, wherein pin 6 of the amplifier U30 is connected to pin 19 of the analog-to-digital conversion chip U2, and a resistor R100 is connected between the connection terminals of pins 5 and 6 of the voltage reference chip U1 and pin 3 of the amplifier U30; the voltage stabilizing circuit includes a voltage stabilizing chip U3 and a capacitor C101 connected to pin 19 of the analog-to-digital conversion chip U2, and a capacitor C66 is connected between pins 1 and 3 of the voltage stabilizing chip U3.

[0009] Preferably, a resistor R41 is connected to pin 2 of the analog-to-digital conversion chip U2, a resistor R42 is connected to pin 28 of the analog-to-digital conversion chip U2, and a resistor R43 is connected to pin 27 of the analog-to-digital conversion chip U2.

[0010] Preferably, pin 24 of the analog-to-digital conversion chip U2 is connected to a 5V power supply, pin 25 of the analog-to-digital conversion chip U2 is connected to a 3.3V power supply, and pins 9 and 10 of the analog-to-digital conversion chip U2 are connected and then grounded.

[0011] Preferably, pin 3 of the amplifier U30 is also connected to capacitors C62 and C63 which are arranged in parallel and grounded, pin 2 of the amplifier U30 is connected to pin 6, and pin 7 of the amplifier U30 is connected to capacitor C100, and one end of the capacitor C100 is connected to pin 24 of the analog-to-digital conversion chip U2.

[0012] Preferably, a capacitor C58 is connected between pin 1 and pin 2 of the voltage reference chip U1, a capacitor C57 is connected between the connection terminals of pin 2, pin 3 and pin 4 of the voltage reference chip U1, and pin 4 of the voltage reference chip U1 is connected to pin 24 of the analog-to-digital conversion chip U2.

[0013] Preferably, a capacitor C65 is connected between pins 1 and 2 of the voltage stabilizing chip U3, and two ends of the capacitor C65 are connected in parallel with an inductor L1 and a capacitor C64 connected in series, and the connection terminals of the inductor L1 and the capacitor C64 are connected to a 6V voltage.

[0014] Compared with the prior art, the beneficial effects of the utility model are:

[0015] The utility model can effectively filter out high-frequency noise, electromagnetic radiation and interference signals generated in the data collection process by adding an anti-interference circuit in the collector, reduce the influence of external interference sources on the data collection work of the collector, and improve the data collection accuracy of the collector, thereby ensuring the normal and stable operation of the data collection system program. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of the analog-to-digital conversion circuit of the utility model;

[0017] Figure 2 It is a schematic diagram of the structure of the voltage reference source circuit of the utility model;

[0018] Figure 3 It is a structural schematic diagram of the voltage stabilizing circuit of the utility model. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0020] See also Figure 1-3 The utility model provides a technical solution: an anti-interference acquisition circuit of a cloud data collector, including an analog-to-digital conversion circuit, a voltage reference source circuit and a voltage stabilizing circuit, wherein the voltage reference source circuit and the voltage stabilizing circuit are both electrically connected to the analog-to-digital conversion circuit, and the analog-to-digital conversion circuit includes an analog-to-digital conversion chip U2, the model of the analog-to-digital conversion chip U2 is AD7193BRUZ, and a resistor R44 is connected between the connection terminals of the 20th and 22nd pins and the 23rd pin of the analog-to-digital conversion chip U2, both ends of the resistor R44 are grounded, and the 4th pin of the analog-to-digital conversion chip U2 is grounded;

[0021] The AD7193 is a low noise, complete analog front end for high precision measurement applications. It integrates a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC). The on-chip low noise gain stage means that small signals can be directly input to the ADC. It can be configured as four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer can enable multiple channels at the same time, and the AD7193 performs conversions on each enabled channel in sequence, simplifying communication with the device. The on-chip 4.92MHz clock can be used as the clock source for the ADC; alternatively, an external clock or crystal oscillator can be used. The output data rate of the analog-to-digital conversion chip U2 can vary from 4.7Hz to 4.8kHz.

[0022] The voltage reference source circuit includes a voltage reference chip U1 and an amplifier U30, wherein pin 6 of the amplifier U30 is connected to pin 19 of the analog-to-digital conversion chip U2, and a resistor R100 is connected between the connection terminals of pins 5 and 6 of the voltage reference chip U1 and pin 3 of the amplifier U30; the voltage stabilizing circuit includes a voltage stabilizing chip U3 and a capacitor C101 connected to pin 19 of the analog-to-digital conversion chip U2, and a capacitor C66 is connected between pins 1 and 3 of the voltage stabilizing chip U3.

[0023] The model of the voltage reference chip U1 is MAX6070. The voltage reference source circuit can provide a stable voltage output to provide a reference voltage for other circuits or devices. It can provide a high-precision and low-drift voltage output to ensure the stability and stability of the circuit. It can also filter out noise and interference signals in advance to improve the circuit's anti-interference and anti-noise performance.

[0024] Pin 2 of the analog-to-digital conversion chip U2 is connected to a resistor R41 , pin 28 of the analog-to-digital conversion chip U2 is connected to a resistor R42 , and pin 27 of the analog-to-digital conversion chip U2 is connected to a resistor R43 .

[0025] Pin 24 of the analog-to-digital conversion chip U2 is connected to a 5V power supply, pin 25 of the analog-to-digital conversion chip U2 is connected to a 3.3V power supply, and pins 9 and 10 of the analog-to-digital conversion chip U2 are connected and then grounded.

[0026] Pin 3 of the amplifier U30 is also connected to capacitors C62 and C63 which are arranged in parallel and grounded. Pin 2 of the amplifier U30 is connected to pin 6. Pin 7 of the amplifier U30 is connected to capacitor C100, and one end of the capacitor C100 is connected to pin 24 of the analog-to-digital conversion chip U2.

[0027] A capacitor C58 is connected between pin 1 and pin 2 of the voltage reference chip U1, a capacitor C57 is connected between the connection terminals of pin 2, pin 3 and pin 4 of the voltage reference chip U1, and pin 4 of the voltage reference chip U1 is connected to pin 24 of the analog-to-digital conversion chip U2.

[0028] A capacitor C65 is connected between pins 1 and 2 of the voltage stabilizing chip U3, and two ends of the capacitor C65 are connected in parallel with an inductor L1 and a capacitor C64 connected in series, and the connection terminals of the inductor L1 and the capacitor C64 are connected to a 6V voltage.

[0029] The voltage regulator chip U3 is ME6118, which is a high-precision, low-noise, LDO regulator that can provide an output current of more than 1A with a maximum voltage difference of 1.3V / 1A, an output current of no more than 1A, an operating voltage of 2.5V-18V, and an on-chip trimming adjustment of the reference / output voltage accuracy within ±2%. Internal protection functions include output current limiting, safe operating area compensation, and thermal shutdown.

[0030] The analog-to-digital conversion circuit also includes a capacitor C59, a capacitor C60 and a capacitor C61 connected in parallel, the capacitor C59 is connected to pin 25 of the analog-to-digital conversion chip U2, and the connection terminals of the capacitors C60 and C61 are connected to pin 24 of the analog-to-digital conversion chip U2.

[0031] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An anti-interference acquisition circuit for a cloud data collector, characterized in that: It includes an analog-to-digital conversion circuit, a voltage reference source circuit and a voltage stabilizing circuit, wherein the voltage reference source circuit and the voltage stabilizing circuit are both electrically connected to the analog-to-digital conversion circuit, and the analog-to-digital conversion circuit includes an analog-to-digital conversion chip U2, and a resistor R44 is connected between the connection terminals of the 20th and 22nd pins and the 23rd pin of the analog-to-digital conversion chip U2; The voltage reference source circuit includes a voltage reference chip U1 and an amplifier U30, wherein pin 6 of the amplifier U30 is connected to pin 19 of the analog-to-digital conversion chip U2, and a resistor R100 is connected between the connection terminals of pins 5 and 6 of the voltage reference chip U1 and pin 3 of the amplifier U30; the voltage stabilizing circuit includes a voltage stabilizing chip U3 and a capacitor C101 connected to pin 19 of the analog-to-digital conversion chip U2, and a capacitor C66 is connected between pins 1 and 3 of the voltage stabilizing chip U3.

2. The anti-interference acquisition circuit of a cloud data collector according to claim 1, characterized in that: Pin 2 of the analog-to-digital conversion chip U2 is connected to a resistor R41 , pin 28 of the analog-to-digital conversion chip U2 is connected to a resistor R42 , and pin 27 of the analog-to-digital conversion chip U2 is connected to a resistor R43 .

3. The anti-interference acquisition circuit of a cloud data collector according to claim 1, characterized in that: Pin 24 of the analog-to-digital conversion chip U2 is connected to a 5V power supply, pin 25 of the analog-to-digital conversion chip U2 is connected to a 3.3V power supply, and pins 9 and 10 of the analog-to-digital conversion chip U2 are connected and then grounded.

4. The anti-interference acquisition circuit of a cloud data collector according to claim 1, characterized in that: Pin 3 of the amplifier U30 is also connected to capacitors C62 and C63 which are arranged in parallel and grounded. Pin 2 of the amplifier U30 is connected to pin 6. Pin 7 of the amplifier U30 is connected to capacitor C100, and one end of the capacitor C100 is connected to pin 24 of the analog-to-digital conversion chip U2.

5. The anti-interference acquisition circuit of a cloud data collector according to claim 1, characterized in that: A capacitor C58 is connected between pin 1 and pin 2 of the voltage reference chip U1, a capacitor C57 is connected between the connection terminals of pin 2, pin 3 and pin 4 of the voltage reference chip U1, and pin 4 of the voltage reference chip U1 is connected to pin 24 of the analog-to-digital conversion chip U2.

6. The anti-interference acquisition circuit of a cloud data collector according to claim 1, characterized in that: A capacitor C65 is connected between pins 1 and 2 of the voltage stabilizing chip U3, and two ends of the capacitor C65 are connected in parallel with an inductor L1 and a capacitor C64 connected in series, and the connection terminals of the inductor L1 and the capacitor C64 are connected to a 6V voltage.

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