Semiconductor device

Abstract

A semiconductor device relates to the field of design and manufacture of semiconductor devices and comprises a channel layer and a barrier layer, a source electrode, a drain electrode and a grid electrode are all located on the barrier layer, and the grid electrode is structurally characterized in that a first P-type III-V group compound semiconductor layer is located on the barrier layer; the III-V group compound semiconductor oxide layer is located on the first P-type III-V group compound semiconductor layer; the second P-type III-V group compound semiconductor layer is located on the III-V group compound semiconductor oxide layer; the top metal is on the second P-type III-V group compound semiconductor layer. The method has the advantage that the excessive etching phenomenon can be effectively prevented in the manufacturing process.

Description

Technical Field

[0001] The utility model relates to a semiconductor device with improved structure, in particular to a semiconductor device with improved etching thickness uniformity. Background Art

[0002] See also Figure 1 , as a semiconductor device, Figure 1 FIG. 1 is a schematic diagram of a p-type gate structure of an existing enhancement mode field effect transistor (GaN HEMT). For the sake of clarity, Figure 1 The source and drain of the field effect tube are omitted in the subsequent drawings of the utility model. The P-type III-V compound semiconductor layer 4 is in direct contact with the barrier layer 2 or the cap layer 3 to form a depletion layer; for the top, the P-type III-V compound semiconductor layer 4 is in contact with the top metal 8 to form a Schottky contact or an Ohmic contact depending on the different work functions of the metal.

[0003] The invention patent application with the publication number CN113540228A discloses a semiconductor device, wherein a similar Figure 1 In the etching process of the enhancement mode field effect transistor shown in the figure, due to the uneven thickness of the wafer after epitaxial growth and the need to etch the thicker P-type III-V compound semiconductor layer 4, the cap layer 3 or the barrier layer 2 will eventually be severely over-etched, thereby affecting the density of the two-dimensional electron gas below. Therefore, it is necessary to improve the gate structure of the semiconductor device to prevent over-etching during the manufacturing process of the semiconductor device, improve the uniformity of the thickness after wafer etching, and thus improve the gate withstand voltage performance. Summary of the invention

[0004] The main purpose of the utility model is to provide a semiconductor device with an improved gate structure.

[0005] To achieve the above-mentioned purpose, the semiconductor device provided by the utility model includes a channel layer; a barrier layer, located on the channel layer; a source, a drain and a gate, all located on the barrier layer, and the source and the drain are respectively located on both sides of the gate; the structure of the gate is as follows: a first P-type III-V group compound semiconductor layer, located on the barrier layer; a III-V group compound semiconductor oxide layer, located on the first P-type III-V group compound semiconductor layer; a second P-type III-V group compound semiconductor layer, located on the III-V group compound semiconductor oxide layer; a top metal, the top metal is located on the second P-type III-V group compound semiconductor layer.

[0006] A further solution is to provide a cap layer between the barrier layer and the first P-type III-V group compound semiconductor layer.

[0007] Compared with the prior art, the utility model inserts a Group III-V compound semiconductor oxide layer into the P-type Group III-V compound semiconductor layer, that is, a barrier layer composed of the Group III-V compound semiconductor oxide layer is formed in the P-type Group III-V compound semiconductor layer, which plays the role of an etching barrier layer during the etching process of the P-type Group III-V compound semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of a conventional semiconductor device;

[0009] Figure 2 It is a structural schematic diagram of an embodiment of the utility model.

[0010] Wherein: channel layer 1; barrier layer 2; cap layer 3; P-type III-V group compound semiconductor layer 4; first P-type III-V group compound semiconductor layer 5; III-V group compound semiconductor oxide layer 6; second P-type III-V group compound semiconductor layer 7; top metal 8.

[0011] The present invention is described in detail below in conjunction with the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0012] See also Figure 2 As mentioned above, in order to focus on the improvements of the utility model, Figure 2 The source and drain electrodes on both sides of the gate are omitted. The gate structure of the semiconductor device is the same as that of the prior art, and is provided with a channel layer 1, a barrier layer 2, and a cap layer 3 from bottom to top, that is, the barrier layer 2 is located on the channel layer 1, and the cap layer 3 is located on the barrier layer 2. The improvement over the prior art is that the P-type III-V compound semiconductor layer 4 of the prior art is divided into a first P-type III-V compound semiconductor layer 5 and a second P-type III-V compound semiconductor layer 7, and a III-V compound semiconductor oxide layer 6 is inserted between the two, that is, the first P-type III-V compound semiconductor layer 5 is located on the cap layer 3, the III-V compound semiconductor oxide layer 6 is located on the first P-type III-V compound semiconductor layer 5, the second P-type III-V compound semiconductor layer 7 is located on the III-V compound semiconductor oxide layer 6, and the top metal 8 is located on the second P-type III-V compound semiconductor layer 7.

[0013] Among them, the material selection and processing technology of the channel layer 1, the barrier layer 2, the cap layer 3, the P-type III-V compound semiconductor layer 4 and the top metal 8 can be completely implemented according to the existing technology. The material of the III-V compound semiconductor layer 6 is aluminum nitride (AIN) or gallium nitride (GaN) or aluminum gallium nitride (AlGaN); the material of the III-V compound semiconductor oxide layer 7 is aluminum oxynitride (AlON) or gallium oxynitride (GaON) or aluminum gallium nitride oxide (AlGaON), and the constructed stack 5 and the semiconductor devices involved in the construction can also be implemented according to traditional processes.

[0014] Other Implementations

[0015] For some semiconductor devices, the cap layer 3 can be omitted when implementing the utility model, that is, the first P-type III-V group compound semiconductor layer 5 is directly located on the barrier layer 2, which can also improve the gate withstand voltage and reliability.

Claims

1. A semiconductor device comprising: a channel layer; a barrier layer, located on the channel layer; A source electrode, a drain electrode and a gate electrode are all located on the barrier layer, and the source electrode and the drain electrode are respectively located on two sides of the gate electrode; It is characterized in that: the structure of the gate is as follows a first P-type III-V compound semiconductor layer, located on the barrier layer; a III-V group compound semiconductor oxide layer, located on the first P-type III-V group compound semiconductor layer; a second P-type III-V compound semiconductor layer, located on the III-V compound semiconductor oxide layer; A top metal is located on the second P-type III-V group compound semiconductor layer.

2. The semiconductor device according to claim 1, wherein: A cap layer is further disposed between the barrier layer and the first P-type III-V group compound semiconductor layer.

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