Voltage-resistant IGBT device

Abstract

The utility model discloses a voltage-resistant IGBT (Insulated Gate Bipolar Transistor) device, which comprises a substrate, a first electrode, a second electrode, a third electrode and a fourth electrode, the collector layer is formed at the bottom of the substrate; the emitter layer is formed on the top of the substrate; the emitter layer is formed on the substrate, the gate layer is formed on the substrate and is insulated and separated from the emitter layer, and the semiconductor device is characterized in that the gate layer comprises two pieces of interconnected gate polycrystalline silicon, a floating region is formed between the two pieces of interconnected gate polycrystalline silicon, and a gate resistor is arranged between a connecting region of the two pieces of interconnected gate polycrystalline silicon and the substrate. The potential difference of the gate layer and a coupling electric field between the gate trenches are formed by connecting the polycrystalline silicon and the floating region, so that Miller capacitance is increased, the switching-on speed is reduced, and the impact of oscillation is alleviated. And a grid resistor capable of controlling the current and voltage of the grid layer and buffering the impact of the grid voltage is arranged below the connecting polycrystalline silicon, so that the stability of the device is improved.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductors, and in particular relates to a voltage-resistant IGBT device. Background Art

[0002] The current structure of the IGBT device is to set three longitudinally spaced gate trenches on the substrate layer and fill the gate polysilicon in the gate trenches to form the G pole, and form the metal layer E pole on the substrate layer and the metal layer C pole under the substrate, respectively. Figure 1 As shown. However, under the condition of small current turn-on test, the turn-on waveform of this type of IGBT device has serious oscillation. Due to the fast turn-on speed, the oscillation amplitude of the gate voltage of the IGBT device exceeds the gate threshold voltage or gate withstand voltage, which will cause the E and G poles of the turned-off IGBT device to be easily turned on or the gate oxide to be broken down and damaged, and there may even be a serious tube explosion problem. Utility Model Content

[0003] The utility model aims to provide a voltage-resistant IGBT device in view of the technical problem that the existing IGBT device may be abnormally turned on or gate oxide may be damaged by breakdown when the device is turned on quickly with a small current.

[0004] The voltage-resistant IGBT device of the utility model comprises:

[0005] a substrate;

[0006] a collector layer formed at the bottom of the substrate;

[0007] an emitter layer formed on top of the substrate;

[0008] A gate layer is formed on the substrate and is insulated from the emitter layer, wherein the gate layer includes two interconnected gate polysilicon layers, a floating region is formed between the two interconnected gate polysilicon layers, and a gate resistor is provided between the connection region of the two interconnected gate polysilicon layers and the substrate.

[0009] Preferably, the floating region starts from the lower edge of the body region of two interconnected gate polysilicon and extends in the longitudinal direction beyond the bottom of the gate polysilicon.

[0010] Preferably, the gate layer comprises:

[0011] Two gate trenches spaced apart longitudinally along the substrate;

[0012] Two gate polysilicons are respectively filled in the two gate trenches;

[0013] A connecting polysilicon has two ends connected to the tops of the two gate polysilicons respectively, and the gate resistor is provided between the connecting polysilicon and the substrate.

[0014] Preferably,

[0015] A vertical oxide dielectric layer is provided between the gate polysilicon and the inner wall of the gate trench;

[0016] A lateral oxide dielectric layer is provided between the connecting polysilicon and the substrate, and the gate resistor is located between the lateral oxide dielectric layer and the connecting polysilicon to increase the thickness of the oxide dielectric layer.

[0017] Preferably,

[0018] An insulating isolation layer (ILD) is disposed between the gate layer and the emitter layer.

[0019] Preferably, the substrate has, from bottom to top:

[0020] an anode layer, the collector layer being deposited below the anode layer;

[0021] a dielectric layer formed on the anode layer;

[0022] A source region layer formed on the dielectric layer;

[0023] a body region layer formed on the source region layer;

[0024] A P-type N-type interphase layer is formed on the body layer, and the connection region of the two interconnected gate polysilicon is located on the P-type N-type interphase layer and is separated by the gate resistor and the lateral oxide dielectric;

[0025] The gate trench passes through the body region layer from the P-type and N-type interlayer in a vertical direction to the source region layer, and the floating region is formed on the source region layer.

[0026] Preferably,

[0027] The source region layer is an n-type source region layer;

[0028] The floating region is a p-type floating region;

[0029] The body region layer is a p-type body region.

[0030] Preferably, the P-type and N-type interphase layers include:

[0031] Two first n+ type doped regions are respectively located between the two gate trenches and close to the gate trenches;

[0032] Two second n+ type doped regions, located on both sides of the two gate trenches and close to the gate trenches;

[0033] a first p+ type doped region, located between the two first n+ type doped regions;

[0034] The two second p+ type doping regions are located beside the two second n+ type doping regions.

[0035] The connection region of the two interconnected gate polysilicon layers is located on the first p+ type doping region and the two first n+ type doping regions and is separated by the gate resistor and the lateral oxide dielectric layer.

[0036] The collector layer and the emitter layer are both made of deposited metal.

[0037] The positive and progressive effects of the utility model are:

[0038] 1) The utility model reduces a middle gate trench, increases the two gate trenches PITCH located on the side, and interconnects the tops of the two gate trenches, and forms a floating area 61 below the interconnected area. The interconnected polysilicon 43 and the floating area 61 form a potential difference of the gate layer 40 and a coupling electric field between the gate trenches 41, thereby increasing the Miller capacitance, reducing the turn-on speed, and mitigating the impact of oscillation.

[0039] 2) The utility model also has a gate resistor 45 built in below the connection polysilicon 43 to control the current and voltage of the gate layer and mitigate the impact of the gate voltage, and a thick oxide dielectric layer 46 is added below the gate resistor 45 to prevent the Miller capacitance Crss from being too large, thereby improving the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of an IGBT device in the prior art;

[0041] Figure 2 It is a schematic structural diagram of a voltage-withstand IGBT device of the utility model;

[0042] Figure 3 A schematic diagram of the process steps of the voltage-withstand IGBT device of the utility model; DETAILED DESCRIPTION

[0043] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Figure 2The schematic diagram of the structure of the IGBT device for coping with small current failure improvement of the utility model includes a substrate 10, a collector layer 20 at the bottom of the substrate 10, an emitter layer 30 at the top of the substrate 10, and a gate layer 40 arranged on the substrate 10. In addition, a gate resistor 45, a P-type N-type interphase layer 50, a body region layer 60, a floating region 61, a source region layer 70, a dielectric layer 80, and an anode layer 90 are arranged on the substrate 10 and between the gate layer 40 and the collector layer 20 from top to bottom.

[0045] The emitter layer 30 is located at the upper end of the substrate 10 and is formed by depositing metal. An insulating isolation layer 31 is also disposed between the emitter layer 30 and the gate layer 40 . The insulating isolation layer 31 can separate the gate layer 40 from the emitter layer 30 .

[0046] The gate layer 40 is located below the emitter layer 30, and the gate layer contains two symmetrical gate trenches 41 located on the side, and a connecting polysilicon 43 laid on the substrate to connect the tops of the two symmetrical gate trenches 41 on the side. Figure 2 As shown, two gate trenches 41 are symmetrically embedded in the source layer 70. Compared with the existing three gate trenches, it has a larger PITCH. And the two gate trenches 41 on the side are also filled with gate polysilicon 42. The connecting polysilicon 43 directly interconnects the two gate polysilicons 42, so the connecting polysilicon 43 is laid below the insulating isolation layer 31 and on the middle area of ​​the P-type N-type interphase layer 50, thereby increasing the corresponding area between the gate layer and the collector layer. Due to the potential difference formed between the connecting gate polysilicon 43 and the P-type N-type interphase layer 50, the oscillation amplitude of the impact current or voltage at the moment of small current opening can be effectively reduced, thereby alleviating the breakdown and damage of the gate oxide, and effectively preventing the Miller capacitance Crss from being too large, thereby improving the response efficiency and stability of the device. Of course, a longitudinal oxide dielectric layer 44 is also formed between the filled gate polysilicon 42 and the inner wall of the gate trench 41 to isolate the gate trench 41 from the gate polysilicon 42. A very thin lateral oxide dielectric layer 46 is also grown between the connection polysilicon 43 and the substrate 10. A gate resistor 45 is also built between the connection polysilicon 43 and the P-type N-type interphase layer 50. The gate resistor 45 is located on the lateral oxide dielectric layer 46. Due to the existence of the gate resistor 45, when a small current is turned on, the current and voltage of the gate layer can be controlled and the impact of the gate voltage can be mitigated. The setting of the gate resistor 45 is also equivalent to thickening the thickness of the lateral oxide dielectric layer 46.

[0047] The structure of the P-type N-type interphase layer 50 is as follows: the periphery of the gate trench 41 is an n+ type doping region, and the other regions are p+ type doping regions, so that the P-type N-type interphase layer 50 is alternately provided with a second p+ type doping region 52, a second n+ type doping region 54, a first n+ type doping region 53, a first p+ type doping region 51, a first n+ type doping region 53, a second n+ type doping region 54, and a second p+ type doping region 52 from left to right. The gate trench 41 is symmetrically arranged between the first n+ type doping region 53 and the second n+ type doping region 54.

[0048] The body layer 60 is located below the P-type and N-type interphase layer 50 , and is, for example, P-Body or P.

[0049] The floating region 61 is located below the body region layer 60 and is also sandwiched between the two gate trenches 41, for example, a P-type floating region, i.e., a p-dummy structure. The floating region 61 extends longitudinally from the lower edge of the body region 60 between the two interconnected gate polysilicon layers and exceeds the bottom of the gate polysilicon 42. The existence of the floating P region 61 isolates the two gate trenches 41, resulting in an increase in the electric field coupling between the two gate trenches 41 and between the gate trench 41 and the floating region 61, which in turn increases the Miller capacitance Crss and reduces the turn-on speed.

[0050] The source region layer 70 is located below the body region layer 60 and the floating region 61 , and is, for example, an n-type source region layer.

[0051] The dielectric layer 80 is located directly below the source region layer 70 and is, for example, of n+ doping type.

[0052] The anode layer 90 is located below the dielectric layer 80 and is, for example, p+ doped.

[0053] The collector layer 20 is located below the anode layer 90 and is formed by depositing metal.

[0054] In this example, Figure 3 The following is a specific implementation process of the IGBT device for improving low current failure of the utility model:

[0055] Step ①, grow a hard mask and pattern it, inject n+ ions into the source layer 70 at two locations by IMP and diffuse them, and remove the hard mask.

[0056] Step ②, grow and pattern a hard mask, inject and diffuse P dummy to form a floating region 61, and remove the hard mask.

[0057] Step ③, grow a hard mask and pattern it, diffuse the p+ ions by IMP, thereby forming a P-type N-type interphase layer 50 as a whole. Remove the hard mask.

[0058] Step ④, grow a hard mask and pattern it, and implant ions to form a P-Body layer 60. Remove the hard mask.

[0059] Step ⑤, the hard mask layer is grown and patterned, the top opening of the gate trench 41 is etched and the gate trench 41 is etched. The hard mask is removed.

[0060] Step ⑥, growing a gate oxide layer, filling polysilicon, and etching back to form a gate. Step ⑥ includes: growing a gate oxide layer in the gate trench etched in step ⑤ and then filling it with polysilicon. Since the deposited polysilicon covers the entire plane, a mask is used to retain the polysilicon between the two gate trenches during etching back, forming a structure in which the two gate trenches are connected by connecting polysilicon 43.

[0061] Step ⑦, the front N+ source region and the dielectric layer 80 are implanted, and after the implantation, the insulating isolation layer 31 is deposited, the emitter contact hole is etched, and the metal is deposited to form the emitter layer 30.

[0062] Step ⑧: The back side of the substrate 10 is thinned to a final thickness, and anode ions are implanted on the back side to form an anode layer 90. Metal is deposited below the anode layer 90 to form a collector layer 20.

[0063] The utility model not only reduces a middle gate trench, but also increases the two gate trenches PITCH located on the side, and interconnects the tops of the two gate trenches, and forms a floating P region 61 below the interconnection. The interconnected polysilicon 43 and the P-type floating region 61 form a potential difference of the gate layer 40 and a coupling electric field between the gate trenches 41, thereby increasing the Miller capacitance, reducing the turn-on speed, and mitigating the impact of oscillation. A gate resistor 45 that can control the current and voltage of the gate layer and mitigate the impact of the gate voltage is also built in below the polysilicon 43, and a thick oxide dielectric layer 46 is added below the gate resistor 45 to prevent the Miller capacitance Crss from being too large, thereby improving the stability of the device. Specific embodiment:

[0065] Taking a 1200V IGBT as an example, the epitaxial layer doping concentration is 8.0E+15, the P-Body AL injection concentration is 3E+13, the critical maximum opening width of the gate trench is 1.0um, the depth of the gate trench is 2.0um, and the thickness of the gate oxide dielectric layer is N+ region (i.e., first conductivity type active region 103) B, 165KeV, 3E+15, P+ active region (i.e., second conductivity type active region 105) region As, 60KeV, 5E+15, P-Body As, 90KeV, 4E+14, P-floating doped region As, 90KeV, 3E+15

[0066] The utility model is described in detail above in conjunction with the embodiments of the drawings. A person skilled in the art can make various variations of the utility model according to the above description. Therefore, some details in the embodiments should not constitute a limitation of the utility model, and the utility model shall be protected within the scope defined by the attached claims.

Claims

1. A withstand voltage IGBT device, the withstand voltage IGBT device comprising: a substrate; a collector layer formed at the bottom of the substrate; an emitter layer formed on top of the substrate; A gate layer is formed on the substrate and is insulated from the emitter layer, wherein the gate layer includes two interconnected gate polysilicon layers, a floating region is formed between the two interconnected gate polysilicon layers, and a gate resistor is provided between the connection region of the two interconnected gate polysilicon layers and the substrate.

2. The withstand voltage IGBT device according to claim 1, characterized in that The floating region starts from a lower edge of the body region between two interconnected gate polysilicons and extends in a longitudinal direction beyond the bottom of the gate polysilicons.

3. The withstand voltage IGBT device according to claim 1, characterized in that The gate layer comprises: Two gate trenches are spaced apart from each other along the substrate in the longitudinal direction; Two gate polysilicons are respectively filled in the corresponding gate trenches; A connecting polysilicon is located on the substrate, two ends of the connecting polysilicon are respectively connected to the tops of the two gate polysilicons, and the gate resistor is provided between the connecting polysilicon and the substrate.

4. The withstand voltage IGBT device according to claim 3, characterized in that A vertical oxide dielectric layer is provided between the gate polysilicon and the inner wall of the gate trench; A lateral oxide dielectric layer is provided between the connecting polysilicon and the substrate, and the gate resistor is located between the lateral oxide dielectric layer and the connecting polysilicon to increase the thickness of the oxide dielectric layer.

5. The withstand voltage IGBT device according to claim 1, characterized in that An insulating isolation layer is provided between the gate layer and the emitter layer.

6. The withstand voltage IGBT device according to claim 4, characterized in that The substrate has, from bottom to top, the following: an anode layer, the collector layer being deposited below the anode layer; a dielectric layer formed on the anode layer; A source region layer formed on the dielectric layer; a body region layer formed on the source region layer; A P-type N-type interphase layer is formed on the body layer, and the connection region of the two interconnected gate polysilicon is located on the P-type N-type interphase layer and is separated by the gate resistor and the lateral oxide dielectric; The gate trench passes through the body layer from the P-type and N-type interlayer to the source layer in a vertical direction, and the floating region is formed in the source layer.

7. The withstand voltage IGBT device according to claim 6, characterized in that The source region layer is an n-type source region layer; The floating area is a p floating area; The body region layer is a p-type body region.

8. The withstand voltage IGBT device according to claim 6, characterized in that The P-type N-type interphase layer comprises: Two first n+ type doped regions are respectively located between the two gate trenches and close to the gate trenches; Two second n+ type doped regions, located on both sides of the two gate trenches and close to the gate trenches; a first p+ type doped region, located between the two first n+ type doped regions; Two second p+ type doping regions are located beside the two second n+ type doping regions; The connection region of the two interconnected gate polysilicons is located on the first p+ type doping region and the two first n+ type doping regions and is separated by the gate resistor and the lateral oxide dielectric.

9. The withstand voltage IGBT device according to claim 1, characterized in that The collector layer and the emitter layer are both made of deposited metal.

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