Relay control circuit and electronic equipment

Abstract

The utility model discloses a relay control circuit and electronic equipment, and belongs to the technical field of relays. The guard circuit accesses a guard signal and outputs a switching signal according to the guard signal; the switching circuit transmits a first control signal according to the switching signal to output a second control signal, and maintains the output of the second control signal of the current level in response to the stop of the switching signal; the driving circuit outputs a driving signal to the relay according to the second control signal so as to control the relay to be switched off or switched on; therefore, when the master control circuit breaks down, no matter the state of the first control signal output port of the master control circuit is a high resistance state, a high level or a low level, because the switching circuit maintains the output of the second control signal of the current level in response to the stop of the switching signal, the level of the second control signal received by the driving circuit is not changed; therefore, the state of the relay is not changed, and the normal work of the current circuit is not influenced.

Description

Technical Field

[0001] The present application belongs to the technical field of relays, and in particular, relates to a relay control circuit and electronic equipment. Background Art

[0002] Figure 1 For the related relay control circuit, when the input / output port (IO) of the main chip outputs a high level, the field effect transistor Q27 is turned on and the relay is closed; when the IO port outputs a low level, the field effect transistor Q27 is turned off and the relay is turned off. In this control circuit, the state of the relay is strictly subject to the state of the IO port of the main chip. If the IO state of the main chip is unstable, such as restarting or resetting, the state of the relay will change, affecting the normal operation of the circuit, and the stability and reliability are poor. In order to solve this problem, the existing solution is to add an RC delay circuit to the gate of the field effect transistor Q27, but this solution is only applicable to the scenario where the IO state is high impedance or high level when the main chip is reset. If the main chip is powered off and restarted or the IO state is low when the main chip is reset, the state of the relay will still change, affecting the normal operation of the circuit.

[0003] Therefore, there is an urgent need for a relay control circuit to ensure that the state of the relay will not change regardless of whether the output port state of the main control circuit is a high impedance state, a high level or a low level. Summary of the invention

[0004] The purpose of the present application is to provide a relay control circuit and an electronic device, aiming to solve the problem that when the main chip in the existing relay control circuit is powered off and restarted or the main chip is reset, the state of the relay will change, affecting the normal operation of the circuit.

[0005] The embodiment of the present application provides a relay control circuit connected to a relay, including:

[0006] A control circuit configured to output a first control signal;

[0007] A guard circuit, configured to receive a guard signal and output a switch signal according to the guard signal;

[0008] a switch circuit connected to the control circuit and the guard circuit, configured to transmit the first control signal according to the switch signal to output a second control signal, and in response to the stop of the switch signal, maintain the output of the second control signal at a current level;

[0009] The driving circuit is connected to the switch circuit and the relay, and is configured to output a driving signal to the relay according to the second control signal to control the relay to be turned off or on.

[0010] In one of the embodiments, the guard circuit is connected to the control circuit;

[0011] The guard signal is a first PWM signal;

[0012] The control circuit is specifically configured to output the first control signal and the first PWM signal;

[0013] The guard circuit is specifically configured to output the switch signal in response to a duty cycle of the first PWM signal being within a preset interval.

[0014] In one embodiment, the guard circuit comprises:

[0015] a level conversion circuit, connected to the control circuit, and configured to perform level conversion on the first PWM signal to output a second PWM signal;

[0016] a filter circuit, connected to the level conversion circuit, and configured to filter the second PWM signal to output a first voltage;

[0017] A reference circuit configured to output a first reference voltage and a second reference voltage; the first reference voltage is greater than the second reference voltage;

[0018] The logic circuit is connected to the reference circuit and the filter circuit, and is configured to output the switch signal in response to the first voltage being greater than the second reference voltage and less than the first reference voltage.

[0019] In one of the embodiments, the level conversion circuit includes a seventh resistor, a fourteenth resistor and a first transistor;

[0020] The first end of the seventh resistor serves as the first PWM signal input end of the level conversion circuit and is connected to the control circuit to input the first PWM signal; the second end of the seventh resistor is connected to the base of the first transistor, the first end of the fourteenth resistor is connected to the first power supply, the collector of the first transistor and the second end of the fourteenth resistor jointly serve as the second PWM signal output end of the level conversion circuit to output the second PWM signal; the emitter of the first transistor is connected to the power ground.

[0021] In one embodiment, the logic circuit includes a first comparator, a second comparator, a second diode, a third diode, a second triode, an eighth resistor, and a ninth resistor;

[0022] The positive phase input terminal of the first comparator and the negative phase input terminal of the second comparator are jointly used as the first voltage input terminal of the logic circuit, connected to the filter circuit to input the first voltage; the negative phase input terminal of the first comparator is used as the first reference voltage input terminal of the logic circuit, connected to the reference circuit to input the first reference voltage; the positive phase input terminal of the second comparator is used as the second reference voltage input terminal of the logic circuit, connected to the reference circuit to input the second reference voltage; the output terminal of the first comparator is connected to the anode of the second diode, the output terminal of the second comparator is connected to the anode of the third diode, the cathode of the second diode is connected to the cathode of the third diode, the first end of the ninth resistor and the base of the second transistor, the collector of the second transistor and the first end of the eighth resistor are jointly used as the switch signal output terminal of the logic circuit, connected to the switch circuit to output the switch signal; the second end of the eighth resistor is connected to the second power supply; the second end of the ninth resistor and the emitter of the second transistor are commonly connected to the power supply ground.

[0023] In one of the embodiments, the guard circuit is connected to the control circuit;

[0024] The guard signal is a maintenance signal;

[0025] The control circuit is specifically configured to output the first control signal and the maintenance signal;

[0026] The guard circuit is specifically configured to output the switch signal according to the maintenance signal.

[0027] In one embodiment, it also includes:

[0028] A power supply circuit, connected to the guard circuit and configured to output a power supply voltage;

[0029] The guard circuit is specifically configured to output the switch signal according to the maintenance signal and the supply voltage.

[0030] In one embodiment, the protection circuit includes a first diode, a fourth resistor, a fifth resistor, a sixth resistor and a second capacitor;

[0031] The first end of the fifth resistor serves as the maintenance signal input terminal of the guard circuit and is connected to the control circuit to input the maintenance signal; the first end of the sixth resistor serves as the power supply voltage input terminal of the guard circuit and is connected to the power supply circuit to input the power supply voltage; the second end of the fifth resistor is connected to the second end of the sixth resistor, the first end of the fourth resistor and the cathode of the first diode, the second end of the fourth resistor, the anode of the first diode and the first end of the second capacitor together serve as the switch signal output terminal of the guard circuit and are connected to the switch circuit to output the switch signal; the second end of the second capacitor is connected to the power ground.

[0032] In one embodiment, the switch circuit includes a first field effect transistor, a second field effect transistor, a first resistor, a second resistor, a third resistor and a first capacitor;

[0033] The first end of the first resistor serves as the first control signal input end of the switch circuit and is connected to the control circuit to input the first control signal; the second end of the first resistor is connected to the drain of the first field effect transistor, the source of the first field effect transistor is connected to the source of the second field effect transistor and the first end of the second resistor, the gate of the first field effect transistor and the gate of the second field effect transistor jointly serve as the switch signal input end of the switch circuit and are connected to the guard circuit to access the switch signal; the drain of the second field effect transistor is connected to the first end of the third resistor, the second end of the third resistor and the first end of the first capacitor jointly serve as the second control signal output end of the switch circuit and are connected to the drive circuit to output the second control signal; the second end of the second resistor and the second end of the first capacitor are jointly connected to the power ground.

[0034] In one of the embodiments, the driving circuit includes a third field effect transistor;

[0035] The gate of the third field effect transistor serves as the second control signal input terminal of the drive circuit and is connected to the switch circuit to input the second control signal; the drain of the third field effect transistor serves as the drive signal output terminal of the drive circuit and is connected to the relay to output the drive signal; the source of the third field effect transistor is connected to the power ground.

[0036] An embodiment of the present application further provides an electronic device, which includes the above-mentioned relay control circuit.

[0037] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the control circuit outputs a first control signal; the guard circuit receives the guard signal and outputs a switch signal according to the guard signal; the switch circuit transmits the first control signal according to the switch signal to output a second control signal, and in response to the stop of the switch signal, maintains the output of the second control signal at the current level; the drive circuit outputs a drive signal to the relay according to the second control signal to control the relay to be turned off or closed; therefore, when the main control circuit fails, no matter whether the state of the first control signal output port of the main control circuit is high impedance, high level or low level, since the switch circuit maintains the output of the second control signal at the current level in response to the stop of the switch signal, the level of the second control signal received by the drive circuit remains unchanged, and therefore the state of the relay will not change, thereby not affecting the normal operation of the current circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical application in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A partial exemplary circuit schematic diagram of a conventional relay control circuit;

[0040] Figure 2 A schematic diagram of a structure of a relay control circuit provided in one embodiment of the present application;

[0041] Figure 3 A schematic diagram of a structure of a relay control circuit provided in one embodiment of the present application;

[0042] Figure 4 A schematic diagram of a structure of a relay control circuit provided in one embodiment of the present application;

[0043] Figure 5 A schematic diagram of a structure of a relay control circuit provided in one embodiment of the present application;

[0044] Figure 6 A partial exemplary circuit schematic diagram of a relay control circuit provided in an embodiment of the present application;

[0045] Figure 7 Another partial exemplary circuit schematic diagram of a relay control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0048] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0049] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0050] Figure 2 The structure diagram of the relay control circuit provided by an embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0051] The relay control circuit is connected to the relay K1 and includes a control circuit 100 , a guard circuit 200 , a switch circuit 300 and a drive circuit 400 .

[0052] The control circuit 100 is configured to output a first control signal.

[0053] The guard circuit 200 is configured to receive a guard signal and output a switch signal according to the guard signal.

[0054] The switch circuit 300 is connected to the control circuit 100 and the guard circuit 200, and is configured to transmit the first control signal according to the switch signal to output the second control signal, and maintain the output of the second control signal at a current level in response to the cessation of the switch signal.

[0055] The driving circuit 400 is connected to the switch circuit 300 and the relay K1 , and is configured to output a driving signal to the relay K1 according to the second control signal to control the relay K1 to be turned off or on.

[0056] In a specific implementation, the first control signal and the second control signal may have the same level, and when the level of the second control signal is high, the drive circuit 400 controls the relay K1 to close, and when the level of the second control signal is low, the drive circuit 400 controls the relay K1 to close.

[0057] Regardless of whether the state of the first control signal output port of the main control circuit is high impedance, high level or low level, since the switch circuit 300 maintains the output of the second control signal of the current level in response to the cessation of the switch signal, the level of the second control signal received by the drive circuit 400 remains unchanged, and therefore the state of the relay K1 will not change, thereby not affecting the normal operation of the current circuit.

[0058] By way of example and not limitation, Figure 3 As shown, the guard circuit 200 is connected to the control circuit 100 .

[0059] The guard signal is a first pulse width modulation (PWM) signal.

[0060] The control circuit 100 is specifically configured to output a first control signal and a first PWM signal.

[0061] The guard circuit 200 is specifically configured to output a switch signal in response to the duty cycle of the first PWM signal being within a preset interval.

[0062] It should be noted that the control circuit 100 outputs the first PWM signal with a duty cycle in a preset interval only when it is working normally, and the preset interval can be adjusted according to actual needs.

[0063] When an abnormality occurs in the control circuit 100, it stops outputting the first PWM signal. If the guard circuit 200 does not receive the first PWM signal, it stops outputting the switching signal. In response to the stop of the switching signal, the switching circuit 300 maintains the output of the second control signal at the current level, thereby avoiding the change of the state of the relay K1 and improving the reliability of the circuit.

[0064] By way of example and not limitation, Figure 4 As shown, the guard circuit 200 includes a level conversion circuit 210 , a filter circuit 220 , a reference circuit 230 and a logic circuit 240 .

[0065] The level conversion circuit 210 is connected to the control circuit 100 and is configured to perform level conversion on the first PWM signal to output a second PWM signal.

[0066] The filter circuit 220 is connected to the level conversion circuit 210 and is configured to filter the second PWM signal to output a first voltage.

[0067] The reference circuit 230 is configured to output a first reference voltage and a second reference voltage. The first reference voltage is greater than the second reference voltage.

[0068] The logic circuit 240 is connected to the reference circuit 230 and the filter circuit 220 , and is configured to output a switch signal in response to the first voltage being greater than the second reference voltage and less than the first reference voltage.

[0069] A failure of the control circuit 100 may cause its output port to be in a high impedance state, a low level or a high level state. However, through the level conversion circuit 210, the filter circuit 220, the reference circuit 230 and the logic circuit 240, a switching signal is output only when the first voltage is greater than the second reference voltage and less than the first reference voltage, thereby avoiding the erroneous output of the switching signal due to a failure of the control circuit 100 and improving the reliability of the circuit.

[0070] By way of example and not limitation, Figure 3 As shown, the guard circuit 200 is connected to the control circuit 100 .

[0071] The guard signal is a maintenance signal. It should be noted that the maintenance signal and the reset signal have opposite levels. When the maintenance signal is stopped, the reset signal is output.

[0072] The control circuit 100 is specifically configured to output a first control signal and a sustain signal.

[0073] The guard circuit 200 is specifically configured to output a switch signal according to the maintenance signal.

[0074] It should be noted that when the control circuit 100 is reset, it stops outputting the maintenance signal, that is, outputs a low-level reset signal. The guard circuit 200 stops outputting the switching signal according to the low-level reset signal. The switching circuit 300 responds to the stop of the switching signal and maintains the output of the second control signal at the current level, ensuring that the relay K1 maintains the current state unchanged when the control circuit 100 is reset by the reset signal, thereby improving the reliability of the circuit.

[0075] By way of example and not limitation, Figure 5 As shown, the relay control circuit also includes a power supply circuit 500 connected to the guard circuit 200 and configured to output a supply voltage.

[0076] The guard circuit 200 is specifically configured to output a switch signal according to the maintenance signal and the supply voltage.

[0077] If the power supply circuit 500 fails and stops outputting the supply voltage, the guard circuit 200 stops outputting the switch signal, ensuring that the relay K1 maintains the current state when the control circuit 100 is powered off and restarted, thereby improving the reliability of the circuit.

[0078] Figure 6 A partial exemplary circuit structure of a relay control circuit provided in an embodiment of the present application is shown. Figure 7 Another partial exemplary circuit structure of the relay control circuit provided in the embodiment of the present application is shown. For the convenience of explanation, only the part related to the embodiment of the present application is shown, which is described in detail as follows:

[0079] like Figure 6 As shown, the level conversion circuit 210 includes a seventh resistor R7, a fourteenth resistor R14 and a first transistor P1.

[0080] The first end of the seventh resistor R7 serves as the first PWM signal input end of the level conversion circuit 210, and is connected to the control circuit 100 to input the first PWM signal; the second end of the seventh resistor R7 is connected to the base of the first transistor P1, the first end of the fourteenth resistor R14 is connected to the first power supply, the collector of the first transistor P1 and the second end of the fourteenth resistor R14 serve together as the second PWM signal output end of the level conversion circuit 210 to output the second PWM signal; the emitter of the first transistor P1 is connected to the power ground.

[0081] The level conversion is realized by the first transistor P1, so the adaptability of the circuit is improved, and the first transistor P1 has fast action, small loss and high stability.

[0082] like Figure 6 As shown, the logic circuit 240 includes a first comparator M1, a second comparator M2, a second diode D2, a third diode D3, a second transistor P2, an eighth resistor R8 and a ninth resistor R9.

[0083] The positive input terminal of the first comparator M1 and the negative input terminal of the second comparator M2 are used together as the first voltage input terminal of the logic circuit 240, which is connected to the filter circuit 220 to input the first voltage; the negative input terminal of the first comparator M1 is used as the first reference voltage input terminal of the logic circuit 240, which is connected to the reference circuit 230 to input the first reference voltage; the positive input terminal of the second comparator M2 is used as the second reference voltage input terminal of the logic circuit 240, which is connected to the reference circuit 230 to input the second reference voltage; the output terminal of the first comparator M1 is connected to the second comparator M2. The anode of the transistor D2 is connected, the output end of the second comparator M2 is connected to the anode of the third diode D3, the cathode of the second diode D2 is connected to the cathode of the third diode D3, the first end of the ninth resistor R9 and the base of the second triode P2 are connected, the collector of the second triode P2 and the first end of the eighth resistor R8 are used as the switching signal output end of the logic circuit 240, and are connected to the switching circuit 300 to output the switching signal; the second end of the eighth resistor R8 is connected to the second power supply; the second end of the ninth resistor R9 and the emitter of the second triode P2 are commonly connected to the power ground.

[0084] It should be noted that the first power source and the second power source may be the same power source.

[0085] The logic circuit 240 is composed of comparators, and the circuit structure is simple and easy to implement.

[0086] like Figure 6 As shown, the filter circuit 220 includes a thirteenth resistor R13 and a third capacitor C3.

[0087] The first end of the thirteenth resistor R13 serves as the second PWM signal input end of the filter circuit 220, and is connected to the level conversion circuit 210 to input the second PWM signal; the second end of the thirteenth resistor R13 and the first end of the third capacitor C3 serve together as the first voltage output end of the filter circuit 220, and are connected to the logic circuit 240 to output the first voltage; the second end of the third capacitor C3 is connected to the power ground.

[0088] like Figure 6 As shown, the reference circuit 230 includes a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12.

[0089] The first end of the tenth resistor R10 is connected to the first power supply, the second end of the tenth resistor R10 and the first end of the eleventh resistor R11 serve together as the first reference voltage output end of the reference circuit 230, and are connected to the logic circuit 240 to output the first reference voltage; the second end of the eleventh resistor R11 and the first end of the twelfth resistor R12 serve together as the second reference voltage output end of the reference circuit 230, and are connected to the logic circuit 240 to output the second reference voltage; the second end of the twelfth resistor R12 is connected to the power ground.

[0090] like Figure 6 As shown, the control circuit 100 includes a microprocessor U1.

[0091] The first universal input and output terminal P1.0 of the microprocessor U1 serves as the first control signal output terminal of the control circuit 100, and is connected to the switching circuit 300 to output a first control signal; the second universal input and output terminal P1.1 of the microprocessor U1 serves as the first PWM signal output terminal of the control circuit 100, and is connected to the protection circuit 200 to output a first PWM signal.

[0092] like Figure 7 As shown, the protection circuit 200 includes a first diode D1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second capacitor C2.

[0093] The first end of the fifth resistor R5 serves as the maintenance signal input terminal of the protection circuit 200 and is connected to the control circuit 100 to input the maintenance signal; the first end of the sixth resistor R6 serves as the power supply voltage input terminal of the protection circuit 200 and is connected to the power supply circuit 500 to input the power supply voltage; the second end of the fifth resistor R5 is connected to the second end of the sixth resistor R6, the first end of the fourth resistor R4 and the cathode of the first diode D1, the second end of the fourth resistor R4 and the anode of the first diode D1 and the first end of the second capacitor C2 serve together as the switching signal output terminal of the protection circuit 200 and are connected to the switching circuit 300 to output the switching signal; the second end of the second capacitor C2 is connected to the power ground.

[0094] It should be noted that the fifth resistor R5 and the sixth resistor R6 are used to isolate the power supply voltage and the sustain signal to avoid mutual interference between the power supply voltage and the sustain signal.

[0095] The second capacitor C2 is charged when the power supply voltage is connected, and is discharged when the power supply voltage is stopped. The charging time of the second capacitor C2 can be adjusted by adjusting the size of the fourth resistor R4, so that the second capacitor C2 is in a low level state when the microprocessor U1 in the control circuit 100 is restarted. At this time, the protection circuit 200 stops outputting the switching signal, avoiding misleading conduction of the switching circuit 300 when the control circuit 100 is restarted, and the second diode D2 can also be used to achieve rapid discharge of the second capacitor C2 when the power supply voltage stops being input.

[0096] The circuit is simple and low cost.

[0097] like Figure 6 and Figure 7 As shown, the switch circuit 300 includes a first field effect transistor Q1, a second field effect transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3 and a first capacitor C1.

[0098] The first end of the first resistor R1 serves as the first control signal input end of the switch circuit 300 and is connected to the control circuit 100 to input the first control signal; the second end of the first resistor R1 is connected to the drain of the first field effect transistor Q1, the source of the first field effect transistor Q1 is connected to the source of the second field effect transistor Q2 and the first end of the second resistor R2, the gate of the first field effect transistor Q1 and the gate of the second field effect transistor Q2 jointly serve as the switch signal input end of the switch circuit 300 and are connected to the guard circuit 200 to access the switch signal; the drain of the second field effect transistor Q2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 and the first end of the first capacitor C1 jointly serve as the second control signal output end of the switch circuit 300 and are connected to the drive circuit 400 to output the second control signal; the second end of the second resistor R2 and the second end of the first capacitor C1 are jointly connected to the power ground.

[0099] It should be noted that the first resistor R1 and the second resistor R2 are voltage-dividing resistors, which avoid the situation where the difference between the gate and source voltages of the two field effect transistors is 0 when the first field effect transistor Q1 and the second field effect transistor Q2 receive a high-level switching signal and the first control signal output terminal of the control circuit 100 is at a high level, resulting in the two field effect transistors being cut off, thereby improving the reliability of the circuit.

[0100] like Figure 6 and Figure 7 As shown, the driving circuit 400 includes a third field effect transistor Q3.

[0101] The gate of the third field effect transistor Q3 serves as the second control signal input terminal of the driving circuit 400, and is connected to the switch circuit 300 to input the second control signal; the drain of the third field effect transistor Q3 serves as the driving signal output terminal of the driving circuit 400, and is connected to the relay K1 to output the driving signal; the source of the third field effect transistor Q3 is connected to the power ground.

[0102] The circuit is simple and reliable.

[0103] like Figure 7 As shown, the control circuit 100 includes a microprocessor U1.

[0104] The first general input and output terminal P1.0 of the microprocessor U1 serves as the first control signal output terminal of the control circuit 100, and is connected to the switching circuit 300 to output a first control signal; the third general input and output terminal P1.2 of the microprocessor U1 serves as the maintenance signal output terminal of the control circuit 100, and is connected to the protection circuit 200 to output a maintenance signal.

[0105] The following is a combination of working principles Figure 6 to Figure 7 As shown for further explanation:

[0106] like Figure 6As shown, during normal operation, the second general input and output terminal P1.1 of the microprocessor U1 outputs a first PWM signal to the first end of the seventh resistor R7, the first end of the fourteenth resistor R14 is connected to the first power supply, the first transistor P1 outputs a second PWM signal from the collector of the first transistor P1 to the first end of the thirteenth resistor R13, the third capacitor C3 and the thirteenth resistor R13 convert the second PWM signal into a first voltage and output it from the first end of the third capacitor C3 to the positive input end of the first comparator M1 and the negative input end of the second comparator M2, the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 divide the first power supply, and output the first reference voltage from the second end of the tenth resistor R10 and the first end of the eleventh resistor R11 to the first comparator M1. The inverting input terminal outputs the second reference voltage from the second terminal of the eleventh resistor R11 and the first terminal of the twelfth resistor R12 to the non-inverting input terminal of the second comparator M2. At this time, the first voltage is less than the first reference voltage and greater than the second reference voltage. The first comparator M1 outputs a low level from the output terminal to the anode of the second diode D2. The second comparator M2 outputs a low level from the output terminal to the anode of the third diode D3. The cathode of the second diode D2 and the cathode of the third diode D3 jointly output a low level to the base of the second triode P2. The second triode P2 is turned off, and a high-level switching signal is output from the collector of the second triode P2 and the first terminal of the eighth resistor R8 to the gate of the first field effect transistor Q1 and the gate of the second field effect transistor Q2. The first field effect transistor Q1 and the second field effect transistor Q2 are turned on. At the same time, the first universal input and output terminal P1.0 of the microprocessor U1 outputs a first control signal to the first end of the first resistor R1. If the first control signal is at a high level at this time, the first resistor R1 and the second resistor R2 divide the first control signal, so that the difference between the gate and source voltages of the first field effect transistor Q1 and the second field effect transistor Q2 both meet the threshold voltage of their conduction, ensuring that the first field effect transistor Q1 and the second field effect transistor Q2 are turned on, and the divided first control signal is transmitted to the first capacitor C1. The divided first control signal can turn on the third field effect transistor Q3. For example, the microprocessor U1 outputs a high-level first control signal, and the first resistor R1 and the second resistor R2 divide it. When the voltage drop across the second resistor R2 is 1.6V, the first field effect transistor Q1 and the second field effect transistor Q2 can be effectively turned on, and the voltage from the gate to the ground of the third field effect transistor Q3 is also 1.6V, which can also be turned on; the first capacitor C1 converts the divided first control signal into a high-level second control signal and outputs it from the first end of the first capacitor C1 to the gate of the third field effect transistor Q3, the third field effect transistor Q3 is turned on, and the high-level second control signal is converted into a drive signal, which is output from the drain of the third field effect transistor Q3 to the relay K1, and the relay K1 is closed; if the first control signal is low at this time, the third field effect transistor Q3 is turned off, stops outputting the drive signal, and the relay K1 is turned off.

[0107] When the circuit fails, the second universal input and output terminal P1.1 of the microprocessor U1 stops outputting the first PWM signal. At this time, its state may be high level, high impedance state or low level. When it is high level, the first voltage output by the third capacitor C3 is higher than the first reference voltage, and the first comparator M1 outputs a high level. When it is low level or high impedance state, the first voltage output by the third capacitor C3 is lower than the second reference voltage, and the second comparator M2 outputs a high level. That is, no matter what state the second universal input and output terminal P1.1 of the microprocessor U1 is in at this time, the cathode of the second diode D2 and the cathode of the third comparator M2 are connected. The cathodes of the diodes D3 all output a high level to the base of the second transistor P2, the second transistor P2 is turned on, and a low level switching signal is output from the collector of the second transistor P2 to the gate of the first field effect transistor Q1 and the gate of the second field effect transistor Q2, the first field effect transistor Q1 and the second field effect transistor Q2 are turned off, so that no matter the first universal input and output terminal P1.0 of the microprocessor U1 is in a high level, a high impedance state or a low level, the first capacitor C1 maintains the output of the second control signal at the current level, the relay K1 maintains the current state, and the circuit works normally.

[0108] like Figure 7 As shown, in normal operation, the third general input and output terminal P1.2 of the microprocessor U1 outputs a high-level maintenance signal to the first end of the fifth resistor R5, and the power supply circuit 500 outputs a supply voltage to the first end of the sixth resistor R6. At this time, the second capacitor C2 stores energy, and outputs a high-level switching signal from the first end of the second capacitor C2 to the gate of the first field effect transistor Q1 and the gate of the second field effect transistor Q2, and the first field effect transistor Q1 and the second field effect transistor Q2 are turned on. When the third general input and output terminal P1.2 of the microprocessor U1 stops outputting the maintenance signal (i.e., outputting a low-level reset signal), the second capacitor C2 is quickly discharged through the first diode D1, and a low-level switching signal is output from the first end of the second capacitor C2 to the gate of the first field effect transistor Q1 and the gate of the second field effect transistor Q2, and the first field effect transistor Q1 and the second field effect transistor Q2 are turned off. When the third universal input / output terminal P1.2 of the microprocessor U1 outputs a high-level maintenance signal or the power supply circuit 500 is powered on again, the second capacitor C2 starts to charge. At this time, since the microprocessor U1 is also in the restart stage, it is necessary to delay through the design of the fourth resistor R4 and the second capacitor C2, so that the first field effect transistor Q1 and the second field effect transistor Q2 are turned on again after the microprocessor U1 is completely restarted. Otherwise, during the restart of the microprocessor U1, the uncertain state (high level, low level or high impedance state) of its first universal input / output terminal P1.0 will affect the working state of the relay. The working principles of the remaining circuits are the same. Figure 6 The same as shown, no further description is given here.

[0109] An embodiment of the present application also provides an electronic device, which includes the above-mentioned relay control circuit.

[0110] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0111] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A relay control circuit, characterized in that: Connect with relay, including: A control circuit configured to output a first control signal; A guard circuit, configured to receive a guard signal and output a switch signal according to the guard signal; a switch circuit connected to the control circuit and the guard circuit, configured to transmit the first control signal according to the switch signal to output a second control signal, and in response to the stop of the switch signal, maintain the output of the second control signal at a current level; The driving circuit is connected to the switch circuit and the relay, and is configured to output a driving signal to the relay according to the second control signal to control the relay to be turned off or on.

2. The relay control circuit according to claim 1, characterized in that: The guard circuit is connected to the control circuit; The guard signal is a first PWM signal; The control circuit is specifically configured to output the first control signal and the first PWM signal; The guard circuit is specifically configured to output the switch signal in response to a duty cycle of the first PWM signal being within a preset interval.

3. The relay control circuit according to claim 2, characterized in that: The protection circuit comprises: a level conversion circuit, connected to the control circuit, and configured to perform level conversion on the first PWM signal to output a second PWM signal; a filter circuit, connected to the level conversion circuit, and configured to filter the second PWM signal to output a first voltage; A reference circuit configured to output a first reference voltage and a second reference voltage; the first reference voltage is greater than the second reference voltage; The logic circuit is connected to the reference circuit and the filter circuit, and is configured to output the switch signal in response to the first voltage being greater than the second reference voltage and less than the first reference voltage.

4. The relay control circuit according to claim 3, characterized in that: The level conversion circuit includes a seventh resistor, a fourteenth resistor and a first transistor; The first end of the seventh resistor is used as the first PWM signal input end of the level conversion circuit, and is connected to the control circuit to input the first PWM signal; the second end of the seventh resistor is connected to the base of the first transistor, the first end of the fourteenth resistor is connected to the first power supply, and the collector of the first transistor and the second end of the fourteenth resistor are used together as the second PWM signal output end of the level conversion circuit to output the second PWM signal; The emitter of the first transistor is connected to the power ground.

5. The relay control circuit according to claim 3, characterized in that: The logic circuit includes a first comparator, a second comparator, a second diode, a third diode, a second triode, an eighth resistor and a ninth resistor; The positive phase input terminal of the first comparator and the negative phase input terminal of the second comparator are used together as the first voltage input terminal of the logic circuit, and are connected to the filter circuit to input the first voltage; The inverting input terminal of the first comparator is used as the first reference voltage input terminal of the logic circuit and is connected to the reference circuit to input the first reference voltage; The non-inverting input terminal of the second comparator serves as the second reference voltage input terminal of the logic circuit and is connected to the reference circuit to input the second reference voltage; the output terminal of the first comparator is connected to the anode of the second diode, the output terminal of the second comparator is connected to the anode of the third diode, the cathode of the second diode is connected to the cathode of the third diode, the first terminal of the ninth resistor and the base of the second transistor, the collector of the second transistor and the first terminal of the eighth resistor serve together as the switching signal output terminal of the logic circuit and are connected to the switching circuit to output the switching signal; the second terminal of the eighth resistor is connected to the second power supply; the second terminal of the ninth resistor and the emitter of the second transistor are connected to the power ground.

6. The relay control circuit according to claim 1, characterized in that: The guard circuit is connected to the control circuit; The guard signal is a maintenance signal; The control circuit is specifically configured to output the first control signal and the maintenance signal; The guard circuit is specifically configured to output the switch signal according to the maintenance signal.

7. The relay control circuit according to claim 6, characterized in that: Also includes: A power supply circuit, connected to the guard circuit and configured to output a power supply voltage; The guard circuit is specifically configured to output the switch signal according to the maintenance signal and the supply voltage.

8. The relay control circuit according to claim 7, characterized in that: The protection circuit includes a first diode, a fourth resistor, a fifth resistor, a sixth resistor and a second capacitor; The first end of the fifth resistor serves as the maintenance signal input terminal of the guard circuit and is connected to the control circuit to input the maintenance signal; the first end of the sixth resistor serves as the power supply voltage input terminal of the guard circuit and is connected to the power supply circuit to input the power supply voltage; the second end of the fifth resistor is connected to the second end of the sixth resistor, the first end of the fourth resistor and the cathode of the first diode, the second end of the fourth resistor, the anode of the first diode and the first end of the second capacitor together serve as the switch signal output terminal of the guard circuit and are connected to the switch circuit to output the switch signal; the second end of the second capacitor is connected to the power ground.

9. The relay control circuit according to any one of claims 1 to 8, characterized in that: The switch circuit includes a first field effect transistor, a second field effect transistor, a first resistor, a second resistor, a third resistor and a first capacitor; The first end of the first resistor serves as the first control signal input end of the switch circuit and is connected to the control circuit to input the first control signal; the second end of the first resistor is connected to the drain of the first field effect transistor, the source of the first field effect transistor is connected to the source of the second field effect transistor and the first end of the second resistor, the gate of the first field effect transistor and the gate of the second field effect transistor jointly serve as the switch signal input end of the switch circuit and are connected to the guard circuit to access the switch signal; the drain of the second field effect transistor is connected to the first end of the third resistor, the second end of the third resistor and the first end of the first capacitor jointly serve as the second control signal output end of the switch circuit and are connected to the drive circuit to output the second control signal; the second end of the second resistor and the second end of the first capacitor are jointly connected to the power ground.

10. The relay control circuit according to any one of claims 1 to 8, characterized in that: The driving circuit includes a third field effect transistor; The gate of the third field effect transistor serves as the second control signal input terminal of the driving circuit and is connected to the switch circuit to input the second control signal; The drain of the third field effect transistor serves as a driving signal output terminal of the driving circuit and is connected to the relay to output the driving signal; The source of the third field effect transistor is connected to the power ground.

11. An electronic device, characterized in that: Comprising the relay control circuit as claimed in any one of claims 1 to 10.

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