High-performance groove type IGBT device structure

Abstract

The utility model discloses a high-performance groove type IGBT device structure, which relates to the field of semiconductor devices and comprises a substrate of a first conductive type and an active region prepared in a central region of the substrate. A second conductive type base region corresponding to the front surface of the substrate and traversing the active region, and a first conductive type carrier storage layer traversing the second conductive type base region are arranged in the first conductive type substrate; the first conduction type carrier storage layer divides the second conduction type base region into a second conduction type first base region and a second conduction type second base region, and the second conduction type first base region is located above the second conduction type second base region; the first conductive type carrier storage layer is isolated from the first conductive type substrate through the second conductive type second base region. According to the IGBT device, the influence of the first conductive type charge storage layer on the breakdown voltage of the device is eliminated, and the IGBT device has relatively small saturation voltage drop and good switching characteristics.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor devices, in particular to a high-performance trench-type IGBT device structure. Background Art

[0002] As a new generation of power electronic devices, the insulated gate bipolar transistor (IGBT) combines the field effect transistor (MOSFET) and the bipolar junction transistor (BJT). It has the advantages of MOSFET, such as easy driving, low input impedance, and fast switching speed, as well as the advantages of BJT, such as high on-state current density, low on-voltage drop, low loss, and good stability. Therefore, it has developed into one of the core electronic components in modern power electronic circuits and is widely used in various fields such as transportation, communications, household appliances, and aerospace.

[0003] In the more than 30 years since the IGBT was introduced, how to reduce the switching loss of the IGBT and improve the trade-off relationship between the device's on-state voltage drop and turn-off loss has always been the focus of research. From the first generation of planar gate punch-through IGBT (PT-IGBT) to the sixth generation of field stop trench IGBT (FST-IGBT), researchers have continuously improved the performance of IGBT by continuously improving the front and back structures of IGBT.

[0004] For the sixth generation FST-IGBT, its performance can still be further improved. On this basis, the seventh generation trench charge storage IGBT (CST-IGBT) was invented. Compared with FST-IGBT, CST-IGBT introduces an N-type carrier storage layer (N-CS) under the P-type base region. The introduction of the N-type carrier storage layer provides a hole barrier, which enhances the carrier concentration on the device surface, improves the distribution of carriers on the device substrate, enhances the conductivity modulation effect, reduces the forward conduction voltage drop of the device, and thus optimizes the compromise relationship between the on-state voltage drop and the turn-off loss of the device.

[0005] However, in practical applications, although the N-CS layer can reduce the saturation voltage drop (Vce, sat) to a certain extent, it will also reduce the depletion layer extension area in the substrate, weaken the pressure-bearing capacity of the device during reverse shutdown, and cause the breakdown characteristics of the device to degrade. At present, in order to ensure that the breakdown characteristics of the device are not degraded, the technical personnel in this field will increase the depth of the trench gate. However, the deeper trench gate will increase the gate capacitance of the device, especially the Miller capacitance (Cgc), and then increase the charge (Qgc) between the gate and the collector, thereby causing the switching characteristics of the device to deteriorate.

[0006] In addition, the existing trench IGBT also has the problem of excessive saturation current density. Excessive saturation current density will shorten the short-circuit withstand time of the device, affecting the short-circuit characteristics of the device, and will also further increase the Cgc and Qgc of the device, affecting the switching characteristics of the device. At the same time, the electric field of the existing trench IGBT is relatively concentrated at the gate oxide layer at the bottom of the trench, and the electric field there is also relatively large, which is easy to cause the problem of long-term reliability degradation of the device. At present, the traditional trench IGBT often needs to be connected in anti-parallel with a fast recovery diode (FRD) for freewheeling when in use, which will additionally increase the cost and volume of the application. Utility Model Content

[0007] In view of the above problems and technical requirements, the applicant has proposed a high-performance trench IGBT device structure. The technical solution of the utility model is as follows:

[0008] A high-performance trench IGBT device structure includes a substrate of a first conductivity type and an active region prepared in a central region of the substrate;

[0009] The first conductive type substrate is provided with a second conductive type base region corresponding to the front side of the substrate and traversing the active region, and a first conductive type carrier storage layer traversing the second conductive type base region;

[0010] The first conductive type carrier storage layer separates the second conductive type base region into a second conductive type first base region and a second conductive type second base region, wherein:

[0011] The second conductivity type first base region is located above the second conductivity type second base region, and the first conductivity type carrier storage layer is isolated from the first conductivity type substrate by the second conductivity type second base region.

[0012] A further technical solution is that the active area includes a plurality of trench-type cells distributed in parallel, and the trench-type cells include trench gate units;

[0013] At least one dummy gate unit is disposed in the active area;

[0014] The front side of the substrate is provided with an emitter metal for forming an emitter and a gate metal for forming a gate;

[0015] The dummy gate unit is electrically connected to an emitter metal for forming an emitter, and the trench gate unit is electrically connected to a gate metal for forming a gate.

[0016] A further technical solution is that the trench gate unit comprises a cell trench, a trench gate oxide layer and a trench gate electrode body filled in the cell trench, wherein:

[0017] The outer sidewall of the cell trench at least contacts the first base region of the second conductivity type;

[0018] The trench gate electrode body is isolated from the inner wall of the cell trench by a trench gate oxide layer, and the trench gate electrode body is electrically connected to the gate metal.

[0019] A further technical solution is that a second conductive type shielding region is provided below the cell trench, and the second conductive type shielding region covers the bottom of the cell trench and contacts the first conductive type substrate.

[0020] A further technical solution is that the virtual gate unit includes a virtual gate trench, a virtual gate oxide layer, and a virtual gate electrode body filled in the virtual gate trench;

[0021] The virtual gate electrode body is isolated from the inner wall of the virtual gate trench by a virtual gate oxide layer, and the virtual gate electrode body is electrically connected to the emitter metal.

[0022] A further technical solution is that a first conductive type barrier region is provided below the virtual gate trench, and the first conductive type barrier region covers the bottom of the virtual gate trench;

[0023] The first conductive type barrier region contacts the first conductive type substrate, and the doping concentration of the first conductive type barrier region is greater than the doping concentration of the first conductive type substrate.

[0024] A further technical solution thereof is that it also includes a first conductive type buffer layer and a second conductive type collector region corresponding to the back side of the substrate;

[0025] The first conductive type buffer layer is located above the second conductive type collector region and contacts the second conductive type collector region;

[0026] The second conductive type collector region is in ohmic contact with a collector metal on the back side of the substrate for forming a collector.

[0027] A further technical solution is that a diode unit for forming a diode is arranged in the second conductive type collector region, and the diode unit includes a plurality of first conductive type collector regions in contact with the first conductive type buffer layer;

[0028] The first conductive type collector region is in ohmic contact with a collector metal on the back side of the substrate for forming a collector.

[0029] A further technical solution is that a first conductive type emitter region and a second conductive type emitter region are provided in the second conductive type first base region, wherein:

[0030] The first conductive type emitter region is located above the second conductive type emitter region and contacts the second conductive type emitter region;

[0031] The first conductive type emitter region is in contact with the trench gate unit and / or the dummy gate unit, and the second conductive type emitter region is isolated from the trench gate unit and / or the dummy gate unit by the second conductive type first base region;

[0032] The first conductive type emitter region and the second conductive type emitter region are both in ohmic contact with the emitter metal.

[0033] A further technical solution is that the doping concentration of the first conductive type carrier storage layer is greater than the doping concentration of the first conductive type substrate;

[0034] The thickness of the second conductivity type first base region is not less than the thickness of the second conductivity type second base region.

[0035] In the above-mentioned "first conductivity type" and "second conductivity type", for N-type IGBT devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type IGBT devices, the types referred to by the first conductivity type and the second conductivity type are opposite to those of N-type devices.

[0036] The beneficial technical effects of the utility model are:

[0037] The utility model sets an N-type carrier storage layer that traverses the P-type base region in the P-type base region. When the device is reversely turned off, the N-type carrier storage layer is isolated by using the P-type second base region, thereby eliminating the influence of the N-type carrier storage layer on the breakdown voltage of the device, reducing the saturation voltage drop while ensuring that the breakdown characteristics of the IGBT device are not affected.

[0038] In addition, the utility model sets a virtual gate unit in the active area. Connecting the virtual gate unit to the emitter potential can effectively reduce the proportion of the conductive channel in the device, reduce the saturation current density of the device, thereby increasing the short-circuit tolerance time of the device and improving the short-circuit characteristics and switching characteristics.

[0039] At the same time, an N-type blocking region is set under the virtual gate trench in the virtual gate unit. When the power device is forward-conducting, the N-type blocking region can block some holes from flowing from the N-type substrate to the emitter to enhance the conductivity effect in the N-type substrate and further reduce the saturation voltage drop. A P-type shielding region is set under the cell trench, which can effectively reduce the electric field size at the gate oxide layer at the bottom of the cell trench and improve the reliability of the gate oxide.

[0040] The utility model also sets a plurality of N-type collector regions in the P-type collector region on the back of the substrate to integrate the diode into the device, so that the IGBT does not need additional parallel diodes when in use, thus saving chip area and improving power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a cross-sectional view of an embodiment of a high-performance trench IGBT device structure provided by the utility model.

[0042] Figure 2-Figure 8 This is a cross-sectional view of the process steps of an embodiment of a method for preparing a high-performance trench IGBT device provided by the utility model, wherein:

[0043] Figure 2 It is a cross-sectional view of an embodiment of the utility model after the P-type shielding region and the N-type blocking region are prepared.

[0044] Figure 3 It is a cross-sectional view of an embodiment of the utility model after the trench gate electrode body and the virtual gate electrode body are prepared.

[0045] Figure 4 It is a cross-sectional view of an embodiment of the utility model after the N-type emission region is prepared.

[0046] Figure 5 It is a cross-sectional view of an embodiment of the utility model after the P-type emission region is prepared.

[0047] Figure 6 It is a cross-sectional view of an embodiment of the utility model after the emitter metal is prepared.

[0048] Figure 7 It is a cross-sectional view of an embodiment of the utility model after the N-type buffer layer is prepared.

[0049] Figure 8 It is a cross-sectional view of an embodiment of the utility model after the collector metal is prepared.

[0050] Figure numerals: 1-collector metal, 2-P-type collector region, 3-N-type buffer layer, 4-N-type substrate, 5-N-type barrier region, 6-P-type shielding region, 7-virtual gate trench, 8-virtual gate oxide layer, 9-virtual gate electrode body, 10-cell trench, 11-trench gate oxide layer, 12-trench gate electrode body, 13-N-type carrier storage layer, 141-P-type first base region, 142-P-type second base region, 15-N-type collector region, 16-N-type emitter region, 17-P-type emitter region, 18-insulating dielectric layer, 19-first electrode metal, 20-first contact hole, 21-second contact hole. DETAILED DESCRIPTION

[0051] The specific implementation of the utility model is further described below in conjunction with the accompanying drawings.

[0052] The utility model provides a high-performance trench IGBT device structure. Taking the first conductivity type as N-type as an example, an embodiment of the utility model includes an N-type substrate 4 and an active region prepared in the central region of the substrate 4;

[0053] The N-type substrate 4 is provided with a P-type base region corresponding to the front surface of the substrate 4 and traversing the active region, and an N-type carrier storage layer 13 traversing the P-base region.

[0054] The N-type carrier storage layer 13 separates the P-type base region into a P-type first base region 141 and a P-type second base region 142, wherein:

[0055] The P-type first base region 141 is located above the P-type second base region 142 , and the N-type carrier storage layer 13 is isolated from the N-type substrate 4 by the P-type second base region 142 .

[0056] Specifically, the substrate 4 can be made of existing common materials, such as silicon substrate, SiC substrate, etc., to meet application requirements. The substrate 4 generally has a front side and a back side corresponding to the front side. For an IGBT device, it generally includes an active area located in the center area of ​​the substrate 4 and a terminal protection area surrounding the active area. The specific functions and distribution states of the active area and the terminal protection area can be consistent with the prior art.

[0057] In this embodiment, the P-type base region extends vertically from the front side of the N-type substrate 4 to the back side of the substrate 4, the N-type carrier storage layer 13 is arranged in the middle of the P-type base region, and the P-type base region is divided into a P-type first base region 141 and a P-type second base region 142, the N-type carrier storage layer 13 is isolated from the N-type substrate 4 by the P-type second base region 142, and the doping concentration of the N-type carrier storage layer 13 is greater than the doping concentration of the N-type substrate 4. When the IGBT is forward-conducted, the N-type carrier storage layer 13 can improve the carrier distribution in the device substrate 4, enhance the conductivity modulation effect, and thus reduce the forward conduction voltage drop of the device. When the IGBT is reversely turned off, since the N-type carrier storage layer 13 is isolated by the P-type second base region 142, the PN junction formed by the P-type second base region 142 and the N-type carrier storage layer 13 will withstand the reverse voltage, thereby eliminating the influence of the N-type charge storage layer 13 on the device breakdown voltage.

[0058] Generally, in the cross section of the active region, the thickness of the P-type first base region 141 is greater than or equal to the thickness of the P-type second base region 142, so as to form a conductive channel at the contact between the P-type first base region 141 and the outer wall of the cell trench 10 of the trench-type cell. The thickness of the N-type carrier storage layer 13 may be the same as the thickness of the P-type second base region 142.

[0059] Furthermore, the active region includes a plurality of trench-type cells distributed in parallel, and the trench-type cells include trench gate units.

[0060] Specifically, the active area includes a number of cells distributed in parallel. In one embodiment of the utility model, the cell adopts a trench-type cell, that is, the active area includes a number of trench-type cells. In the active area, the trench-type cells can generally adopt the same structural form. The trench gate unit includes a cell trench 10, a trench gate oxide layer 11, and a trench gate electrode body 12 filled in the cell trench 10, wherein the outer side wall of the cell trench 10 is in contact with at least the P-type first base region 141 to form a conductive channel at the contact point between the P-type first base region 141 and the outer wall of the cell trench 10. Generally, the cell trench 10 passes through the P-type first base region 141, the N-type carrier storage layer 13, and the P-type second base region 142 from the front of the substrate 4, and the bottom of the cell trench 10 is located in the N-type substrate 4 below the P-type second base region 142.

[0061] The front side of the substrate 4 is provided with a gate metal for forming a gate, and the trench gate electrode body 12 is isolated from the inner wall of the cell trench 10 by the trench gate oxide layer 11, and the trench gate electrode body 12 is electrically connected to the gate metal. The material of the trench gate electrode body 12 can be metal or polysilicon. When the material of the trench gate electrode body 12 is polysilicon, the trench gate electrode body 12 is in ohmic contact with the gate metal. The specific form of the ohmic contact between the trench gate electrode body 12 and the gate metal can refer to the following description.

[0062] Furthermore, in order to improve the short-circuit characteristics of the device and reduce the gate-collector capacitance Cgc and the gate-collector charge Qgc, at least one virtual gate unit is set in the active area. Optionally, the number and distribution of virtual gate units in the active area can be selected according to actual needs. In one embodiment of the utility model, the number of virtual gate units is the same as the number of trench gate units. In the direction from the terminal area to the active area, the virtual gate units and the trench gate units are arranged alternately, and any trench-type cell includes a trench gate unit and a virtual gate unit. The virtual gate unit set in the active area reduces the area of ​​the gate electrode body that actually acts in the device, effectively reduces the proportion of the conductive channel in the device, and reduces the saturation current density of the device, thereby increasing the short-circuit tolerance time of the two devices and improving the short-circuit characteristics. At the same time, the setting of the virtual gate unit can also reduce the area of ​​the gate electrode body used to form the gate-collector capacitance Cgc, which can significantly reduce the gate-collector capacitance Cgc and the gate-collector charge Qgc, and improve the switching characteristics of the device.

[0063] Specifically, the virtual gate unit includes a virtual gate trench 7, a virtual gate oxide layer 8, and a virtual gate electrode body 9 filled in the virtual gate trench. An emitter metal 19 for forming an emitter is provided on the front side of the substrate 4, and the virtual gate electrode body 9 is isolated from the inner wall of the virtual gate trench 7 by the virtual gate oxide layer 8, and the virtual gate electrode body is electrically connected to the emitter metal 19.

[0064] Generally, the cell trench 10 and the dummy gate trench 7 are both in the shape of long strips, and the length direction of the cell trench 10 is parallel to the length direction of the dummy gate trench 7. Figure 1 As shown, in the cross section of the active area, the virtual gate trench 7 has the same depth as the cell trench 10 and is prepared by the same process, that is, the virtual gate trench 7 also penetrates the P-type first base region 141, the N-type carrier storage layer 13 and the P-type second base region 142, and the bottom of the virtual gate trench 7 is located in the N-type substrate 4 below the P-type second base region 142. The material of the virtual gate electrode body 9 can be metal or polysilicon. When the material of the virtual gate electrode body 9 is polysilicon, the virtual gate electrode body 9 is in ohmic contact with the emitter metal 19. The specific form of the ohmic contact between the virtual gate electrode body 9 and the emitter metal 19 can refer to the following description.

[0065] Furthermore, a P-type shielding region 6 is disposed below the cell trench 10 , and the P-type shielding region 6 covers the bottom of the cell trench 10 and contacts the N-type substrate 4 .

[0066] Specifically, the P-type shielding region 6 is located in the N-type substrate 4, the P-type shielding region 6 corresponds to the cell trench 10 one by one, and in the direction from the active region to the terminal region, the length of the P-type shielding region 6 is greater than or equal to the width of the cell trench 10. When the length of the P-type shielding region 6 is equal to the width of the cell trench 10, the P-type shielding region 6 covers the bottom of the cell trench 10. When the IGBT device is reversely turned off, the P-type shielding region 6 can transfer the peak electric field at the trench gate oxide layer 11 at the bottom of the cell trench 10 to the PN junction formed by the P-type shielding region 6 and the N-type substrate 4, thereby effectively reducing the electric field at the trench gate oxide layer 11 at the bottom of the cell trench 10 and improving the reliability of the trench gate oxide layer 11.

[0067] Furthermore, an N-type barrier region 5 is provided below the virtual gate trench 7, and the N-type barrier region 5 covers the bottom of the virtual gate trench 7;

[0068] The N-type barrier region 5 is in contact with the N-type substrate 4 , and the doping concentration of the N-type barrier region 5 is greater than the doping concentration of the N-type substrate 4 .

[0069] Specifically, the N-type barrier region 5 is located in the N-type substrate 4, the N-type barrier region 5 corresponds to the virtual gate trench 7 one by one, and in the direction from the active region to the terminal region, the length of the N-type barrier region 5 is greater than or equal to the width of the virtual gate trench 7. When the length of the N-type barrier region 5 is equal to the width of the virtual gate trench 7, the N-type barrier region 5 covers the bottom of the virtual gate trench 7. When the IGBT is forward-conducted, the N-type barrier region 5 can block part of the holes from flowing from the N-type substrate 4 to the emitter, so as to increase the hole concentration in the N-type substrate 4, thereby enhancing the conductivity modulation effect in the N-type substrate 4 and further reducing the forward conduction voltage drop.

[0070] Furthermore, the P-type first base region 141 is provided with an N-type emitter region 16 and a P-type emitter region 17, wherein:

[0071] The N-type emitter region 16 is located above the P-type emitter region 17 and contacts the P-type emitter region 17;

[0072] The N-type emitter region 16 is in contact with the trench gate unit and / or the dummy gate unit, and the P-type emitter region 17 is isolated from the trench gate unit and / or the dummy gate unit by the P-type first base region 141 .

[0073] The N-type emitter region 16 and the P-type emitter region 17 are both in ohmic contact with the emitter metal 19 .

[0074] like Figure 1 As shown, the N-type emitter region 16 extends vertically from the front side to the back side of the substrate 1, and the junction depth of the N-type emitter region 16 is less than the junction depth of the P-type first base region 141, and the junction depth of the P-type first base region 141 is less than the groove depth of the virtual gate groove 7 and the cell groove 10. In this embodiment, the virtual gate grooves 7 and the cell grooves 10 are arranged alternately, and an N-type emitter region 16 is arranged between adjacent virtual gate grooves 7 and cell grooves 10, one side of the N-type emitter region 16 contacts the outer side wall of the corresponding cell groove 10, and the other side of the N-type emitter region 16 contacts the outer side wall of the corresponding virtual gate groove 7. The P-type emitter region 17 is located in the P-type first base region 141 and below the N-type emitter region 16, and is used to improve the avalanche resistance of the IGBT device. The P-type emitter region 17 contacts the N-type emitter region 16. The doping concentration of the P-type emitter region 17 is greater than the doping concentration of the P-type first base region 141.

[0075] Furthermore, the IGBT device further includes an N-type buffer layer 3 and a P-type collector region 2 corresponding to the back side of the substrate 4;

[0076] The N-type buffer layer 3 is located above the P-type collector region 2 and contacts the P-type collector region 2;

[0077] The P-type collector region 2 is in ohmic contact with a collector metal 1 on the back side of the substrate 4 for forming a collector;

[0078] A diode unit for forming a diode is arranged in the P-type collector region 2, and the diode unit includes a plurality of N-type collector regions 15 in contact with the N-type buffer layer 3;

[0079] The N-type collector region 15 is in ohmic contact with the collector metal 1 on the back side of the N-type substrate 4 for forming a collector.

[0080] Specifically, in the active area, the P-type collector region 2 traverses the back of the substrate 4, and a plurality of N-type collector regions 15 are arranged in the P-type collector region 2. The N-type collector region 15 extends vertically from the back of the substrate 4 to the front of the substrate 4, penetrates the P-type collector region 2 and contacts the N-type buffer layer 3, so as to integrate the diode into the IGBT, effectively improving the utilization rate and power density of the chip area. When the IGBT is reversely conducted, for any N-type collector 15 in the cell, the diode formed by the N-type collector 15, the N-type buffer layer 3, the N-type substrate 4, and the P-type second base region 142 is turned on, providing a circuit for discharging current for the inductive load. Among them, the N-type collector 15, the N-type buffer layer 3 and the N-type substrate 4 together serve as the cathode of the diode, and the P-type second base region 142 serves as the anode of the diode. When the diode unit includes more than one N-type collector region 15, adjacent N-type collector regions 15 are isolated from each other by a P-type collector region, and each N-type collector region 15 forms a diode in the above manner, and multiple diodes formed based on multiple N-type collector regions 15 in the diode unit are connected in parallel.

[0081] The doping concentration of the N-type buffer layer 3 is greater than the doping concentration of the N-type carrier storage layer 13, and the doping concentration of the N-type collector region 15 is greater than the doping concentration of the N-type buffer layer 3. Preferably, the direction from the active region to the terminal region is the length direction, and the direction from the front surface of the substrate 4 to the back surface of the substrate 4 is the thickness direction. The diode unit includes a plurality of N-type collector regions 15 with the same length and thickness, and the plurality of N-type collector regions 15 are uniformly distributed in the P-type collector region 2 along the length direction, and the thickness of the P-type collector region 2 is the same as that of the N-type collector region 15.

[0082] For the high-performance trench IGBT device structure, the utility model provides a method for preparing the high-performance trench IGBT device, which includes a front process performed on the front of the substrate 4 and a back process performed on the back of the substrate 4. Generally, the front process is performed first and then the back process. Figures 2 to 8 An embodiment of the process steps of the high-performance trench IGBT device is shown, and the process steps of the embodiment are described in detail below:

[0083] like Figure 2As shown, an N-type silicon wafer is selected as the substrate 4, and a front process is performed on the front of the substrate 4. The front process includes preparing an active area in the central area of ​​the substrate 4, and etching a cell trench 10 and a virtual gate trench 7 in the active area. The cell trench 10 and the virtual gate trench 7 are alternately arranged in the direction from the terminal area to the active area, and the groove depth of the cell trench 10 is the same as the groove depth of the virtual gate trench 7. The cell trench 10 is used to prepare a P-type shielding area 6 under the cell trench 10 by ion implantation and high-temperature push-junction process, and the virtual gate trench 7 is used to prepare an N-type barrier area 5 under the virtual gate trench 7 by ion implantation and high-temperature push-junction process. In specific implementation, the process conditions of the ion implantation and high-temperature push-junction process can be selected according to actual needs, specifically to meet the preparation of the P-type shielding area 6 and the N-type barrier area 5.

[0084] like Figure 3 As shown, an oxide layer of a preset thickness is deposited in the cell trench 10 and the dummy gate trench 7, and polysilicon is deposited in the cell trench 10 and the dummy gate trench 7 to form a trench gate oxide layer 11 and a trench gate electrode body 12 in the cell trench 10, and a dummy gate oxide layer 8 and a dummy gate electrode body 9 in the dummy gate trench 7. The trench gate electrode body 12 is insulated and isolated from the inner wall of the cell trench 10 by the trench gate oxide layer 11, and the dummy gate electrode body 9 is insulated and isolated from the dummy gate trench 7 by the dummy gate oxide layer 8.

[0085] like Figure 4 As shown, P-type impurities are injected into the substrate 4 from the front side of the substrate 4 to prepare a P-type base region, and N-type impurities are injected into the middle of the P-type base region to invert the middle of the P-type base region into an N-type carrier storage layer 13. The N-type carrier storage layer 13 separates the P-type base region into a P-type first base region 141 and a P-type second base region 142. The distribution form of the P-type first base region 141 and the P-type second base region 142 is the same as above and will not be repeated here. An N-type emitter region 16 is injected into the P-type first base region 141, and the junction depth of the N-type emitter region 16 is less than the junction depth of the P-type first base region 141.

[0086] like Figure 5 As shown, an insulating dielectric layer 18 is deposited on the front side of the substrate 4, and a first contact hole 20 and a second contact hole 21 are etched, wherein the first contact hole 20 is located in the N-type emitter region, and penetrates the N-type emitter region 16 from the front side of the substrate 4, and the second contact hole 21 is located in the virtual gate electrode body 9. The first contact hole 20 is used to inject P-type impurities into the P-type first base region 141 to prepare the P-type emitter region 17. The doping concentration of the P-type emitter region 17 is greater than the doping concentration of the P-type first base region 141.

[0087] like Figure 6As shown, metal is deposited on the front side of the substrate 4 to prepare the emitter metal 19 and the gate metal (not shown in the figure). When the metal is deposited to form the emitter metal 19, the metal is simultaneously deposited in the first contact hole 20 and the second contact hole 21. The metal deposited in the first contact hole 20 is used to make the N-type emitter region 16 and the P-type emitter region 17 ohmically contact with the emitter metal 19 to form an emitter. The metal deposited in the second contact hole 21 is used to make the virtual gate electrode body 9 ohmically contact with the emitter metal 19. The gate metal is in ohmically contact with the trench gate electrode body 12 to form a gate. The specific form of the ohmically contact between the gate metal and the trench gate electrode body 12 can be consistent with the prior art.

[0088] like Figure 7 As shown, a backside process is performed on the backside of the substrate 4 , and an N-type buffer layer 3 is obtained by implantation on the backside of the substrate 4 . The doping concentration of the N-type buffer layer 3 is greater than the doping concentration of the N-type substrate 4 .

[0089] like Figure 8 As shown, a P-type collector region 2 and an N-type collector region 15 are prepared under the N-type buffer layer 3. The distribution of the N-type collector region 15 and the P-type collector region 2 can refer to the above description. A metal layer is deposited on the back of the substrate 4 to form a collector metal 1. The collector metal 1 is in ohmic contact with the P-type collector region 2 and the N-type collector region 15 to form a collector.

[0090] It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the above description refer to directions in the drawings of the present application specification, and the words "front" and "back", "inner" and "outer" refer to directions toward or away from a specific component, respectively. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0091] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A high performance trench IGBT device structure, characterized in that: A substrate comprising a first conductivity type and an active region prepared in a central region of the substrate; The first conductive type substrate is provided with a second conductive type base region corresponding to the front side of the substrate and traversing the active region, and a first conductive type carrier storage layer traversing the second conductive type base region; The first conductive type carrier storage layer separates the second conductive type base region into a second conductive type first base region and a second conductive type second base region, wherein: The second conductivity type first base region is located above the second conductivity type second base region, and the first conductivity type carrier storage layer is isolated from the first conductivity type substrate by the second conductivity type second base region.

2. The high performance trench IGBT device structure according to claim 1, characterized in that: The active area includes a plurality of trench-type cells distributed in parallel, and the trench-type cells include trench gate units; At least one dummy gate unit is disposed in the active area; The front side of the substrate is provided with an emitter metal for forming an emitter and a gate metal for forming a gate; The dummy gate unit is electrically connected to an emitter metal for forming an emitter, and the trench gate unit is electrically connected to a gate metal for forming a gate.

3. The high performance trench IGBT device structure according to claim 2, characterized in that: The trench gate unit comprises a cell trench, a trench gate oxide layer and a trench gate electrode body filled in the cell trench, wherein: The outer sidewall of the cell trench at least contacts the first base region of the second conductivity type; The trench gate electrode body is isolated from the inner wall of the cell trench by a trench gate oxide layer, and the trench gate electrode body is electrically connected to the gate metal.

4. The high performance trench IGBT device structure according to claim 3, characterized in that: A second conductive type shielding region is disposed below the cell trench, and the second conductive type shielding region covers the bottom of the cell trench and contacts the first conductive type substrate.

5. The high performance trench IGBT device structure according to claim 2, characterized in that: The dummy gate unit includes a dummy gate trench, a dummy gate oxide layer, and a dummy gate electrode body filled in the dummy gate trench; The virtual gate electrode body is isolated from the inner wall of the virtual gate trench by a virtual gate oxide layer, and the virtual gate electrode body is electrically connected to the emitter metal.

6. The high performance trench IGBT device structure according to claim 5, characterized in that: A first conductive type barrier region is disposed below the dummy gate trench, and the first conductive type barrier region covers the bottom of the dummy gate trench; The first conductive type barrier region contacts the first conductive type substrate, and the doping concentration of the first conductive type barrier region is greater than the doping concentration of the first conductive type substrate.

7. The high performance trench IGBT device structure according to claim 1, characterized in that: It also includes a first conductive type buffer layer and a second conductive type collector region corresponding to the back side of the substrate; The first conductive type buffer layer is located above the second conductive type collector region and contacts the second conductive type collector region; The second conductive type collector region is in ohmic contact with a collector metal on the back side of the substrate for forming a collector.

8. The high performance trench IGBT device structure according to claim 7, characterized in that: A diode unit for forming a diode is arranged in the second conductive type collector region, and the diode unit includes a plurality of first conductive type collector regions in contact with the first conductive type buffer layer; The first conductive type collector region is in ohmic contact with a collector metal on the back side of the substrate for forming a collector.

9. The high performance trench IGBT device structure according to claim 2, characterized in that: The second conductive type first base region is provided with a first conductive type emitter region and a second conductive type emitter region, wherein: The first conductive type emitter region is located above the second conductive type emitter region and contacts the second conductive type emitter region; The first conductive type emitter region is in contact with the trench gate unit and / or the dummy gate unit, and the second conductive type emitter region is isolated from the trench gate unit and / or the dummy gate unit by the second conductive type first base region; The first conductive type emitter region and the second conductive type emitter region are both in ohmic contact with the emitter metal.

10. The high performance trench IGBT device structure according to any one of claims 1 to 9, characterized in that: The doping concentration of the first conductive type carrier storage layer is greater than the doping concentration of the first conductive type substrate; The thickness of the second conductivity type first base region is not less than the thickness of the second conductivity type second base region.

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