DPU chip and electronic equipment
By designing multiple acceleration units and on-chip networks in the DPU chip, efficient forwarding and management of accelerated data is achieved, and complex communication problems of DPU acceleration units in multiple business scenarios are solved, and hardware efficiency and communication capabilities are improved.
Patent Information
- Application Number
- CN202421387479.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-18
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2034-06-18
AI Technical Summary
In the prior art, in multiple business scenarios, the communication method between DPU acceleration units cannot meet the needs of large amount of acceleration data and frequent interactions, resulting in complex overall hardware configuration.
A DPU chip is designed, including multiple acceleration units and on-chip networks, and accelerated data forwarding and management through routing nodes and routing units, establish independent data channels and backup data channels to ensure efficient data communication.
Centrally manages data forwarding of DPU chips through on-chip networks, simplifies hardware configuration, improves operating speed and forwarding efficiency, and supports efficient communication between accelerated units in multiple business scenarios.
Smart Images
Figure CN222672324U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the utility model relate to the field of chip technology, and in particular to a DPU chip and an electronic device. Background Art
[0002] DPU (Data Processing Unit) is a hardware accelerator designed for data-intensive tasks. Compared with traditional CPUs, DPUs focus on optimizing specific types of data processing tasks, such as network packet processing, storage operations, security protocol processing, etc., to improve performance and efficiency. The design concept of DPU is to offload certain tasks from the main CPU, allowing it to focus on other computing tasks while processing multiple data streams or tasks through highly parallel processing capabilities. DPUs generally have better energy efficiency because they are optimized for specific tasks and can perform these tasks more energy-efficiently.
[0003] Another important feature of DPUs is their programmability, which means that users can adjust the behavior of the DPU as needed to meet specific application requirements. In addition, DPUs can be integrated into a variety of devices, including servers, network equipment, and storage devices, providing these devices with enhanced data processing capabilities. DPUs also have the potential to improve system security because they can handle encryption and decryption operations to ensure the security of data transmission.
[0004] As the amount of data continues to grow and the demand for real-time processing capabilities increases, DPUs, as an emerging hardware accelerator, are becoming increasingly important. Their development is accompanied by corresponding software tools and APIs to support developers to fully utilize the hardware capabilities of DPUs. DPUs have a wide range of application scenarios, including network processing, storage systems, reasoning processes of machine learning models, and security applications, providing strong support for modern data centers and various computing-intensive applications.
[0005] Currently, DPU supports multiple business scenarios and multiple acceleration units are designed. The acceleration units for various business scenarios need to interact with a large number of data packets and need to communicate with the Internet.
[0006] However, in the prior art, the communication method between different acceleration units is that the upstream acceleration unit records the downstream acceleration unit by adding a destination field to the acceleration data, and uses the destination field to send the acceleration data to the downstream acceleration unit. However, the above method is only applicable to a single business scenario. In a multi-business scenario, there is a large amount of acceleration data and frequent interactions. The above method cannot meet the communication needs between acceleration units in multiple business scenarios. Even if some methods are used to meet the acceleration units in multiple business scenarios, the overall hardware configuration is relatively complicated. Utility Model Content
[0007] In view of this, an embodiment of the present invention provides a DPU chip and an electronic device to at least partially solve the above problems.
[0008] According to a first aspect of an embodiment of the utility model, a DPU chip is provided, including:
[0009] A plurality of acceleration units, each of which includes a transceiver and a routing end, each of which is used to receive data through the transceiver, process the received data according to the data acceleration type of the acceleration unit, and obtain accelerated data sent from the transceiver, wherein the plurality of acceleration units include at least two acceleration units selected from a media access control acceleration unit, a peripheral bus, a direct memory access unit, a network processor, a local area network, a database offload acceleration engine, a double data rate SDRAM unit, and a storage acceleration unit;
[0010] The on-chip network includes multiple routing nodes and routing units connected to the multiple routing nodes, and is respectively connected to the routing ends of the multiple acceleration units. The on-chip network is used to receive upstream acceleration data from an upstream acceleration unit corresponding to a data acceleration task among the multiple acceleration units via the routing nodes corresponding to the upstream acceleration unit, determine a downstream acceleration unit corresponding to the data acceleration task among the multiple acceleration units through the routing units, and send the upstream acceleration data to the downstream acceleration unit via the routing nodes corresponding to the downstream acceleration unit.
[0011] In some embodiments, the routing unit is specifically used to: parse the upstream acceleration data to obtain pre-configured downstream task indication information, and determine the downstream acceleration unit according to the downstream task indication information.
[0012] In some embodiments, the routing unit includes at least one storage unit, and the routing unit is specifically used to: determine a first number of upstream acceleration units and a second number of downstream acceleration units, connect the routing nodes corresponding to the upstream acceleration units and the downstream acceleration units to at least one storage unit, establish at least one independent data channel between the upstream acceleration unit and the downstream acceleration unit, and the at least one storage unit is used to independently cache the acceleration data queues between the upstream acceleration unit and the downstream acceleration unit.
[0013] In some embodiments, the routing unit is specifically configured to: if the first number is equal to the second number, establish the same number of the independent data channels as the first number or the second number.
[0014] In some embodiments, the routing unit is specifically configured to: if the first number is not equal to the second number, establish the same number of the independent data channels as the second number.
[0015] In some embodiments, the DPU chip further includes a peripheral bus, which is connected between the downstream acceleration unit and an external host, and the peripheral bus is used to send downstream acceleration data received from the downstream acceleration unit to the external host.
[0016] In some embodiments, the routing unit is further used to: establish a backup data channel outside the at least one independent data channel, the backup data channel is used to send the upstream acceleration data received from the upstream acceleration unit to the downstream acceleration unit,
[0017] In some embodiments, the routing unit is further used to: detect a channel status of the at least one independent data channel, and switch from the at least one independent data channel to the backup data channel when the channel status indicates that the at least one independent data channel is abnormal.
[0018] In some embodiments, the DPU chip further includes:
[0019] A packaging shell, comprising a plurality of pins, wherein the plurality of pins are connected to the transceiver ends of the plurality of acceleration units;
[0020] Wherein, the multiple acceleration units and the on-chip network are packaged in the packaging shell.
[0021] According to a second aspect of an embodiment of the utility model, an electronic device is provided, comprising: a host and the DPU chip described in the first aspect.
[0022] According to the DPU chip provided by the embodiment of the utility model, by setting up multiple acceleration units, each acceleration unit performs different acceleration tasks, and can execute acceleration tasks in parallel, thereby supporting multiple business scenarios. At the same time, upstream acceleration data is received through the routing nodes on the on-chip network, and the acceleration data is sent to the downstream through the routing units. The data forwarding of the DPU chip can be centrally managed through the on-chip network, which simplifies the overall hardware configuration while ensuring the operating speed and forwarding efficiency of the DPU chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the utility model. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0024] Figure 1 A schematic diagram of the structure of a DPU chip applicable to an embodiment of the utility model;
[0025] Figure 2 The structure diagram of the network on chip according to the embodiment of the utility model is as follows
[0026] Figure 3 This is another DPU chip structure diagram according to an embodiment of the utility model;
[0027] Figure 4 It is a flowchart of a data transmission method based on a DPU chip according to an embodiment of the utility model;
[0028] Figure 5 The figure is a schematic diagram of the structure of an electronic device according to an embodiment of the utility model. DETAILED DESCRIPTION
[0029] In order to make those skilled in the art better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.
[0030] The specific implementation of the embodiment of the present utility model is further described below in conjunction with the accompanying drawings of the embodiment of the present utility model.
[0031] The utility model embodiment provides a DPU chip, specifically as follows Figure 1As shown, the DPU chip includes multiple acceleration units and an on-chip network, wherein each acceleration unit includes a transceiver and a routing end, and is respectively connected to the on-chip network. The acceleration unit receives data based on the receiving end, and processes the received data according to the data acceleration type of the acceleration unit to obtain accelerated data, and sends the accelerated data to the on-chip network through the routing end. Specifically, the multiple units include but are not limited to a media access control acceleration unit (MAC), a peripheral bus (PCIE, Poriphoral Component Intorconnect Express), a direct memory access unit (DMA, Direct Memory Access), a network processor (NP, Network processor), a local area network (K2Pro-LAN), a database offload acceleration engine (DOE, Database Offload Engine), a double data rate SDRAM unit (DDR, Double Data Rate SDRAM) and a storage acceleration unit (NVME-of, Non-Volatile Memory express ovor Fabrics).
[0032] Specifically, the media access range control acceleration unit (MAC) is responsible for media access control. The first end of the media access range control acceleration unit is connected to an external network device through two Ethernet interface SERDES, and the second end is connected to a network processor (NP), and is connected to a routing unit of an on-chip network through the network processor (NP). The Ethernet interface SERDES can include 10G, 25G, 40G, 50G, 100G and other rates.
[0033] Specifically, the bus acceleration unit (PCIE, Poriphoral Component Intorconnect Express) is used to provide a host communication interface for the acceleration unit. The first end is connected to the host through the physical layer, the second end is connected to the acceleration unit through the AXI4 bus interface of the standard protocol, and the third end is connected to the on-chip network to achieve high-speed, high-bandwidth, and low-latency data communication between the host and the acceleration unit.
[0034] Specifically, a direct memory access unit (DMA) is used to increase the transmission speed, a first end of which is connected to a bus acceleration unit (PCIE, Poriphoral Component Intorconnect Express), and a second end of which is connected to an on-chip network.
[0035] Specifically, the network processor (NP) is used to parse, identify and process received network data packets, and can specifically implement functions such as packet processing, protocol parsing, and table entry lookup. Its first end is connected to the on-chip network, and its second end is connected to the media access range control acceleration unit (MAC).
[0036] Specifically, the local area network (K2Pro-LAN) is used to implement network layer 2 addressing, network virtualization, and load balancing calculations. Its first end is connected to the media access range control acceleration unit (MAC), and the second end is connected to the on-chip network.
[0037] Specifically, the database offload acceleration engine (DOE) is used to collect, store, process and other functions of real-time processed data, and its first end is connected to the network processor (NP), the second end is connected to the double data rate SDRAM unit (DDR), and the third end is connected to the on-chip network. Further, in the embodiment of the utility model, the database offload acceleration engine (DOE) is used to provide flow table offloading for the network processor (NP).
[0038] Specifically, a double data rate SDRAM unit (DDR) is used for fast data transmission, a first end of which is connected to an external memory through a physical layer, a second end is connected to a database offload acceleration engine (DOE), and a third end is connected to an on-chip network, wherein the double data rate SDRAM unit (DDR) can be set to multiple.
[0039] Specifically, a storage acceleration unit (NVME-of, Non-Volatile Memory express ovor Fabrics) is used to establish shared register access between two external hosts, a first end of which is connected to the on-chip network, and a second end is connected to a bus acceleration unit (PCIE, Poriphoral Component Intorconnect Express).
[0040] Specifically, a remote memory acceleration unit (RDMA) is used to achieve remote communication with an external memory, a first end of which is connected to an on-chip network, and a second end of which is connected to an external memory through a double data rate SDRAM unit (DDR, Double Data Rate SDRAM).
[0041] The on-chip network is connected to each acceleration unit, and is used to receive the upstream acceleration data sent by the upstream acceleration unit corresponding to the data acceleration task, and determine the downstream acceleration unit corresponding to the data acceleration task according to the upstream acceleration data, and further send the upstream acceleration data to the corresponding downstream acceleration unit. Specifically, Figure 2 As shown, the slice network includes multiple routing nodes R and routing units. The routing node R is used to receive acceleration data sent by the acceleration unit through the routing end. The routing unit determines the downstream acceleration unit corresponding to the data acceleration task among the multiple acceleration units, and sends the upstream acceleration data to the downstream acceleration unit via the routing node corresponding to the downstream acceleration unit.
[0042] In one example, the upstream acceleration unit in the embodiment of the present invention is an acceleration unit that needs to send acceleration data, and the downstream acceleration unit is an acceleration unit that needs to receive acceleration data.
[0043] Specifically, for example, the data acceleration task is direct memory reading, and the acceleration unit corresponding to the data acceleration task determined by the on-chip network is a direct memory reading acceleration unit, and then the on-chip network sends the upstream acceleration data to the direct memory reading unit.
[0044] According to the DPU chip provided by the embodiment of the utility model, by setting up multiple acceleration units, acceleration tasks can be executed in parallel, and at the same time, upstream acceleration data can be received through the routing nodes on the on-chip network, and the acceleration data can be sent to the downstream through the routing units. The data forwarding of the DPU chip can be centrally managed through the on-chip network, thereby improving the operating speed and forwarding efficiency of the DPU chip.
[0045] Furthermore, if Figure 3As shown, an embodiment of the utility model provides another DPU chip, wherein a bus acceleration unit (PCIE, Poriphoral Component Intorconnect Express) may include a first bus acceleration subunit (PCIE_1) and a second bus acceleration subunit (PCIE_2), the first bus acceleration subunit (PCIE_1) is used to connect to a first host, and the second bus acceleration subunit is used to connect to a second host.
[0046] The number of direct memory access units (DMA) can be set to multiple, which is consistent with the number of bus acceleration subunits.
[0047] Furthermore, the DPU chip of the embodiment of the utility model may also include a clock unit (CLOCK) for performing clock synchronization on each module in the DPU chip.
[0048] Furthermore, the DPU chip of the embodiment of the utility model may also include a reset unit (RESET) for resetting the DPU chip.
[0049] Furthermore, the DPU chip of the embodiment of the utility model may also include a control unit and a parameter storage unit (FLASH_CTRL), wherein the control unit includes a control subunit (CTRL_SYS) and an embedded management processor (EPU), and the control subunit is also directly connected to the microcontroller through a serial peripheral interface (QSPI).
[0050] Furthermore, the routing unit of the embodiment of the utility model is also used to parse the upstream acceleration data, obtain the pre-configured downstream task indication information, and determine the downstream acceleration unit according to the downstream task indication information. Specifically, after receiving the upstream acceleration data, the on-chip network parses the upstream acceleration data, determines the pre-configured downstream task indication information, and then determines the task that the downstream acceleration unit needs to perform, and then determines the acceleration unit. For example, the on-chip network parses the upstream acceleration data, and determines that the downstream task indication information is directly written to the host memory, and then the downstream acceleration unit determined by the on-chip network is a direct memory access unit (DMA, Direct Memory Access), and then the on-chip network sends the upstream data packet to the direct memory access unit (DMA, Direct Memory Access).
[0051] Furthermore, the routing unit of the embodiment of the utility model includes at least one storage unit, and the routing unit is also used to determine the first number of upstream acceleration units and the second number of downstream acceleration units, establish at least one independent data channel between the upstream acceleration unit and the downstream acceleration unit, and send the upstream acceleration data received from the upstream acceleration unit to the downstream acceleration unit through the at least one independent data channel. Specifically, before transmitting the upstream data packet, the routing unit also obtains the first number of upstream acceleration units and the second number of downstream acceleration units, and establishes at least one independent data channel based on the first number and the second number, and further, transmits the upstream data packet using the established at least one independent data channel.
[0052] In one example, if the routing unit determines that the first number is equal to the second number, the routing unit establishes independent data channels that are the same as the first number or the second number. For example, if the first number and the second number are both 3, the on-chip network establishes 3 independent data channels.
[0053] In one example, if the routing unit determines that the first number is not equal to the second number, the routing unit establishes independent data channels equal to the second number. For example, if the first number is 1 and the second number is 3, the routing unit establishes 3 independent data channels.
[0054] Furthermore, the routing unit of the embodiment of the utility model is also used to establish a backup data channel, which sends the upstream acceleration data received from the upstream acceleration unit to the downstream acceleration unit to complete the data transmission through the backup data transmission channel, thereby improving the stability of data transmission. Specifically, the routing unit detects the channel status of at least one independent data channel, and switches from at least one independent data channel to the backup data channel when the channel status indicates that at least one independent data channel is abnormal. Please continue to refer to
[0055] Figure 3 As shown, the dotted line in the figure represents the spare data channel.
[0056] In one example, the routing unit may detect the state of the independent data channel by detecting the transmission time of the acceleration unit sending the upstream acceleration data, and when the transmission time exceeds a preset threshold, the on-chip network determines that the transmission has timed out.
[0057] In one example, the DPU chip of the embodiment of the utility model further includes: a packaging shell, including multiple pins, wherein the multiple pins are connected to the transceiver ends of the multiple acceleration units; wherein the multiple acceleration units and the on-chip network are packaged in the packaging shell.
[0058] Furthermore, the embodiment of the utility model also provides a data transmission method based on a DPU chip, which is applied to the DPU chip of the embodiment of the utility model. The specific steps are as follows: Figure 4As shown, including:
[0059] S401, the on-chip network receives upstream acceleration data corresponding to a data acceleration task.
[0060] In an embodiment of the utility model, the upstream acceleration unit processes the received data according to its own data acceleration type to obtain upstream acceleration data. Further, the upstream acceleration unit sends the obtained acceleration data to the on-chip network, and the on-chip network can receive the upstream acceleration data corresponding to the data acceleration task.
[0061] In one example, the data acceleration types of the acceleration unit in the embodiment of the utility model may include low-latency data acceleration transmission, real-time data acceleration transmission, and high-efficiency data acceleration transmission.
[0062] S402, the on-chip network determines a downstream acceleration unit corresponding to the data acceleration task.
[0063] In an embodiment of the utility model, after receiving the upstream acceleration data, the on-chip network determines the downstream acceleration unit corresponding to the data acceleration task according to the upstream acceleration data. Specifically, for example, the data acceleration task is direct memory reading, and the acceleration unit corresponding to the data acceleration task determined by the on-chip network is the direct memory reading acceleration unit, and then the on-chip network sends the upstream acceleration data to the direct memory reading unit.
[0064] S403, the on-chip network sends the upstream acceleration data to the downstream acceleration unit.
[0065] In the embodiment of the utility model, after determining the downstream acceleration unit, the on-chip network transmits the upstream acceleration data to the downstream acceleration unit to complete the data communication between different acceleration units.
[0066] Further, refer to Figure 5 , shows a schematic diagram of the structure of an electronic device according to an embodiment of the utility model. The specific embodiment of the utility model does not limit the specific implementation of the electronic device.
[0067] like Figure 5 As shown, the electronic device may include: a processor (processor) 502 , a communication interface (Communications Intorface) 504 , a memory (memory) 506 , and a communication bus 508 .
[0068] in:
[0069] The processor 502 , the communication interface 504 , and the memory 506 communicate with each other via a communication bus 508 .
[0070] The communication interface 504 is used to communicate with other electronic devices or servers.
[0071] The processor 502 is used to execute the program 510, and specifically can execute the relevant steps in the above-mentioned DPU chip-based data transmission method embodiment.
[0072] Specifically, the program 510 may include program codes, which include computer operation instructions.
[0073] The processor 502 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiment of the present utility model. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.
[0074] The memory 506 is used to store the program 510. The memory 506 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.
[0075] The program 510 may be specifically configured to enable the processor 502 to perform the following operations:
[0076] In an optional implementation, the program 510 is also used to enable the processor 502 to implement each step in the program 510. The specific implementation can refer to the corresponding steps and corresponding descriptions in the units in the above-mentioned DPU chip-based data transmission method embodiment, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, which will not be repeated here.
[0077] An embodiment of the utility model further provides a computer program product, including computer instructions, which instruct a computing device to execute operations corresponding to the DPU chip-based data transmission method in the above method embodiment.
[0078] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the utility model can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the utility model.
[0079] The above-mentioned method according to the embodiment of the utility model can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the DPU chip-based data transmission method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the DPU chip-based data transmission method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the DPU chip-based data transmission method shown herein.
[0080] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present utility model.
[0081] The above implementation methods are only used to illustrate the embodiments of the present utility model, and are not limitations of the embodiments of the present utility model. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present utility model. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present utility model. The patent protection scope of the embodiments of the present utility model should be limited by the claims.
Claims
1. A DPU chip, characterized in that: include: A plurality of acceleration units, each of which includes a transceiver and a routing end, each of which is used to receive data through the transceiver, and process the received data according to the data acceleration type of the acceleration unit to obtain accelerated data sent from the transceiver, wherein the plurality of acceleration units include at least two acceleration units selected from a media access control acceleration unit, a peripheral bus, a direct memory access unit, a network processor, a local area network, a database offload acceleration engine, a double data rate SDRAM unit, a storage acceleration unit, and a remote storage acceleration unit; The on-chip network includes multiple routing nodes and routing units connected to the multiple routing nodes, and is respectively connected to the routing ends of the multiple acceleration units. The on-chip network is used to receive upstream acceleration data from an upstream acceleration unit corresponding to a data acceleration task among the multiple acceleration units via the routing nodes corresponding to the upstream acceleration unit, determine a downstream acceleration unit corresponding to the data acceleration task among the multiple acceleration units through the routing units, and send the upstream acceleration data to the downstream acceleration unit via the routing nodes corresponding to the downstream acceleration unit.
2. The DPU chip according to claim 1, characterized in that: The routing unit is specifically used to: parse the upstream acceleration data to obtain pre-configured downstream task indication information, and determine the downstream acceleration unit according to the downstream task indication information.
3. The DPU chip according to claim 2, characterized in that: The routing unit includes at least one storage unit, and the routing unit is specifically used to: determine a first number of upstream acceleration units and a second number of downstream acceleration units, connect routing nodes corresponding to the upstream acceleration units and the downstream acceleration units to at least one storage unit, establish at least one independent data channel between the upstream acceleration unit and the downstream acceleration unit, and the at least one storage unit is used to independently cache acceleration data queues between the upstream acceleration unit and the downstream acceleration unit.
4. The DPU chip according to claim 3, characterized in that: The routing unit is specifically configured to: if the first number is equal to the second number, establish the same number of independent data channels as the first number or the second number.
5. The DPU chip according to claim 3, characterized in that: The routing unit is specifically configured to establish, if the first number is not equal to the second number, the same number of independent data channels as the second number.
6. The DPU chip according to claim 1, characterized in that: The DPU chip also includes a peripheral bus connected between the downstream acceleration unit and an external host, and the peripheral bus is used to send downstream acceleration data received from the downstream acceleration unit to the external host.
7. The DPU chip according to claim 3, characterized in that: The routing unit is further used to establish a backup data channel outside the at least one independent data channel, and the backup data channel is used to send the upstream acceleration data received from the upstream acceleration unit to the downstream acceleration unit.
8. The DPU chip according to claim 7, characterized in that: The routing unit is further configured to detect a channel status of the at least one independent data channel, and switch from the at least one independent data channel to the standby data channel when the channel status indicates that the at least one independent data channel is abnormal.
9. The DPU chip according to claim 1, characterized in that: The DPU chip also includes: A packaging shell, comprising a plurality of pins, wherein the plurality of pins are connected to the transceiver ends of the plurality of acceleration units; Wherein, the multiple acceleration units and the on-chip network are packaged in the packaging shell.
10. An electronic device, characterized in that: include: A host and a DPU chip according to any one of claims 1-9.