Memory
By vertically nesting write transistors and read transistors in the DRAM memory cell and having the semiconductor layer of the write transistor located in the gate slot of the read transistor, the problems of low DRAM storage density and complex process are solved, and higher storage density and lower production costs are achieved.
Patent Information
- Application Number
- CN202421387122.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-17
- Publication Date
- 2025-03-25
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The storage density of DRAM storage units is low and the production process is complex, making it difficult to reduce process technology difficulty while ensuring storage density.
Direct connection between the write transistor and the read transistor is achieved by nesting a portion of the CAA-type write transistor vertically inside the CAA-type read transistor in the memory cell and placing the semiconductor layer of the write transistor in the gate slot of the read transistor.
While ensuring storage density, the horizontal area and vertical height of the storage unit are reduced, thereby increasing the storage density, reducing the requirements for lithography processes during the production process, improving product yields and reducing production costs.