Radar receiver

Abstract

The utility model provides a radar receiver. The radar receiver comprises at least one group of receiving antennas; a clock chip; the sampling circuit is controlled to perform two-channel sampling on the analog intermediate-frequency signal according to different sampling frequencies under a reference clock provided by the clock chip to form two groups of sampling signals with different sampling rates; a group of ADC circuits connected with the sampling circuit and used for converting the two groups of analog sampling signals at a sampling rate configured by the sampling circuit so as to form two groups of digital signals; and the digital signal processor is configured to perform fast Fourier transform processing on digital signals formed by the two groups of analog sampling signals with different sampling rates so as to determine the distance of the measured object. According to the method, fast Fourier transform processing is carried out on two groups of fast and slow digital signals to obtain the moving distance of a moving target, and then a corresponding time difference is obtained according to a sampling period, so that a corresponding moving speed is calculated.

Description

Technical Field

[0001] This utility model relates to the field of radar technology, and in particular to a radar receiver. Background Technology

[0002] The radar receiver is a crucial component of a radar system. Its main functions include pre-selecting, amplifying, frequency-converting, filtering, demodulating, and digitizing the weak signals received by the radar antenna. Simultaneously, it suppresses external interference clutter and internal noise, ensuring the echo signal retains as much target information as possible for further signal and data processing. Currently, data processing utilizes digital signal processors (DSPs). Their advantage lies in using intermediate frequency (IF) signals for ranging. Furthermore, to detect objects at different distances, a Fast Fourier Transform (FFT) can be performed on the IF signal, with each peak representing an obstacle at a corresponding distance. However, this method yields significant distance measurements, especially with moving targets, failing to meet operational requirements. Utility Model Content

[0003] Therefore, the main objective of this utility model is to provide a radar receiver.

[0004] The technical solution adopted in this utility model is as follows:

[0005] Radar receiver, including:

[0006] At least one set of receiving antennas;

[0007] Clock chip;

[0008] The sampling circuit, under the reference clock provided by the clock chip, controls the sampling circuit to perform two-channel sampling of the analog intermediate frequency signal at different sampling frequencies, forming two sets of sampling signals with different sampling rates;

[0009] An ADC circuit, connected to the sampling circuit, is used to convert two sets of analog sampled signals at a sampling rate configured in the sampling circuit to form two sets of digital signals.

[0010] A digital signal processor is configured to perform fast Fourier transform processing on digital signals formed by two sets of analog sampling signals with different sampling rates, thereby determining the distance to the object being measured.

[0011] Furthermore, the sampling circuit includes sampling units arranged in parallel, the sampling unit comprising:

[0012] A pre-amplified switched-capacitor integrator is configured to have different sampling frequencies;

[0013] The sampling capacitor, coupled to the back end of the pre-switched capacitor integrator, is used for independent channel sampling of analog intermediate frequency signals.

[0014] A post-connected switched-capacitor integrator, coupled to the back end of the sampling capacitor, is used to integrate the signals sampled from the independent channels.

[0015] Furthermore, the analog intermediate frequency signal is obtained by a processing circuit.

[0016] Furthermore, the processing circuit includes:

[0017] A mixer is used to mix the echo signal received by the receiving antenna with the transmitted signal transmitted by the transmitting antenna to obtain a mixed signal.

[0018] A low-pass filter circuit, connected to the mixer, is used to perform low-pass filtering on the mixed signal to obtain a low-intermediate frequency signal;

[0019] An intermediate frequency amplifier, connected to the low-pass filter circuit, is used to amplify the low-intermediate frequency signal to obtain an analog intermediate frequency signal.

[0020] Furthermore, the echo signal is obtained by amplifying the received transmitted signal through a low-noise amplifier using a receiving antenna.

[0021] Furthermore, the ADC circuit includes:

[0022] The resistor voltage divider unit consists of several resistor voltage dividers connected in parallel. These resistor voltage dividers are used to quantize the input reference voltage threshold into multiple corresponding reference comparison voltages.

[0023] The voltage comparator unit consists of several voltage comparators. One end of each voltage comparator is connected to the same capacitor, and the other end is connected together as the input terminal of the sample-and-hold analog voltage.

[0024] A sample-and-hold circuit, coupled to the input of the sample-and-hold analog voltage, is used to sample the analog input signal separately to obtain several converted sample signals. The converted sample signals are compared with the reference comparison voltage formed by the resistor divider unit. After the comparison is completed, the signal is input to the corresponding register and then sent from the register to the encoder. The encoder forms a binary digital signal.

[0025] Furthermore, several parallel resistor dividers quantize the input reference voltage threshold into multiple corresponding, successively increasing reference comparison voltages according to a set rule.

[0026] Furthermore, the setting rule is to quantify the reference comparison voltage by successively increasing the set reference voltage threshold according to the rated coefficient.

[0027] Furthermore, the voltage divider includes a voltage divider resistor R1 and a voltage divider resistor R2.

[0028] Furthermore, based on the parallel configuration of several parallel resistor voltage dividers, the total resistance value of the voltage dividing resistors R1 and R2 contained in each resistor voltage divider remains unchanged, and according to the parallel configuration, the voltage dividing resistors R1 and R2 change accordingly with the same resistance value.

[0029] This application utilizes a sampling circuit to sample an analog intermediate frequency signal at different sampling frequencies using two channels, forming two sets of sampled signals with different sampling rates. These two sets of signals are then converted into digital signals by an ADC circuit. A digital signal processor then performs a Fast Fourier Transform (FFT) on the two sets of digital signals, one fast and one slow, to obtain two corresponding results. The distance to the target is calculated by averaging these two results. For static targets, this technique can significantly improve the accuracy of distance measurement. For moving objects, the moving distance can be obtained by performing a FFT on the two sets of digital signals (one fast and one slow). The time difference between these two sets of signals is then calculated based on the sampling period, allowing for the determination of the target's speed. Attached Figure Description

[0030] The following figures are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0031] Figure 1 This is a general schematic diagram of the framework of this utility model;

[0032] Figure 2 This is a schematic diagram of the sampling circuit in this utility model;

[0033] Figure 3 This is a schematic diagram of the processing circuit in this utility model.

[0034] Figure 4 This is a schematic diagram of the ADC circuit in this utility model. Detailed Implementation

[0035] To make the objectives, technical solutions, design methods, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this utility model.

[0036] Reference Figure 1 The present invention provides a technical solution as follows:

[0037] Radar receiver, including:

[0038] At least one set of receiving antennas;

[0039] Clock chip;

[0040] The sampling circuit, under the reference clock provided by the clock chip, controls the sampling circuit to perform two-channel sampling of the analog intermediate frequency signal at different sampling frequencies, forming two sets of sampling signals with different sampling rates;

[0041] An ADC circuit, connected to the sampling circuit, is used to convert two sets of analog sampled signals at a sampling rate configured in the sampling circuit to form two sets of digital signals.

[0042] A digital signal processor is configured to perform fast Fourier transform processing on digital signals formed by two sets of analog sampling signals with different sampling rates, thereby determining the distance to the object being measured.

[0043] In the above, the sampling circuit includes sampling units arranged in parallel, and the sampling unit includes:

[0044] A pre-amplified switched-capacitor integrator is configured to have different sampling frequencies;

[0045] The sampling capacitor, coupled to the back end of the pre-switched capacitor integrator, is used for independent channel sampling of analog intermediate frequency signals.

[0046] A post-connected switched-capacitor integrator, coupled to the back end of the sampling capacitor, is used to integrate the signals sampled from the independent channels.

[0047] Reference Figure 2 The input signal is sampled by two different sampling capacitors. Sampling capacitor C1 samples in the sampling phase of the pre-switched capacitor integrator ψ1 and integrates in the integration phase of the post-switched capacitor integrator ψ2; sampling capacitor C2 samples in the sampling phase of the pre-switched capacitor integrator ψ3 and integrates in the integration phase of the post-switched capacitor integrator ψ4. Therefore, sampling and integration exist simultaneously in both phases of the clock, and the effective sampling frequency is thus doubled.

[0048] In the above, the analog intermediate frequency signal is obtained by the processing circuit.

[0049] Reference Figure 3 In the above, the processing circuit includes:

[0050] A mixer is used to mix the echo signal received by the receiving antenna with the transmitted signal transmitted by the transmitting antenna to obtain a mixed signal.

[0051] A low-pass filter circuit, connected to the mixer, is used to perform low-pass filtering on the mixed signal to obtain a low-intermediate frequency signal;

[0052] An intermediate frequency amplifier, connected to the low-pass filter circuit, is used to amplify the low-intermediate frequency signal to obtain an analog intermediate frequency signal.

[0053] In the above, the function of the low-pass filter circuit is to filter out the high-frequency components in the mixing signal, leaving only the low-frequency components in the differential signal. The low-IF signal is then amplified by the intermediate frequency amplifier to finally obtain the analog intermediate frequency signal.

[0054] In the above, the echo signal is obtained by amplifying the received transmitted signal through a low-noise amplifier using a receiving antenna.

[0055] Reference Figure 4 In the above, the ADC circuit includes:

[0056] The resistor voltage divider unit consists of several resistor voltage dividers connected in parallel. These resistor voltage dividers are used to quantize the input reference voltage threshold into multiple corresponding reference comparison voltages.

[0057] The voltage comparator unit consists of several voltage comparators. One end of each voltage comparator is connected to the same capacitor, and the other end is connected together as the input terminal of the sample-and-hold analog voltage.

[0058] A sample-and-hold circuit, coupled to the input of the sample-and-hold analog voltage, is used to sample the analog input signal separately to obtain several converted sample signals. The converted sample signals are compared with the reference comparison voltage formed by the resistor divider unit. After the comparison is completed, the signal is input to the corresponding register and then sent from the register to the encoder. The encoder forms a binary digital signal.

[0059] Furthermore, several parallel resistor dividers quantize the input reference voltage threshold into multiple corresponding, successively increasing reference comparison voltages according to a set rule.

[0060] Furthermore, the setting rule is to quantify the reference comparison voltage by successively increasing the set reference voltage threshold according to the rated coefficient.

[0061] Furthermore, the voltage divider includes a voltage divider resistor R1 and a voltage divider resistor R2.

[0062] Furthermore, based on the parallel configuration of several parallel resistor voltage dividers, the total resistance value of the voltage dividing resistors R1 and R2 contained in each resistor voltage divider remains unchanged, and according to the parallel configuration, the voltage dividing resistors R1 and R2 change accordingly with the same resistance value.

[0063] In this application, the resistive voltage divider is used to quantize the input reference voltage threshold into five comparison reference voltages, U1-U5. The specific values ​​of U1-U5 are U1=1Uf / 12, U2=3Uf / 12, U3=5Uf / 12, U4=7Uf / 12, and U5=9Uf / 12, respectively, where Uf is the input reference voltage.

[0064] In this application, the reference voltage threshold setting method is: R2 / (R1+R2). Assuming R1+R2 is 12Ω, based on the parallel connection of several parallel resistor voltage dividers, when setting U1, R1 is set to 11Ω and R2 is set to 1Ω; when setting U2, R1 is set to 9Ω and R2 is set to 2Ω; when setting U3, R1 is set to 7Ω and R2 is set to 5Ω; when setting U4, R1 is set to 5Ω and R2 is set to 7Ω; when setting U5, R1 is set to 3Ω and R2 is set to 9Ω.

[0065] This application utilizes a sampling circuit to sample an analog intermediate frequency signal at different sampling frequencies using two channels, forming two sets of sampling signals with different sampling rates. These two sets of signals are then converted into digital signals by an ADC circuit, and subsequently processed by a digital signal processor using a fast Fourier transform (FFT) on each set of digital signals, yielding two corresponding results. The distance to the target is calculated by averaging these two results. For static targets, this technique can significantly improve the accuracy of distance measurement. For moving objects, the moving distance can be obtained by performing a FFT on the two sets of digital signals (one fast and one slow), and the corresponding time difference can be calculated based on the sampling period to determine the moving speed. The various embodiments of this utility model have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the various embodiments, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A radar receiver, characterized by include: At least one set of receiving antennas; Clock chip; The sampling circuit, under the reference clock provided by the clock chip, controls the sampling circuit to perform two-channel sampling of the analog intermediate frequency signal at different sampling frequencies, forming two sets of sampling signals with different sampling rates; An ADC circuit, connected to the sampling circuit, is used to convert two sets of analog sampled signals at a sampling rate configured in the sampling circuit to form two sets of digital signals. A digital signal processor is configured to perform fast Fourier transform processing on digital signals formed by two sets of analog sampling signals with different sampling rates, thereby determining the distance to the object being measured.

2. The radar receiver of claim 1, wherein, The sampling circuit includes sampling units connected in parallel, and the sampling unit includes: A pre-amplified switched-capacitor integrator is configured to have different sampling frequencies; The sampling capacitor, coupled to the back end of the pre-switched capacitor integrator, is used for independent channel sampling of analog intermediate frequency signals. A post-connected switched-capacitor integrator, coupled to the back end of the sampling capacitor, is used to integrate the signals sampled from the independent channels.

3. The radar receiver of claim 1, wherein, The analog intermediate frequency signal is obtained by the processing circuit.

4. The radar receiver of claim 3, wherein, The processing circuit includes: A mixer is used to mix the echo signal received by the receiving antenna with the transmitted signal transmitted by the transmitting antenna to obtain a mixed signal. A low-pass filter circuit, connected to the mixer, is used to perform low-pass filtering on the mixed signal to obtain a low-intermediate frequency signal; An intermediate frequency amplifier, connected to the low-pass filter circuit, is used to amplify the low-intermediate frequency signal to obtain an analog intermediate frequency signal.

5. The radar receiver of claim 4, wherein, The echo signal is obtained by amplifying the received transmitted signal through a low-noise amplifier using a receiving antenna.

6. The radar receiver of claim 1, wherein, The ADC circuit includes: The resistor voltage divider unit consists of several resistor voltage dividers connected in parallel. These resistor voltage dividers are used to quantize the input reference voltage threshold into multiple corresponding reference comparison voltages. The voltage comparator unit consists of several voltage comparators. One end of each voltage comparator is connected to the same capacitor, and the other end is connected together as the input terminal of the sample-and-hold analog voltage. A sample-and-hold circuit, coupled to the input of the sample-and-hold analog voltage, is used to sample the analog input signal separately to obtain several converted sample signals. The converted sample signals are compared with the reference comparison voltage formed by the resistor divider unit. After the comparison is completed, the signal is input to the corresponding register and then sent from the register to the encoder. The encoder forms a binary digital signal.

7. The radar receiver of claim 6, wherein, Several parallel resistor dividers quantize the input reference voltage threshold into multiple corresponding, successively increasing reference comparison voltages according to a set rule.

8. The radar receiver of claim 7, wherein, The setting rule is to quantify the reference comparison voltage by successively increasing the set reference voltage threshold according to the rated coefficient.

9. The radar receiver of claim 6, wherein, The voltage divider includes voltage divider resistor R1 and voltage divider resistor R2.

10. The radar receiver of claim 9, wherein, Based on the parallel configuration of several parallel resistive voltage dividers, the total resistance value of the voltage dividing resistors R1 and R2 contained in each resistive voltage divider remains unchanged, and according to the parallel configuration, the voltage dividing resistors R1 and R2 change accordingly with the same resistance value.

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