High-voltage direct-current power supply protection circuit
By introducing a reference voltage source and comparator into the high-voltage DC power supply protection circuit, combined with a MOSFET, and setting hysteresis characteristics and an adjustable reference voltage, the problems of single function and repeated startup of the high-voltage DC power supply protection circuit are solved, and accurate overvoltage and undervoltage protection is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUN CREATIVE ZHEJIANG TECH CO LTD
- Filing Date
- 2025-05-14
- Publication Date
- 2026-05-01
AI Technical Summary
Existing high-voltage DC power supply protection circuits suffer from problems such as limited functionality, high cost, or insufficient current capacity. Furthermore, protection circuits using common discrete components are prone to causing repeated circuit restarts.
The protection circuit, composed of a reference voltage source, comparator, and MOSFET, achieves overvoltage and undervoltage protection by setting hysteresis characteristics and an adjustable reference voltage, thus preventing the circuit from repeatedly starting up.
It achieves overvoltage and undervoltage protection for high-voltage DC power supplies, has hysteresis characteristics, adjustable protection threshold, adapts to different product requirements, and avoids repeated activation of the protection circuit.
Smart Images
Figure CN224191626U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit technology, and in particular to a high-voltage DC power supply protection circuit. Background Technology
[0002] When using imported components for overvoltage and undervoltage protection circuits of high-voltage DC power supplies, the applications are more extensive due to their comprehensive functions, but the high price makes procurement difficult and unsuitable for large-scale mass production. When using domestically produced chips, the current capacity of the chips is insufficient, which can easily trigger overcurrent protection. On the other hand, when using common discrete components, the protection function is limited and lacks hysteresis adjustment characteristics, which can easily cause the circuit to restart repeatedly when the protection circuit is activated. Summary of the Invention
[0003] The purpose of this invention is to address the shortcomings of existing technologies and provide a high-voltage DC power supply protection circuit.
[0004] The purpose of this utility model is achieved through the following technical solution: a high-voltage DC power supply protection circuit, including a reference voltage source U1, comparator U2A, comparator U2B, NMOS transistor Q1, PMOS transistor Q2, NMOS transistor Q3, and NMOS transistor Q4. The reference voltage source U1 is used to generate a reference voltage. A first main path is provided between the power input terminal and the power output terminal, and a second main path is provided between the power output terminal and the ground terminal. A first branch and a second branch are provided between the first main path and the second main path. The non-inverting input terminal of comparator U2A and the inverting input terminal of comparator U2B are simultaneously connected to the reference voltage source U1 and the first main path. The inverting input terminal of comparator U2A is connected to the first branch, and the non-inverting input terminal of comparator U2B is connected to the second branch. The output terminals of comparator U2A and comparator U2B are simultaneously connected to a third branch, and the third branch is connected to the first main path.
[0005] The drain and source of NMOS transistor Q1 are both connected to the second branch, and the gate of NMOS transistor Q1 is connected to the third branch; the drain and source of NMOS transistor Q3 are both connected to the second branch, and the gate of NMOS transistor Q3 is connected to the third branch; the gate of NMOS transistor Q4 is connected to the third branch, and the drain of NMOS transistor Q4 is connected to the gate of PMOS transistor Q2; the drain and source of PMOS transistor Q2 are connected to the first main circuit.
[0006] Preferably, a fourth branch is provided between the first main road and the second main road, and a capacitor C1 is provided on the fourth branch.
[0007] Preferably, the positive power supply terminal of comparator U2A is connected to the first main circuit.
[0008] Preferably, a resistor R3 is provided between the non-inverting input terminal of comparator U2A and the inverting input terminal of comparator U2B and the first main circuit.
[0009] Preferably, resistors R2 and R7 are provided on the first branch, and resistor R8 is provided on the drain and source supports of the NMOS transistor Q3.
[0010] Preferably, resistors R1 and R5 are provided on the second branch, and resistor R6 is provided between the source and drain of NMOS transistor Q1.
[0011] Preferably, a resistor R11 is provided between the drain of the NMOS transistor Q4 and the gate of the PMOS transistor Q2.
[0012] Preferably, a resistor R4 is provided between the gate and source of the PMOS transistor Q2.
[0013] Preferably, the reference voltage source U1 is an adjustable three-terminal reference voltage regulator.
[0014] The beneficial effects of this utility model are:
[0015] 1. This new patent is applicable to overvoltage and undervoltage protection of high-voltage DC power supplies. The circuit has hysteresis characteristics to avoid repeated power supply restarts caused by the operation of the protection circuit.
[0016] 2. The protection threshold of this utility model can be set, the protection threshold accuracy is high, and the hysteresis voltage can be freely adjusted according to the specific power supply conditions, which meets the usage needs of different products. Attached Figure Description
[0017] Figure 1 This is a circuit diagram of the present invention. Detailed Implementation
[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model are within the protection scope of the present utility model.
[0019] like Figure 1As shown, a high-voltage DC power supply protection circuit includes a reference voltage source U1, comparators U2A and U2B, NMOS transistors Q1, Q2, Q3, and Q4. The reference voltage source U1 generates a reference voltage. A first main path is provided between the power input terminal and the power output terminal, and a second main path is provided between the power output terminal and the ground terminal. A first branch and a second branch are provided between the first main path and the second main path. The non-inverting input terminal of comparator U2A and the inverting input terminal of comparator U2B are simultaneously connected to the reference voltage source U1 and the first main path. The inverting input terminal of comparator U2A is connected to the first branch, and the non-inverting input terminal of comparator U2B is connected to the second branch. The output terminals of comparator U2A and comparator U2B are simultaneously connected to a third branch, which is connected to the first main path.
[0020] The drain and source of NMOS transistor Q1 are both connected to the second branch, and the gate of NMOS transistor Q1 is connected to the third branch; the drain and source of NMOS transistor Q3 are both connected to the first branch, and the gate of NMOS transistor Q3 is connected to the third branch; the gate of NMOS transistor Q4 is connected to the third branch, and the drain of NMOS transistor Q4 is connected to the gate of PMOS transistor Q2; the drain and source of PMOS transistor Q2 are connected to the first main circuit.
[0021] The reference voltage source U1 is an adjustable three-terminal reference voltage regulator. Reference voltage source U1 generates a reference voltage VREF. Resistors R9 and R10 are provided on reference voltage source U1; these resistors are used to set the voltage value of the reference voltage VREF.
[0022] ;
[0023] Wherein, VR = 2.5V.
[0024] A fourth branch is provided between the first and second main power lines, and capacitor C1 is installed on the fourth branch. Capacitor C1 serves as a filter capacitor at the power input terminal. Capacitor C2 serves as a filter capacitor at the power output terminal.
[0025] The positive power supply terminal of comparator U2A is connected to the first main circuit.
[0026] A resistor R3 is provided between the non-inverting input terminal of comparator U2A and the inverting input terminal of comparator U2B and the first main circuit.
[0027] Resistors R2 and R7 are installed on the first branch, and resistor R8 is installed between the drain and source of NMOS transistor Q3. Resistor R2 is installed between the inverting input of comparator U2A and the first main branch, and resistor R7 is installed between the source of NMOS transistor Q3 and ground.
[0028] The second branch is equipped with resistors R1 and R5, and resistor R6 is placed between the source and drain of NMOS transistor Q1. Resistor R1 is placed between the non-inverting input of comparator U2B and the ground terminal, and resistor R5 is placed between the drain of NMOS transistor Q1 and the first main branch.
[0029] A resistor R11 is placed between the drain of NMOS transistor Q4 and the gate of PMOS transistor Q2. A resistor R4 is placed between the gate and source of PMOS transistor Q2.
[0030] Resistor R3 is used to adjust the operating current I of the reference voltage source U1. KA In this embodiment, the operating current I KA The range is 0.45mA to 150mA.
[0031] Resistors R7, R8, R2, and NMOS transistor Q3 are used to set the overvoltage cutoff voltage OVP. rise and overvoltage turn-on voltage (OVP) fall When NMOS transistor Q3 is turned on,
[0032] OVP rise =VREF×(R2+R7) / R7;
[0033] When NMOS transistor Q3 is turned off
[0034] OVP fall =VREF×(R2+R8+R7) / (R7+R8).
[0035] Resistors R5, R6, R1, and NMOS transistor Q1 are used to set the undervoltage cutoff voltage UVLO. fall and undervoltage turn-on voltage UVLO rise When NMOS transistor Q1 is turned on,
[0036] UVLO fall =VREF×(R5+R1) / R1;
[0037] When NMOS transistor Q1 is turned off
[0038] UVLO rise =VREF×(R5+R6+R1) / R1.
[0039] Comparators U2A and U2B compare the magnitudes of the non-inverting input voltage (IN+ terminal) and the inverting input voltage (IN- terminal), outputting either a high or low level at their output terminals (OUT terminals). When the non-inverting input voltage is higher than the inverting input voltage, the OUT terminal of the comparator outputs a high level; when the non-inverting input voltage is lower than the inverting input voltage, the OUT terminal outputs a low level.
[0040] Overvoltage protection methods are as follows:
[0041] When the voltage V at the power input terminal POWER_IN In UVLO fall With OVP rise During this period, PMOS transistor Q2 is on, and the load operates normally. When the input voltage changes higher than OVP... rise When the overvoltage protection is activated, PMOS transistor Q2 (power switch transistor) is turned off, the power output is shut off, and the load stops working.
[0042] If the voltage V at the power input terminal POWER_IN Pullback to lower, below OVP fall When the power switch is activated, PMOS transistor Q2 (power switch transistor) turns on, opening the power output and restoring the load to normal operation.
[0043] Overvoltage hysteresis = OVP rise -OVP fall .
[0044] The operating principle of the overvoltage protection circuit is analyzed as follows:
[0045] When the voltage V at the power input terminal POWER_IN In UVLO fall With OVP rise When the voltage is between these two values, the voltage detected at the inverting input of comparator U2A is V. POWER_IN *{R7 / (R7+R2)}, the voltage monitored at the non-inverting input of comparator U2A is VREF. Since the voltage at the non-inverting input is greater than the detection voltage at the inverting input, the output of comparator U2A is high. The gates of NMOS transistors Q1, Q3, and Q4 are turned on due to the high-level load. The drain and source of NMOS transistor Q4 are grounded, and the gate of PMOS transistor Q2 is turned on due to the low-level load. The load is powered on and operates.
[0046] When the voltage at the power input terminal changes upward and exceeds OVP rise When the voltage at the inverting input of comparator U2A is higher than the reference power supply VREF at the non-inverting input, the output of comparator U2A is low. The gates of NMOS transistors Q1, Q3, and Q4 are cut off due to the low voltage applied. The drain and source of NMOS transistor Q4 are cut off, and the gate of PMOS transistor Q2 is cut off due to the high voltage applied. The load is de-energized and does not work.
[0047] When the voltage at the power input terminal drops, the overvoltage / overvoltage hysteresis adjustment phase begins. At this time, the voltage detected at the inverting input terminal of comparator U2A is V. POWER_INWhen the voltage at the inverting input of comparator U2A is lower than the reference power supply VREF at the non-inverting input, the output of comparator U2A is high. The gates of NMOS transistors Q1, Q3, and Q4 are turned on due to the high level applied. The drain and source of NMOS transistor Q4 are grounded. The gate of PMOS transistor Q2 is turned on due to the low level applied. The load is powered on and works.
[0048] The undervoltage protection method is as follows:
[0049] When the voltage V at the power input terminal POWER_IN It changes downwards and is below UVLO. fall When the undervoltage protection trips, PMOS transistor Q2 is cut off, shutting down the power output and stopping the load from operating. If the input voltage is high and the trip is higher than UVLO, the protection will trip. rise When this occurs, PMOS transistor Q2 turns on, opening the power output and restoring the load to normal operation. Undervoltage hysteresis = UVLO rise -UVLO fall .
[0050] The operating principle of the undervoltage protection circuit is analyzed as follows:
[0051] When the voltage V at the power input terminal POWER_IN In UVLO fall With OVP rise When the voltage is between these two points, the non-inverting input of comparator U2B detects a voltage of V. POWER_IN *{R1 / (R1+R5)}, the voltage at the inverting input is VREF. Since the voltage at the non-inverting input is greater than the voltage at the inverting input, the output of comparator U2B is high. The gates of NMOS transistors Q1, Q3, and Q4 are turned on due to the high level applied. The drain and source of NMOS transistor Q4 are grounded, and the gate of PMOS transistor Q2 is turned on with a low level applied, thus powering on the load.
[0052] When the voltage at the power input terminal changes downward and falls below UVLO fall When the voltage detected at the non-inverting input of comparator U2B is lower than the reference power supply VREF at the inverting input, the output of comparator U2B outputs a low level. The gates of NMOS transistors Q1, Q3, and Q4 are cut off due to the low-level load. The drain and source of NMOS transistor Q4 are cut off, and the gate of PMOS transistor Q2 is cut off due to the high voltage load. The load is de-energized and does not work.
[0053] When the input voltage rises and then falls back, the undervoltage hysteresis adjustment phase begins. At this time, the detection voltage at the non-inverting input of comparator U2B is V. POWER_INWhen the voltage at the non-inverting input terminal is greater than the reference power supply VREF at the inverting input terminal, the output terminal of comparator U2B outputs a high level. The gates of NMOS transistors Q1, Q3, and Q4 are turned on due to the high level applied. The drain and source of NMOS transistor Q4 are grounded. The gate of PMOS transistor Q2 is turned on due to the low level applied. The load is powered on and works.
[0054] In this application, the DC voltage range at the power input terminal is 10-15V, and the undervoltage turn-on voltage is UVLO. rise Set to 10.13V, undervoltage cutoff voltage UVLO fa11 Set to 10.03V, overvoltage cutoff voltage OVP rise Set to 14.95V, overvoltage turn-on voltage (OVP) fa11 The voltage is set to 14.47V. Capacitors C1 and C2 have a capacitance of 10uF / 25V. Resistors R1 and R7 are 2.49KΩ, R2 is 28KΩ, R3 is 5.1KΩ, R4, R10, and R12 are 10KΩ, R5 is 7.5KΩ, R6 and R8 are 100Ω, R9 is 0Ω, and R11 is 1KΩ. PMOS transistor Q2 is a CJAE10P06, NMOS transistors Q1, Q3, and Q4 are CJ2310, the reference voltage source U1 is a CJ431D-N3A-ARG, and comparators U2A and U2B are LM393.
[0055] This utility model is not limited to the above-described preferred embodiments. Anyone can derive other forms of products under the guidance of this utility model. However, regardless of any changes made in their shape or structure, any technical solution that is the same as or similar to this application falls within the protection scope of this utility model.
Claims
1. A high voltage direct current power supply protection circuit, characterized by, It includes a reference voltage source U1, comparator U2A, comparator U2B, NMOS transistor Q1, PMOS transistor Q2, NMOS transistor Q3, and NMOS transistor Q4. The reference voltage source U1 is used to generate a reference voltage. A first main path is provided between the power input terminal and the power output terminal, a second main path is provided between the power output terminal and the ground terminal, and a first branch and a second branch are provided between the first main path and the second main path. The non-inverting input of comparator U2A and the inverting input of comparator U2B are simultaneously connected to the reference voltage source U1 and the first main circuit. The inverting input of comparator U2A is connected to the first branch. The non-inverting input of comparator U2B is connected to the second branch. The outputs of comparator U2A and comparator U2B are simultaneously connected to the third branch, which is connected to the first main circuit. The drain and source of NMOS transistor Q1 are both connected to the second branch, and the gate of NMOS transistor Q1 is connected to the third branch; the drain and source of NMOS transistor Q3 are both connected to the second branch, and the gate of NMOS transistor Q3 is connected to the third branch; the gate of NMOS transistor Q4 is connected to the third branch, the drain of NMOS transistor Q4 is connected to the gate of PMOS transistor Q2, and the drain of NMOS transistor Q4 is connected to the second main path; the drain and source of PMOS transistor Q2 are connected to the first main path.
2. The high-voltage DC power supply protection circuit according to claim 1, characterized in that, A fourth branch is provided between the first main road and the second main road, and a capacitor C1 is provided on the fourth branch.
3. The protective circuit for a high voltage DC power supply according to claim 1, wherein The positive power supply terminal of comparator U2A is connected to the first main circuit.
4. The protective circuit for a high voltage DC power supply according to claim 1, wherein A resistor R3 is provided between the non-inverting input of comparator U2A and the inverting input of comparator U2B and the first branch.
5. A high-voltage DC power supply protection circuit according to claim 1, characterized in that, Resistors R2 and R7 are provided on the first branch, and resistor R8 is provided between the drain and source of NMOS transistor Q3.
6. A high-voltage DC power supply protection circuit according to claim 1, characterized in that, The second branch is provided with resistors R1 and R5, and resistor R6 is provided between the source and drain of NMOS transistor Q1.
7. The protective circuit for a high voltage DC power supply of claim 1, wherein, A resistor R11 is provided between the drain of the NMOS transistor Q4 and the gate of the PMOS transistor Q2.
8. The protective circuit for a high voltage DC power supply of claim 1, wherein, A resistor R4 is provided between the gate and source of the PMOS transistor Q2.
9. A high-voltage DC power supply protection circuit according to claim 1, characterized in that, The reference voltage source U1 is an adjustable three-terminal reference voltage regulator.