Solar cell
By incorporating a patterned barrier layer into the solar cell, the problems of metal paste burn-through and excessively low short-circuit current were solved, thereby improving the cell's performance and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TRINA SOLAR CO LTD
- Filing Date
- 2025-06-09
- Publication Date
- 2026-05-08
AI Technical Summary
During the metallization process of solar cells, if the barrier layer is too thin, the metal paste may burn through the polycrystalline silicon layer, while if it is too thick, the short-circuit current will be too low, affecting the cell conversion efficiency.
In solar cells, barrier layers are set between multiple polycrystalline silicon layers, including a thicker first barrier and a thinner second barrier, or a thicker first barrier is set only in the electrode projection area. Through patterned design, metal paste burn-through is avoided and the impact on short-circuit current is reduced.
It effectively protects the polycrystalline silicon layer from being burned through, reduces impurity diffusion, improves battery performance and stability, and ensures battery conversion efficiency.
Smart Images
Figure CN224218759U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of photovoltaic cell technology, specifically to a solar cell. Background Technology
[0002] Tunnel oxide passivating contacts (TOPCon) solar cells form a novel passivated contact structure through a tunnel oxide layer and a doped polycrystalline silicon layer. This passivated contact structure can selectively transport charge carriers, significantly improving the overall efficiency of solar cells and becoming an important direction for the development of photovoltaic cells.
[0003] In related technologies, solar cells include a silicon substrate and electrodes. A tunneling oxide layer is disposed on one side of the silicon substrate. At least two doped polycrystalline silicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polycrystalline silicon layers. The electrodes are electrically connected to different doped polycrystalline silicon layers.
[0004] However, the metallization process of solar cells requires the use of metal pastes with certain corrosive properties. If the barrier layer is too thin, the metal paste may burn through the polycrystalline silicon layer. If the barrier layer is too thick, the short-circuit current of the solar cell will be too low, affecting the cell's conversion efficiency.
[0005] Accordingly, a new technical solution is needed in this field to solve the above problems. Utility Model Content
[0006] In order to solve at least one of the above-mentioned problems in the prior art, namely, that if the barrier layer is too thin, the metal paste will easily burn through the polycrystalline silicon layer, and if the barrier layer is too thick, the short-circuit current of the solar cell will be too low, affecting the conversion efficiency of the cell.
[0007] In a first aspect, this application provides a solar cell, the solar cell comprising: a silicon substrate including a first surface and a second surface disposed opposite to each other; a tunneling oxide layer disposed on the first surface and / or the second surface of the silicon substrate; multiple polycrystalline silicon layers disposed on the tunneling oxide layer; a barrier layer disposed between two adjacent polycrystalline silicon layers; a passivation layer disposed on the multiple polycrystalline silicon layers; and a plurality of electrodes disposed on the passivation layer; wherein the barrier layer includes a plurality of first barrier portions and second barrier portions, the first barrier portions corresponding one-to-one with the orthographic projections of the electrodes on the silicon substrate, and the thickness of the first barrier portion being greater than the thickness of the second barrier portion; or, the barrier layer includes only a plurality of first barrier portions corresponding one-to-one with the orthographic projections of the electrodes on the silicon substrate.
[0008] In some embodiments, the thickness of the first blocking portion ranges from 2 mm to 2.5 mm.
[0009] In some embodiments, the thickness of the second blocking portion ranges from 1 mm to 2 mm.
[0010] In some embodiments, the barrier layer comprises one or more of silicon carbide, silicon oxide, silicon nitride, and aluminum oxide.
[0011] In some embodiments, the orthogonal projection of the first blocking portion onto the silicon substrate includes the orthogonal projection of the electrode onto the silicon substrate.
[0012] In some embodiments, the solar cell includes three polycrystalline silicon layers, and a first barrier layer and a second barrier layer disposed between two adjacent polycrystalline silicon layers, wherein the first barrier layer is located on the side of the second barrier layer closer to the silicon substrate.
[0013] In some embodiments, the first blocking layer includes the first blocking portion and the second blocking portion, and the second blocking layer includes only the first blocking portion.
[0014] In some embodiments, the first blocking layer includes only the first blocking portion, and the second blocking layer includes both the first blocking portion and the second blocking portion.
[0015] In some embodiments, the first blocking layer includes the first blocking portion and the second blocking portion, and the second blocking layer includes the first blocking portion and the second blocking portion.
[0016] In some embodiments, the passivation layer includes a silicon nitride layer and an aluminum oxide layer stacked together.
[0017] Under the premise of adopting the above technical solution, the solar cell provided in this application has a barrier layer between two adjacent polycrystalline silicon layers. The barrier layer includes a first barrier portion corresponding to the electrode and a second barrier portion corresponding to the outer region of the electrode, or the barrier layer only includes the first barrier portion corresponding to the electrode, wherein the thickness of the first barrier portion is greater than the thickness of the second barrier portion. This application uses a patterned design for the barrier layer. A thicker first barrier portion is provided in the electrode projection area to prevent the metal paste from burning through the polycrystalline silicon layer; a thinner second barrier portion is provided in the non-electrode projection area, or the barrier layer is selectively removed, which can reduce the impact of the barrier layer on the short-circuit current of the solar cell and help ensure the conversion efficiency of the cell. In addition, by providing a barrier layer, impurities can be prevented from diffusing into the silicon substrate, which is beneficial to further improving the performance and stability of the solar cell. Attached Figure Description
[0018] The preferred embodiments of this application are described below with reference to the accompanying drawings, in which:
[0019] Figure 1 This is a schematic diagram of the structure of the solar cell in this application;
[0020] Figure 2 This is another schematic diagram of the solar cell structure in this application;
[0021] Figure 3 This is another schematic diagram of the solar cell structure in this application;
[0022] Figure 4 This is another schematic diagram of the solar cell structure in this application;
[0023] Figure 5 This is another schematic diagram of the structure of the solar cell in this application.
[0024] Figure label:
[0025] 100. Silicon substrate;
[0026] 200. Tunneling oxide layer;
[0027] 300, polycrystalline silicon layer;
[0028] 400, barrier layer; 401, first barrier part; 402, second barrier part; 700, first barrier layer; 800, second barrier layer;
[0029] 500, passivation layer; 501, silicon nitride layer; 502, aluminum oxide layer;
[0030] 600, Electrode. Detailed Implementation
[0031] Preferred embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely for explaining the technical principles of this application and are not intended to limit the scope of protection of this application. Those skilled in the art can make adjustments as needed to adapt to specific application scenarios. Such changes in application scenarios do not deviate from the basic principles of this application and fall within the scope of protection of this application.
[0032] In the embodiments of this application, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly for better describing the embodiments of this application and their implementations, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation. Furthermore, some of the above terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application according to the specific circumstances.
[0033] It should be noted that, in the description of this preferred embodiment, unless otherwise explicitly specified and limited, the terms "connected" and "connected" should be interpreted broadly. For example, they can refer to mechanical connections or electrical connections, direct connections or indirect connections through an intermediate medium, or connections within two components. These should not be construed as limitations on this application. Furthermore, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only, and those skilled in the art can understand the specific meaning of these terms in this application according to the specific circumstances.
[0034] Tunnel oxide passivating contacts (TOPCon) solar cells form a novel passivated contact structure through a tunnel oxide layer and a doped polycrystalline silicon layer. This passivated contact structure can selectively transport charge carriers, significantly improving the overall efficiency of solar cells and becoming an important direction for the development of photovoltaic cells.
[0035] In related technologies, solar cells include a silicon substrate and electrodes. A tunneling oxide layer is disposed on one side of the silicon substrate. At least two doped polycrystalline silicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polycrystalline silicon layers. The electrodes are electrically connected to different doped polycrystalline silicon layers.
[0036] However, the metallization process of solar cells requires the use of metal pastes with a certain degree of corrosivity. If the barrier layer is too thin, the metal paste may burn through the polycrystalline silicon layer; if the barrier layer is too thick, the short-circuit current of the solar cell will be too low, affecting the cell's conversion efficiency. The role of metallization is to deposit metal electrodes, which form good ohmic contact with the silicon substrate, thereby efficiently extracting photogenerated carriers.
[0037] This application provides a solar cell that can prevent the metal paste from burning through the polycrystalline silicon layer, while reducing the impact of the barrier layer on the short-circuit current of the solar cell.
[0038] Combination Figure 1 As shown, the solar cell provided in this application includes a silicon substrate 100, a tunneling oxide layer 200, a multilayer polycrystalline silicon layer 300, a barrier layer 400, a passivation layer 500, and multiple electrodes 600.
[0039] The silicon substrate 100 includes a first surface and a second surface disposed opposite to each other. The silicon substrate 100 is capable of light absorption and generating charge carriers. Optionally, the silicon substrate is an N-type silicon substrate. N-type silicon substrates have higher absorption efficiency for long-wavelength light (>1000nm) and, compared with P-type silicon substrates, can reduce recombination losses of photogenerated charge carriers, which is beneficial to improving battery performance.
[0040] The tunneling oxide layer 200 is disposed on the first surface and / or the second surface of the silicon substrate 100.
[0041] A multilayer polycrystalline silicon layer 300 is disposed on the tunneling oxide layer 200. That is, the multilayer polycrystalline silicon layer 300 is stacked on the surface of the tunneling oxide layer 200 away from the silicon substrate 100. The polycrystalline silicon layer 300 can have two, three, four, or five layers, etc., and the number of layers can be flexibly set according to actual needs. The tunneling oxide layer 200 and the polycrystalline silicon layer 300 together constitute a passivated contact structure, replacing the direct contact between the metal electrode and the silicon substrate 100 in traditional solar cells, effectively reducing carrier recombination losses.
[0042] A barrier layer 400 is disposed between two adjacent polysilicon layers 300. The barrier layer 400 can protect the polysilicon layer 300 from being burned through by the metal paste, and at the same time can prevent impurities from diffusing into the silicon substrate 100.
[0043] A passivation layer 500 is disposed on the multilayer polysilicon layer 300. By disposing of the passivation layer 500, the polysilicon layer 300 can be protected from environmental corrosion.
[0044] Multiple electrodes 600 are disposed on the passivation layer 500.
[0045] The barrier layer 400 includes a plurality of first barrier portions 401 and second barrier portions 402. Each first barrier portion 401 corresponds one-to-one with the orthographic projection of the electrode 600 onto the silicon substrate 100, and the thickness of the first barrier portion 401 is greater than the thickness of the second barrier portion 402. Alternatively, the barrier layer 400 may include only a plurality of first barrier portions 401 that correspond one-to-one with the orthographic projection of the electrode 600 onto the silicon substrate 100.
[0046] Under the premise of adopting the above technical solution, the solar cell provided in this application has a barrier layer 400 between two adjacent polycrystalline silicon layers. The barrier layer 400 includes a first barrier portion 401 corresponding to the electrode and a second barrier portion 402 corresponding to the outer region of the electrode, or the barrier layer 400 only includes the first barrier portion 401 corresponding to the electrode 600, wherein the thickness of the first barrier portion 401 is greater than the thickness of the second barrier portion 402. This application has a patterned design for the barrier layer 400. A thicker first barrier portion 401 is provided in the electrode projection region (the electrode projection region refers to the orthogonal projection of the electrode 600 on the silicon substrate 100), which can prevent the metal paste from burning through the polycrystalline silicon layer 300. A thinner second barrier portion 402 is provided in the non-electrode projection region (the non-electrode projection region refers to the orthogonal projection of the outer region of the electrode 600 on the silicon substrate 100), or the barrier layer 400 is selectively removed, which can reduce the impact of the barrier layer on the short-circuit current of the solar cell and help ensure the conversion efficiency of the cell. In addition, by providing the barrier layer 400, impurities can be prevented from diffusing into the silicon substrate, which is beneficial to further improve the performance and stability of the solar cell.
[0047] In some embodiments, the thickness of the first blocking portion 401 ranges from 2 mm to 2.5 mm. For example, the thickness of the first blocking portion 401 can be 2 mm, 2.1 mm, 2.2 mm, 2.3 mm, 2.4 mm, or 2.5 mm, etc. By limiting the thickness of the first blocking portion 401 to the above range, it is possible to effectively prevent the metal paste from burning through the underlying polycrystalline silicon layer during the metallization process.
[0048] In some embodiments, the thickness of the second blocking portion 402 ranges from 1 mm to 2 mm. For example, the thickness of the second blocking portion 402 can be 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, or 2.0 mm. By limiting the thickness of the second blocking portion 402 to the above range, it is possible to ensure efficient transport of charge carriers to the metal electrode, reduce resistance loss, reduce the impact on the short-circuit current of the solar cell, and thus improve the efficiency of the solar cell. At the same time, the second blocking portion 402 can prevent impurities from diffusing into the silicon substrate 100, reduce the carrier recombination loss caused by impurity diffusion, and help ensure the cell efficiency of the solar cell.
[0049] In some embodiments, the barrier layer 400 comprises silicon carbide (SiC). x ), silicon dioxide (SiO) x ), silicon nitride (SiN) x ) and aluminum oxide (AlO xOne or more of the following. For example, the barrier layer 400 is a silicon oxide layer, a silicon carbide layer, a silicon oxide layer, or an aluminum oxide layer.
[0050] By limiting the composition of the barrier layer 400 to the aforementioned range, a barrier effect can be achieved, preventing the metal paste from spreading laterally and burning through the polysilicon layer 300. At the same time, it can also prevent impurities from diffusing into the silicon substrate and reduce the impact on electron transport.
[0051] In some embodiments, the orthographic projection of the first blocking portion 401 onto the silicon substrate 100 includes the orthographic projection of the electrode 600 onto the silicon substrate 100. That is, the length of the first blocking portion 401 is greater than or equal to the length of the electrode 600. This configuration provides effective protection against the metal paste burning through the polysilicon layer 300.
[0052] In some embodiments, combined with Figure 2 As shown, the passivation layer 500 includes a silicon nitride layer 501 and an aluminum oxide layer 502 stacked together. This configuration can improve the passivation effect of the solar cell.
[0053] In some embodiments, combined with Figure 3 , Figure 4 and Figure 5 As shown, the solar cell includes three polycrystalline silicon layers 300, and a first barrier layer 700 and a second barrier layer 800 disposed between two adjacent polycrystalline silicon layers 300. The first barrier layer 700 is located on the side of the second barrier layer 800 closer to the silicon substrate 100. The first barrier layer 700 and the second barrier layer 800 can include various possible combinations:
[0054] Optionally, combined Figure 3 As shown, the first barrier layer 700 includes a first barrier portion 401 and a second barrier portion 402, while the second barrier layer 800 includes only the first barrier portion 401. The second barrier layer can prevent the metal paste from burning through the polysilicon layer 300 above it. The first barrier layer 700 is disposed close to the silicon substrate 100, which not only prevents the metal paste from burning through the polysilicon layer 300 above it, but also prevents impurities from diffusing downwards into the silicon substrate 100.
[0055] Optionally, combined Figure 4 As shown, the first barrier layer 700 includes only a first barrier portion 401, and the second barrier layer 800 includes a first barrier portion 401 and a second barrier portion 402. The first barrier layer 700 can prevent the metal paste from burning through the polysilicon layer 300 above it. The second barrier layer 800 can not only prevent the metal paste from burning through the polysilicon layer 300 above it, but also prevent impurities from diffusing downwards to the silicon substrate 100.
[0056] Optionally, combined Figure 5As shown, the first barrier layer 700 includes a first barrier portion 401 and a second barrier portion 402, and the second barrier layer 800 includes a first barrier portion 401 and a second barrier portion 402. Both the first barrier layer 700 and the second barrier layer 800 can prevent the metal paste from burning through the polycrystalline silicon layer 300 above them, and can also prevent impurities from diffusing downwards to the silicon substrate 100.
[0057] Optionally, the first barrier layer 700 includes only the first barrier portion 401, and the second barrier layer 800 includes only the first barrier portion 401. Both the first barrier layer 700 and the second barrier layer 800 can prevent the metal paste from burning through the polysilicon layer 300 above them.
[0058] The solar cell provided in this application can be prepared by the following steps:
[0059] The silicon substrate 100 is cleaned and texturized.
[0060] A tunneling oxide layer 200 is prepared on a silicon substrate 100;
[0061] Multiple polycrystalline silicon layers 300 and barrier layers 400 are alternately fabricated on the tunneling oxide layer 200;
[0062] A passivation layer 500 is prepared on the polycrystalline silicon layer 300 that is furthest from the silicon substrate 100;
[0063] Electrode 600 is fabricated on passivation layer 500;
[0064] The barrier layer 400 includes a first barrier portion 401 and a second barrier portion 402. The first barrier portion 401 corresponds one-to-one with the orthographic projection of the electrode 600 on the silicon substrate 100, and the thickness of the first barrier portion 401 is greater than the thickness of the second barrier portion 402. Alternatively, the barrier layer 400 may include only a plurality of first barrier portions 401 that correspond one-to-one with the orthographic projection of the electrode 600 on the silicon substrate 100.
[0065] Cleaning and texturing the silicon substrate 100 removes impurities from its surface and forms a micron-scale textured structure, which helps reduce light reflectivity, improves incident light utilization, and provides a clean, low-defect silicon surface for subsequent passivation contact structures. A tunneling oxide layer 200, alternating polycrystalline silicon layers 300 and barrier layers 400, a passivation layer 500, and an electrode 600 are sequentially fabricated on the silicon substrate 100. The tunneling oxide layer 200 and the polycrystalline silicon layers 300 together constitute the passivation contact structure, replacing the direct contact between the metal electrode and the silicon substrate 100 in traditional solar cells, enabling the fabrication of the desired TOPCon cell. Furthermore, this application features a patterned design for the barrier layer 400. A thicker first barrier portion 401 is provided in the electrode projection area to prevent the metal paste from burning through the polycrystalline silicon layer 300; a thinner second barrier portion 402 is provided in the non-electrode projection area, or the barrier layer is selectively removed, which reduces the impact of the barrier layer on the short-circuit current of the solar cell, thus ensuring the cell's conversion efficiency.
[0066] Optionally, the tunneling oxide layer 200, the polycrystalline silicon layer 300, and the passivation layer 500 are prepared using PECVD (Plasma Enhanced Chemical Vapor Deposition). That is, the tunneling oxide layer 200 is directly deposited on the silicon substrate 100 using PECVD; the polycrystalline silicon layer 300 is directly deposited on the tunneling oxide layer 200 or the passivation layer 500 using PECVD; and the passivation layer 500 is directly deposited on the polycrystalline silicon layer 300 using PECVD.
[0067] Optionally, the barrier layer 400 is prepared by deposition or etching.
[0068] The preparation of the barrier layer 400 by deposition method is described in detail below:
[0069] For example, the barrier layer 400 includes a first barrier portion 401 and a second barrier portion 402. First, the bottom of the second barrier portion 402 and the first barrier portion 401 are deposited on the polysilicon layer 300. Then, a baffle is used to block the area where the first barrier portion 401 is located and expose the area where the second barrier portion 402 is located. Deposition continues to increase the second barrier portion 401 to the required thickness, and then the baffle is removed.
[0070] For example, the barrier layer 400 includes only the first barrier portion 401. First, the polysilicon layer 300 is shielded by a baffle, exposing only the area where the second barrier portion 402 is located. Deposition is performed to increase the second barrier portion 401 to the required thickness, and then the baffle is removed.
[0071] Preparing barrier layers by deposition is relatively simple and can save raw materials.
[0072] The following is a detailed explanation of the etching method used to prepare the barrier layer 400:
[0073] For example, the barrier layer 400 includes a first barrier portion 401 and a second barrier portion 402. First, a deposition layer with the same thickness as the first barrier portion 401 is deposited on the polysilicon layer 300. Then, the thickness of the area where the first barrier portion 401 is located is retained, and the area in the deposition layer corresponding to the second barrier portion 402 is etched to the required thickness.
[0074] For example, the barrier layer 400 includes only the first barrier portion 401. First, a deposition layer with the same thickness as the first barrier portion 401 is deposited on the polysilicon layer 300. Then, the thickness of the area where the first barrier portion 401 is located is retained, and the remaining part of the deposition layer is etched away.
[0075] Optionally, before fabricating the passivation layer 500, the fabrication steps of the solar cell further include: high-temperature annealing of the silicon substrate; and removal of the polycrystalline silicon layer deposited around the silicon substrate. High-temperature annealing activates doped atoms and removes excess polycrystalline silicon layer from the sides of the silicon substrate.
[0076] The technical solutions of this application have been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions resulting from these changes or substitutions will all fall within the scope of protection of this application.
Claims
1. A solar cell, characterized in that, The solar cell includes: A silicon substrate (100) includes a first surface and a second surface disposed opposite to each other; A tunneling oxide layer (200) is disposed on the first surface and / or the second surface of the silicon substrate (100); A multilayer polycrystalline silicon layer (300) is disposed on the tunneling oxide layer (200); A barrier layer (400) is disposed between two adjacent polysilicon layers (300); A passivation layer (500) is disposed on the multilayer polycrystalline silicon layer (300); Multiple electrodes (600) are disposed on the passivation layer (500); The barrier layer (400) includes a plurality of first barrier portions (401) and second barrier portions (402), wherein each first barrier portion (401) corresponds one-to-one with the orthographic projection of the electrode (600) on the silicon substrate (100), and the thickness of the first barrier portion (401) is greater than the thickness of the second barrier portion (402); or, the barrier layer (400) includes only a plurality of first barrier portions (401) that correspond one-to-one with the orthographic projection of the electrode (600) on the silicon substrate (100).
2. The solar cell according to claim 1, characterized in that, The thickness of the first blocking part (401) ranges from 2mm to 2.5mm.
3. The solar cell according to claim 1, characterized in that, The thickness of the second blocking part (402) ranges from 1 mm to 2 mm.
4. The solar cell according to claim 1, characterized in that, The barrier layer (400) is composed of one or more of silicon carbide, silicon oxide, silicon nitride and aluminum oxide.
5. The solar cell according to claim 1, characterized in that, The orthographic projection of the first blocking portion (401) onto the silicon substrate (100) includes the orthographic projection of the electrode (600) onto the silicon substrate (100).
6. The solar cell according to any one of claims 1 to 5, characterized in that, The solar cell includes three polycrystalline silicon layers (300), and a first barrier layer (700) and a second barrier layer (800) disposed between two adjacent polycrystalline silicon layers (300), wherein the first barrier layer (700) is located on the side of the second barrier layer (800) closer to the silicon substrate (100).
7. The solar cell according to claim 6, characterized in that, The first barrier layer (700) includes a first barrier portion (401) and a second barrier portion (402), and the second barrier layer (800) includes only the first barrier portion (401).
8. The solar cell according to claim 6, characterized in that, The first barrier layer (700) includes only the first barrier portion (401), and the second barrier layer (800) includes the first barrier portion (401) and the second barrier portion (402).
9. The solar cell according to claim 6, characterized in that, The first barrier layer (700) includes a first barrier portion (401) and a second barrier portion (402), and the second barrier layer (800) includes the first barrier portion (401) and the second barrier portion (402).
10. The solar cell according to any one of claims 1 to 5, characterized in that, The passivation layer (500) includes a silicon nitride layer (501) and an aluminum oxide layer (502) stacked together.