Low-code based data quality quick configuration device

Abstract

The utility model provides a data quality rapid configuration device based on low code, including shell, data input interface, rule configuration panel, rule compiling unit, quality execution unit and rule extension unit, data input interface and rule configuration panel are installed on the casing of shell respectively, rule compiling unit and quality processing execution unit are installed in the shell respectively, rule extension unit is installed in the shell, and is equipped with extension interface on the casing of shell, rule configuration panel and rule extension unit are electrically connected with rule compiling unit, and data input interface and rule compiling unit are electrically connected with quality execution unit. The utility model uses in through hardware device cooperation simple such as button, knob, drag component etc. external input equipment setting configuration parameter, realizes data quality configuration processing, needs the work of user programming to be very little, reduces the dependence to software development environment, realizes low code's data quality rapid configuration.

Description

Technical Field

[0001] This utility model relates to the field of data processing device technology, and in particular to a low-code-based data quality rapid configuration device. Background Technology

[0002] Low-code refers to technologies that enable developers to quickly build applications with minimal or no code, utilizing graphical interfaces, drag-and-drop components, and predefined logic, thus reducing development difficulty.

[0003] In today's data-driven era, data quality is paramount. Rapid data quality configuration refers to the use of specific tools or technologies to quickly establish a series of rules and standards for data processing workflows to ensure data quality. This process includes data verification, cleaning, and standardization.

[0004] For example, in industrial manufacturing, workers can quickly set data quality rules—such as the normal range of equipment parameters like temperature and pressure—based on production needs within the data configuration device. In the financial industry, rules for the integrity and accuracy of data like names and ID numbers can be rapidly set for customer identity verification. In the healthcare field, the data quality configuration device can configure data quality rules for medical record data, such as standardized diagnosis names and reasonable drug dosage ranges. After the data acquisition device collects medical record data, the data recognition device determines whether the data is compliant. If non-standard diagnosis names or drug dosages exceeding safe ranges are found, the data configuration device can adjust the data according to established rules, such as standardizing non-standard diagnosis names and issuing warnings for abnormal drug dosages, ensuring the accuracy of medical data, providing a reliable basis for medical decisions, and improving the quality of medical services.

[0005] In summary, data quality configuration enables the system to perform quality judgment and processing on the collected data in real time according to rules, which greatly improves the efficiency of the data processing preparation work and enables the data to meet business needs more quickly.

[0006] However, in existing technologies, data quality is mostly achieved by developers writing corresponding rule code. When the rules are updated, the code needs to be recompiled, which requires writing a lot of complex code, resulting in slow response speed and high requirements for the programming skills of staff. Utility Model Content

[0007] The purpose of this invention is to provide a low-code-based data quality rapid configuration device that can reduce the need for writing a large amount of complex code and embody low-code characteristics.

[0008] This utility model provides a low-code-based rapid data quality configuration device, including a housing, a data input interface, a rule configuration panel, a rule compilation unit, a quality execution unit, and a rule extension unit. The data input interface and the rule configuration panel are respectively mounted on the housing. The rule compilation unit and the quality execution unit are respectively mounted inside the housing. The rule extension unit is mounted inside the housing and has an extension interface on the housing. The rule configuration panel and the rule extension unit are electrically connected to the rule compilation unit, and the data input interface and the rule compilation unit are electrically connected to the quality execution unit.

[0009] Furthermore, the rule configuration panel includes a touch screen, through which data features are selected via a graphical interface.

[0010] Furthermore, the rule configuration panel includes a mechanical knob for adjusting threshold parameters.

[0011] Furthermore, the rule configuration panel includes a DIP switch group, and rule logic is generated through different combinations of the DIP switch group.

[0012] Furthermore, the rule configuration panel includes mechanical buttons for mode selection.

[0013] Furthermore, the rule compilation unit includes an FPGA chipset, onboard memory, and a multi-channel PCIe interface.

[0014] Furthermore, the FPGA chipset is pre-programmed with various data quality rule hardware description files.

[0015] Furthermore, the quality execution unit includes a multi-core DSP cluster.

[0016] Furthermore, the rule extension unit includes a rule card and a card reader connector. The card reader connector is installed inside the housing and forms a slot on the housing. The rule card can be plugged into the slot.

[0017] Furthermore, there are multiple rule cards and card reader connectors, with different rule libraries recorded in different rule cards, and at least one rule card can be inserted into each slot.

[0018] This invention's technical solution utilizes a hardware architecture and physical interaction design. A rule configuration panel provides a visual / physical operation interface, directly mapping user operations to hardware signals. Parameters such as data field positions, verification types, and threshold ranges can be defined without writing code, significantly reducing configuration time compared to traditional data quality management processes that require coding. A rule compilation unit (such as an FPGA) converts user configurations into hardware-executable logic, achieving rule deployment through circuit reconstruction rather than software compilation, greatly shortening rule activation time. The quality execution unit uses physical devices such as comparator circuits and shift registers to directly trigger exception handling via hardware interrupt signals, avoiding latency and unreliability caused by the software stack. The rule extension unit allows for pluggable new rule modules with automatic loading functionality, eliminating the need for driver installation or software updates. Therefore, this device uses hardware in conjunction with simple external input devices (such as buttons, knobs, and drag-and-drop components) to set configuration parameters for data quality configuration, requiring minimal user coding. This ensures performance while reducing reliance on software development environments, achieving low-code, rapid data quality configuration. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the external components from the front view of this utility model;

[0021] Figure 2 This is a schematic diagram of the external components from the rear view of this utility model;

[0022] Figure 3 This is a schematic diagram of the internal components of this utility model;

[0023] Explanation of reference numerals in the attached figures:

[0024] 1-Casing; 2-Data input interface;

[0025] 3-Rules configuration panel; 31-Touchscreen; 32-Mechanical knob; 33-Switch group; 34-Mechanical button;

[0026] 4-Rule compilation unit; 5-Quality execution unit;

[0027] 6-Rule extension unit; 61-Rule card; 62-Card reader connector; 63-Slot. Detailed Implementation

[0028] The technical solution of this utility model will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0029] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0031] Example 1

[0032] like Figures 1-3As shown, circuit wiring and data wiring are omitted. This utility model provides a low-code-based rapid data quality configuration device, including a housing 1, a data input interface 2, a rule configuration panel 3, a rule compilation unit 4, a quality execution unit 5, and a rule extension unit 6. The data input interface 2 and the rule configuration panel 3 are respectively mounted on the housing 1; the rule compilation unit 4 and the quality execution unit are respectively mounted inside the housing 1; the rule extension unit 6 is mounted inside the housing 1 and has an extension interface on the housing 1; the rule configuration panel 3 and the rule extension unit 6 are electrically connected to the rule compilation unit 4, and the data input interface 2 and the rule compilation unit 4 are electrically connected to the quality execution unit 5. The housing 1 also includes a power supply device (such as a power supply and voltage regulator) and a heat dissipation device (such as a fan or liquid cooler), which will not be described in detail.

[0033] The rule configuration panel 3 includes a touchscreen 31, through which data features are selected via a graphical interface. The rule configuration panel 3 also includes a mechanical knob 32, used to adjust threshold parameters. Furthermore, the rule configuration panel 3 includes a DIP switch group 33, through which rule logic is generated using different combinations of DIP switches. Finally, the rule configuration panel 3 includes mechanical buttons 34, used for mode selection. The touchscreen 31's coordinate mapping circuit directly converts the finger touch position into a data field address (e.g., X-axis coordinate mapping field number, Y-axis coordinate mapping field type). The mechanical knob 32 has a built-in optical encoder; the rotation angle is converted into binary threshold parameters via a photoelectric sensor (e.g., 0-300° rotation corresponds to a value range of 0x0000-0xFFFF). The physical combination states of the DIP switches generate rule logic via a hardware decoder (e.g., switch 1-ON = length check, switch 2-ON = range check → generating an AND logic circuit signal).

[0034] Rule compilation unit 4 includes an FPGA chipset, onboard memory, and a multi-channel PCIe interface. Various data quality rule hardware description files are pre-programmed onto the FPGA chipset. The FPGA chipset uses a Xilinx UltraScale+ FPGA chipset with 256MB of onboard configuration memory (NORFlash) and a multi-channel PCIe interface. The FPGA chipset pre-programs 20 general data quality rule hardware description files (e.g., length check.hdl: containing shift register + counter circuitry; range check.hdl: containing comparator + threshold register circuitry). The rule combination selected by the user through the configuration panel triggers the FPGA's partial reconfiguration circuitry, updating only the relevant logic areas. The threshold parameters set by the knob are directly written to the FPGA's internal registers via the DMA channel, bypassing the traditional software driver layer.

[0035] Quality execution unit 5 includes a multi-core DSP cluster. It employs 4 × TITMS320C6678 DSP chips (32-core cluster). The hardware acceleration module includes a data padding circuit (supporting leading / tail zero padding hardware operation) and a format conversion matrix (ASCII / Hex / BCD physical conversion circuit). Abnormal data directly triggers the processing flow via hardware interrupt lines (IRQs), eliminating the need for software scheduling and achieving physical signal flow control. The DIP switch states are mapped to the DSP's microcode execution address via GPIO expanders, achieving hard-wired processing modes.

[0036] The rule expansion unit 6 includes a rule card 61 and a card reader connector 62. The card reader connector 62 is installed inside the housing 1 and forms a slot 63 on the housing. The rule card 61 is pluggably inserted into the slot 63. There are multiple rule cards 61 and card reader connectors 62. Different rule cards 61 contain different rule libraries, and at least one rule card 61 can be inserted into each slot 63. The rule expansion unit 6 is a hardware-level rule library between rule configuration (input) and rule execution (output), and it interacts with the rule compilation unit 4 (FPGA) and the quality execution unit 5 (DSP) through the slot 63. The rule card 61 is a PCIe half-height, half-length board (size: 167.64mm × 111.15mm). The card reader connector 62 uses a gold-finger connector (PCIe x8 interface + custom rule bus), forming multiple rule card slots 61 and 63 (compliant with PICMG 2.0 specifications) on the housing 1, and integrates a hardware logic arbiter (Xilinx CoolRunner-IICPLD). The mechanical structure of the card reader connector 62 uses a reinforced slot 63 with locking screws (vibration withstand 5Grms), supports PCIe Gen3x8 links, and integrates impedance matching circuitry. Onboard components include a rule-fixing chip (NORFlash stores hardware logic description files), a signal repeater (SN65LVDS104 driver chip), and a physical logic gate array (74 series TTL chips implement basic AND / OR logic). Rule configuration methods: Insertion / removal selection: Inserting a "range check card" enables the range check function. Combinatorial logic: When multiple cards are inserted, rule superposition is achieved through the hardware priority circuit of the backplane bus (such as a 74LS148 encoder). Hot-swappable support: The backplane integrates a TPS25982AA load switch, supporting hot-swapping. The rule transmission path is: Rule Card 61 - Backplane Bus - FPGA Configuration Interface + DSP Interrupt Line.

[0037] To facilitate understanding, this embodiment uses the quality control of welding temperature data in an automotive parts production line as an example to provide a detailed explanation of the technical solution:

[0038] Example Implementation Scenario: On an automotive parts production line, the temperature sensor data collected in real time by the welding robot exhibits the following problems: ① Outlier interference: Occasional sensor malfunctions cause temperature values ​​to exceed the reasonable range (e.g., normal welding temperature: 200℃~300℃, but it may suddenly drop to -999℃ or 500℃); ② Excessive fluctuation: Transmission interference causes excessive temperature differences between adjacent data points (e.g., the process requires fluctuation ≤30℃ / second, but it actually reaches >50℃); ③ Format errors: The temperature value is displayed incorrectly in the data protocol (e.g., it should be a 3-digit integer in the format "250", but it often appears in formats such as "2A5", "251.3", etc., containing decimals or mixed characters); To solve the above problems, operators can perform the following operations:

[0039] Step 1, Hardware Initialization: Connect the device to the production line data bus through the data input interface 2 (e.g., SFP+ optical port) on the housing 1, turn on the power of the rule configuration panel 3, and the touch screen 31 will automatically load the welding process preset template.

[0040] Step 2, configure low-code rules through the rule configuration panel 3:

[0041] 2.1. Field location (operated via touchscreen 31):

[0042] In the grid interface of the touch screen 31, the operator can slide their finger (for example, slide the finger horizontally to the third column to map the temperature data field); the finger can also click (for example, click the "numerical" area vertically to define the data type); indicator lights can be set on the touch screen 31 to indicate hardware response (for example, the panel LED indicator turns green to indicate that the identification field is successfully bound).

[0043] 2.2. Threshold setting (operated via mechanical knob 32):

[0044] There can be multiple mechanical knobs 32, such as three. Operators can adjust different threshold parameters by rotating different mechanical knobs 32. Different colored areas can be set around the mechanical knobs 32 for easy and quick positioning. For example, rotating the first "upper limit range knob" on the left to 300 will cause the scale pointer to point to the orange area; or rotating the middle "lower limit range knob" to 200 will cause the scale pointer to point to the blue area; or rotating the "volatility knob" to 30 will cause the digital LED to display "Δ30℃ / s". The resulting hardware response is that the reference voltage of the FPGA's internal comparator circuit is automatically adjusted to 2.0V~3.0V.

[0045] 2.3. Rule Expansion (via inserting rule card 61):

[0046] There can be multiple card reader connectors 62, forming multiple slots 63 on the housing 1. In some cases, special rule processing is required for a certain set of data. In this case, the operator can insert one or more rule cards 61 to achieve rule expansion. After inserting the rule card 61, the corresponding card reader connector 62 can be controlled to start reading and loading the rule through the switch group 33 or mechanical button 34.

[0047] 2.4 Rule Combinations (DIP Switch Operation):

[0048] Switch groups 33 can be configured, for example, into four groups, each controlling a different function via DIP switches. For instance, the first, second, third, and fourth switch groups 33 can be set sequentially to ON-ON-OFF-ON (corresponding to enabling range checking, volatility detection, disabling format verification, and enabling hardware truncation of abnormal data, respectively). The resulting hardware response is a backplane bus generation rule enable signal (binary code).

[0049] Step 3: Real-time quality processing is performed through rule compilation unit 4 and quality execution unit 5:

[0050] 3.1 Anomaly Detection (via FPGA chipset):

[0051] When an abnormal value (e.g., "-999") is detected, the shift register in the FPGA chipset triggers an abnormal length (3-4 bits), and the comparator circuit outputs an over-limit signal (voltage < 2.0V); when the temperature difference between adjacent data reaches an abnormal value (e.g., "55℃"), the amplifier circuit outputs a voltage exceeding the set threshold, and the pulse counter triggers an over-limit.

[0052] 3.2 Execution Processing (via DSP Cluster):

[0053] For handling outliers (e.g., "-999"), the processing flow is directly triggered via a hardware interrupt line (IRQ) to discard the data packet, clear low-quality / erroneous data, and implement data quality configuration. An alarm light can also be configured to provide a notification. For fluctuations exceeding the limit (e.g., "55℃"), the moving average filter circuit automatically inserts a smoothing value, and the anomaly counter displays the cumulative number of occurrences, thus implementing data quality configuration.

[0054] In summary, the rule configuration panel 3 provides a visual / physical interface, directly mapping user operations to hardware signals. Parameters such as data field location, verification type, and threshold range can be defined without writing code, significantly reducing configuration time compared to traditional data quality management processes that require coding. The rule compilation unit 4 (e.g., FPGA) converts user configurations into hardware-executable logic, achieving rule deployment through circuit reconstruction rather than software compilation, greatly shortening rule activation time. The quality execution unit 5, through physical devices such as comparator circuits and shift registers, can be directly triggered by hardware interrupt signals during exception handling, avoiding latency and unreliability caused by the software stack. The rule extension unit 6 allows for pluggable new rule modules with automatic loading functionality, eliminating the need for driver installation or software updates. Therefore, this device enables data quality configuration processing by setting configuration parameters through hardware devices and simple external input devices (such as buttons, knobs, and drag-and-drop components), requiring minimal user coding. This eliminates dependence on software development environments while ensuring performance, achieving low-code, rapid data quality configuration.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A low-code-based data quality rapid configuration device, characterized in that, It includes the shell, data input interface, rule configuration panel, rule compilation unit, quality execution unit, and rule extension unit; The data input interface and the rule configuration panel are respectively mounted on the housing of the outer shell; The rule compilation unit and the quality processing execution unit are respectively installed inside the outer casing; The rule extension unit is installed inside the housing, and an extension interface is provided on the housing. The rule configuration panel and the rule extension unit are electrically connected to the rule compilation unit, and the data input interface and the rule compilation unit are electrically connected to the quality execution unit.

2. The low-code-based rapid data quality configuration device according to claim 1, characterized in that, The rule configuration panel includes a touch screen, through which data features are selected via a graphical interface.

3. The low-code-based rapid data quality configuration device according to claim 2, characterized in that, The rule configuration panel includes a mechanical knob for adjusting threshold parameters.

4. The low-code-based rapid data quality configuration device according to claim 3, characterized in that, The rule configuration panel includes a group of DIP switches, and rule logic is generated through different combinations of the DIP switches.

5. The low-code-based rapid data quality configuration device according to claim 4, characterized in that, The rule configuration panel includes mechanical buttons for mode selection.

6. The low-code-based rapid data quality configuration device according to claim 1, characterized in that, The rule compilation unit includes an FPGA chipset, onboard memory, and a multi-channel PCIe interface.

7. The low-code-based rapid data quality configuration device according to claim 6, characterized in that, The FPGA chipset has various data quality rule hardware description files pre-programmed on it.

8. The low-code-based rapid data quality configuration device according to claim 6, characterized in that, The quality execution unit includes a multi-core DSP cluster.

9. The low-code-based rapid data quality configuration device according to claim 8, characterized in that, The rule extension unit includes a rule card and a card reader connector. The card reader connector is installed inside the housing and forms a slot on the housing. The rule card can be plugged into the slot.

10. The low-code-based rapid data quality configuration device according to claim 9, characterized in that, There are multiple rule cards and card reader connectors. Different rule cards are engraved with different rule libraries. At least one rule card can be inserted into each slot.

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