Deposition mask

Abstract

The deposition mask includes a cell region, a cell periphery region surrounding the cell region, and a grid region positioned between the cell region and the cell periphery region in a planar view. The deposition mask includes: a mask septum disposed in the cell region, the mask septum including a mask masking element and defining pixel openings within the mask septum; a mask frame disposed in the cell periphery region and the grid region; and a plurality of ruler patterns disposed in the grid region, wherein the plurality of ruler patterns are adjacent to each other in a direction parallel to the main surface of the mask frame and spaced apart by equal intervals.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0047243, filed on April 8, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to deposition masks. Background Technology

[0004] Wearable devices, developed in the form of glasses or helmets, are being developed that focus on a distance close to the user's eyes. For example, the wearable device could be a head-mounted display (“HMD”) device or augmented reality (hereinafter referred to as “AR”) glasses. Such wearable devices provide users with AR or virtual reality (hereinafter referred to as “VR”) visuals.

[0005] Wearable devices such as HMD devices or AR glasses require a display specification of at least 2000 pixels per inch (“PPI”) to allow users to use the wearable device for extended periods without experiencing dizziness. For this purpose, organic light-emitting diodes on silicon (“OLEDoS”) technology is emerging as a small, high-resolution organic light-emitting display device. OLEDoS is a technology that sets organic light-emitting diodes (“OLEDs”) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (“CMOS”) is disposed. Utility Model Content

[0006] This disclosure provides a deposition mask capable of manufacturing high-resolution display panels.

[0007] This disclosure also provides a deposition mask capable of measuring the positional accuracy of pixel openings.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0009] Details of other embodiments are included in the detailed description and accompanying drawings.

[0010] In embodiments of this disclosure, the deposition mask includes a cell region, a cell periphery region surrounding the cell region, and a grid region positioned in a plan view between the cell region and the cell periphery region. The deposition mask includes: a mask septum disposed in the cell region, the mask septum including a mask shield and defining pixel openings within the mask septum; a mask frame disposed in the cell periphery region and the grid region; and a plurality of ruler patterns disposed in the grid region, wherein the plurality of ruler patterns are adjacent to each other and spaced at equal intervals in a direction parallel to the main surface of the mask frame.

[0011] In an embodiment, the mask frame may include a mask base disposed in the peripheral region of the cell and an upper inorganic layer positioned on the mask base, and the upper inorganic layer may include a protrusion that protrudes toward the cell region from the side surface of the mask base that is positioned toward the cell region.

[0012] In one embodiment, the protrusions of the upper inorganic layer are disposed in the grid area.

[0013] In an embodiment, multiple ruler patterns can be positioned on the upper inorganic layer, and the multiple ruler patterns overlap with the protrusions of the upper inorganic layer in a direction perpendicular to the main surface of the mask frame.

[0014] In an embodiment, the height of each of the plurality of scale patterns in a direction perpendicular to the main surface of the mask frame may be greater than or equal to 0.2 micrometers and less than or equal to 3.0 micrometers.

[0015] In an embodiment, the height of each of the plurality of scale patterns in a direction perpendicular to the main surface of the mask frame may be greater than or equal to 50 nanometers and less than or equal to 500 nanometers.

[0016] In an embodiment, the gap between adjacent ruler patterns in a direction parallel to the main surface of the mask frame can be greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.

[0017] In an embodiment, in a cross-sectional view, each of the plurality of scale patterns may have at least one of a cylindrical shape, a trapezoidal shape, and an inverted tapering shape, wherein the angle of inclination formed by the first side surface and the second side surface is an obtuse angle.

[0018] In an embodiment, at least one of the plurality of ruler patterns can be positioned at a predetermined location pointing to a pixel opening.

[0019] In an embodiment, the deposition mask includes a cell region, a cell periphery region surrounding the cell region, and a grid region positioned between the cell region and the cell periphery region in a plan view. The deposition mask includes: a mask septum disposed in the cell region, the mask septum defining pixel openings in the mask septum and including mask masking members surrounding the pixel openings; a mask frame disposed in the cell periphery region and the grid region and defining mask openings in the mask frame; and a plurality of ruler patterns disposed in the grid region, wherein, in a plan view, the plurality of ruler patterns are positioned adjacent to each other and spaced apart by equal intervals.

[0020] In an embodiment, in a planar view, the gap between adjacent scale patterns among a plurality of scale patterns can be greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.

[0021] According to the deposition mask of the embodiment, a deposition mask for manufacturing a high-resolution display panel can be provided by forming a mask septum in the portion overlapping with the cell region of the mask substrate. Furthermore, the deposition mask of the embodiment can measure the positional accuracy of pixel apertures by forming a nanoscale pattern in the portion overlapping with the grid region of the mask substrate.

[0022] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon which they pertain by referring to the claims. Attached Figure Description

[0023] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0024] Figure 1 This is a perspective view showing a head-mounted electronic device according to an embodiment;

[0025] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted electronic device;

[0026] Figure 3 This is a perspective view showing a head-mounted electronic device according to an embodiment;

[0027] Figure 4 This is an exploded perspective view showing a display device according to an embodiment;

[0028] Figure 5 This is a cross-sectional view showing an example of a portion of the display panel being cut according to an embodiment;

[0029] Figure 6 This is a schematic plan view of the mask according to an embodiment;

[0030] Figure 7 yes Figure 6 An enlarged plan view of region A;

[0031] Figure 8 It is along Figure 7 A cross-sectional view taken by line X1-X1';

[0032] Figure 9 yes Figure 7 An enlarged plan view of region C;

[0033] Figure 10 It is along Figure 9 A cross-sectional view taken from line C1-C1'; and

[0034] Figures 11 to 13 This illustrates other embodiments. Figure 10 Cross-sectional views of various shapes of the ruler pattern. Detailed Implementation

[0035] The present invention will now be described more fully below with reference to the accompanying drawings, which illustrate various embodiments. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0036] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or an intermediary element may exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, no intermediary element exists.

[0037] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms containing “at least one.” Thus, in the claims, a reference to “the” element following a reference to “a” element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises” and / or “includes” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0039] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other elements will subsequently be oriented to be “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other elements will subsequently be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0040] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “approximately” or “about” as used herein include stated values ​​and mean within an acceptable range of deviation from a particular value as determined by one of ordinary skill in the art. For example, a term such as “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0042] Embodiments are described herein with reference to cross-sectional views as schematic representations of idealized embodiments. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to factors such as manufacturing. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0043] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a perspective view showing a head-mounted electronic device according to an embodiment. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted electronic device.

[0045] Reference Figure 1 and Figure 2 According to an embodiment, the head-mounted electronic device 1 includes a display device housing portion 110, a housing portion cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted strap 140, a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector.

[0046] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Each of the first display device 10_1 and the second display device 10_2 is associated with a reference. Figure 4 and Figure 5 The described display devices 10 are substantially the same. Therefore, the descriptions of the first display device 10_1 and the second display device 10_2 will be based on reference. Figure 4 and Figure 5 The description is replaced by [the description].

[0047] The first optical component 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical component 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical component 151 and the second optical component 152 may include at least one convex lens.

[0048] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can also be disposed between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0049] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing portion 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 170 can convert externally input image sources into digital video data, and can transmit the digital video data to the first display device 10_1 and the second display device 10_2 via connectors.

[0050] The control circuit board 170 can transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 can transmit the same digital video data to both the first display device 10_1 and the second display device 10_2.

[0051] The display device receiving portion 110 is used to house a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical component 151, a second optical component 152, a control circuit board 170, and a connector. The receiving portion cover 120 is configured to cover an opening in the display device receiving portion 110. The receiving portion cover 120 may include a first eyepiece 131 for the user's left eye and a second eyepiece 132 for the user's right eye. Figure 1 and Figure 2 The illustration shows the first eyepiece 131 and the second eyepiece 132 being disposed separately, but the embodiments described herein are not limited thereto. In another embodiment, the first eyepiece 131 and the second eyepiece 132 may be integrated into one unit.

[0052] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical component 152. Therefore, the user can observe the image of the first display device 10_1 magnified into a virtual image by the first optical component 151 through the first eyepiece 131, and can observe the image of the second display device 10_2 magnified into a virtual image by the second optical component 152 through the second eyepiece 132.

[0053] A headband 140 is used to secure the display device housing 110 to the user's head, such that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are respectively positioned over the user's left and right eyes. When the display device housing 110 is implemented in a lightweight and small size, the head-mounted electronic device 1 may include, for example... Figure 3 The eyeglasses frame shown is not the headband 140.

[0054] In addition, the head-mounted electronic device 1 may also include a battery for supplying power, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (“USB”) terminal, a display port, or a High Definition Multimedia Interface (“HDMI”) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0055] Figure 3 This is a perspective view showing a head-mounted electronic device according to an embodiment.

[0056] Reference Figure 3 According to an embodiment, the head-mounted electronic device 1_1 can be an eyeglass-type display device in which the display device housing portion 120_1 is implemented in a lightweight and small size. The head-mounted electronic device 1_1 according to an embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, eyeglass frame temples 341 and 342, an optical component 320, an optical path conversion component 330, and the display device housing portion 120_1.

[0057] Figure 3 The display device 10_3 shown is the same as the reference. Figure 4 and Figure 5 The described display device 10 is essentially the same. Therefore, the description of the display device 10_3 will be based on reference 10_3. Figure 4 and Figure 5 The description is replaced by [the description].

[0058] The display device housing 120_1 may include a display device 10_3, an optical component 320, and a light path conversion component 330. Since the image displayed on the display device 10_3 is magnified by the optical component 320 and the light path of the image is converted by the light path conversion component 330, the image can be provided to the user's right eye through the right eye lens 312. Therefore, the user can observe an augmented reality image, in which the virtual image displayed on the display device 10_3 and the real image observed through the right eye lens 312 are combined, through their right eye.

[0059] Figure 3 The illustration shows the display device receiving portion 120_1 located at the right end of the support frame 350, but the embodiments described herein are not limited thereto. For another example, the display device receiving portion 120_1 may be located at the left end of the support frame 350, and in this case, the image from the display device 10_3 can be provided to the user's left eye. Alternatively, the display device receiving portion 120_1 may be located at both the left and right ends of the support frame 350. In this case, the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0060] Figure 4 This is an exploded perspective view showing a display device according to an embodiment.

[0061] Reference Figure 4 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs (“PCs”), mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (“PMPs”), navigation devices, and ultra-mobile PCs (“UMPCs”). For example, the display device 10 can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (“IoT”) device. Alternatively, the display device 10 can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0062] The display device 10 according to an embodiment includes a display panel 410, a heat dissipation layer 420, a circuit board 430, a driving circuit 440, and a power supply circuit 450.

[0063] The display panel 410 may have a planar shape similar to a quadrilateral. For example, the display panel 410 may have a planar shape similar to a quadrilateral having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). In the display panel 410, the corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect each other may be formed at right angles, or may have a circular shape with a predetermined curvature. The planar shape of the display panel 410 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the embodiments described in this specification are not limited thereto.

[0064] The display panel 410 includes a display area for displaying images and a non-display area for not displaying images.

[0065] The display area comprises multiple pixels, and each of these pixels comprises multiple subpixels. Figure 5 The sub-pixels SP1, SP2, and SP3 are mentioned. Multiple sub-pixels SP1, SP2, and SP3 comprise multiple pixel transistors. These pixel transistors can be formed using semiconductor processes and can be disposed on a semiconductor substrate (…). Figure 5 On a semiconductor substrate (SSUB). For example, multiple pixel transistors can be formed from complementary metal-oxide-semiconductor (CMOS).

[0066] The heat dissipation layer 420 may overlap with the display panel 410 in a third direction (Z-axis direction) that is the thickness direction of the display panel 410. The heat dissipation layer 420 may be disposed on one surface of the display panel 410 (e.g., the rear surface of the display panel 410). The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include graphite or metal (such as silver (Ag), copper (Cu), or aluminum (Al)) with high thermal conductivity.

[0067] The circuit board 430 can be electrically connected to multiple pads PD of the PDA in the pad area of ​​the display panel 410 using conductive adhesive components such as anisotropic conductive films. The circuit board 430 can be a flexible printed circuit board or a flexible film made of flexible materials. Figure 4 The circuit board 430 is shown unfolded, but it can be bent. In this case, one end of the circuit board 430 can be disposed on the rear surface of the display panel 410. One end of the circuit board 430 can be the opposite end of the other end of a plurality of pads PD of the circuit board 430 which are connected to the pad area PDA of the display panel 410 by means of conductive adhesive.

[0068] The driving circuit 440 can receive digital video data and timing signals from the outside. The driving circuit 440 can generate scanning timing control signals, transmission timing control signals and data timing control signals for controlling the display panel 410 according to the timing signals.

[0069] The power supply circuit 450 can generate multiple panel drive voltages based on the power supply voltage from the outside.

[0070] The drive circuit 440 and the power supply circuit 450 may each be formed as an integrated circuit (“IC”) and attached to a surface of the circuit board 430.

[0071] Figure 5 This is a cross-sectional view showing an example of a portion of a display panel according to an embodiment being cut. For example, Figure 5 It shows multiple sub-pixels ( Figure 5 The partial cross-sectional structure of the display area of ​​the sub-pixels SP1, SP2 and SP3 in the image.

[0072] Reference Figure 5 The display panel 410 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, an encapsulation layer TFE, a polarizing plate POL, and a cover layer CVL.

[0073] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs).

[0074] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a type I impurity. Multiple well regions WA can be disposed on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a type II impurity. The type II impurity can be different from the type I impurity described above. For example, when the type I impurity is a p-type impurity, the type II impurity can be an n-type impurity. Alternatively, when the type I impurity is an n-type impurity, the type II impurity can be a p-type impurity.

[0075] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate containing polyimide, etc. In this case, the thin film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0076] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0077] Each of the source region SA and drain region DA can be a region doped with a type I impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA in the third direction (Z-axis direction). The channel region CH can overlap with the gate electrode GE in the third direction (Z-axis direction). The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0078] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed based on silicon carbonitride (SiCN) or silicon oxide (SiO). x The inorganic membranes described herein are not limited to these examples.

[0079] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed based on silicon oxide (SiO2). x The inorganic membranes described herein are not limited to these examples.

[0080] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0081] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The upper surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be formed based on silicon oxide (SiO2). x The inorganic membranes described herein are not limited to these examples.

[0082] The backplane (EBP) of the light-emitting element includes a first metal layer ML1 to an eighth metal layer ML8, reflective electrodes RL1 to RL4, multiple vias VA1 to VA10, and a step layer STPL. Furthermore, the backplane (EBP) of the light-emitting element also includes multiple interlayer insulating films INS1 to INS10.

[0083] The first metal layers ML1 to the eighth metal layers ML8 are used to implement the circuitry of the sub-pixel SP by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP.

[0084] A first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating film INS1 and connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may connect to the first via VA1.

[0085] A second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may be connected to the first metal layer ML1 exposed by penetrating the second interlayer insulating film INS2. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second via VA2.

[0086] A third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may be connected to the second metal layer ML2 exposed by penetrating the third interlayer insulating film INS3. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third via VA3.

[0087] A fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may be connected to the third metal layer ML3 exposed by penetrating the fourth interlayer insulating film INS4. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via VA4.

[0088] A fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may be connected to the fourth metal layer ML4 exposed by penetrating the fifth interlayer insulating film INS5. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth via VA5.

[0089] A sixth interlayer insulating film INS6 can be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 can be connected to the fifth metal layer ML5 exposed by penetrating the sixth interlayer insulating film INS6. Each of the sixth metal layers ML6 can be disposed on the sixth interlayer insulating film INS6 and can be connected to the sixth via VA6.

[0090] A seventh interlayer insulating film INS7 can be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can be connected to the sixth metal layer ML6 exposed by penetrating the seventh interlayer insulating film INS7. Each of the seventh metal layers ML7 can be disposed on the seventh interlayer insulating film INS7 and can be connected to the seventh via VA7.

[0091] An eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may be connected to the seventh metal layer ML7 exposed by penetrating the eighth interlayer insulating film INS8. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via VA8.

[0092] The first metal layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first metal layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first vias VA1 to VA8 can be formed of substantially the same material. The first interlayer insulating film INS1 to INS8 can be formed as a silicon oxide (SiO2) based material. x The inorganic membranes described herein are not limited to these examples.

[0093] The thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can each be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. Each of the following thicknesses can be greater than the thickness of the first metal layer ML1: ML2, ML3, ML4, ML5, and ML6: ML2, ML3, ML4, ML5, and ML6. The thicknesses of the second metal layer ML2, ML3, ML4, ML5, and ML6 can be substantially the same.

[0094] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can each be greater than the thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can each be greater than the thickness of the seventh via VA7 and the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 can each be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can be substantially the same.

[0095] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 can be formed based on silicon oxide (SiO2). x The inorganic membranes described herein are not limited to these examples.

[0096] Each of the ninth vias VA9 can be connected to the eighth metal layer ML8 exposed by penetrating the ninth interlayer insulating film INS9. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0097] Each of the first reflective electrodes RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrode RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy thereof.

[0098] Each of the second reflective electrodes RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof or a nitride thereof. For example, the second reflective electrode RL2 can be formed of titanium nitride (TiN).

[0099] In the portion overlapping with the first sub-pixel SP1, a stepped layer STPL can be formed on the second reflective electrode RL2. In the portions overlapping with the second sub-pixel SP2 and the third sub-pixel SP3, the stepped layer STPL may not be formed. The stepped layer STPL can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes are formed, but the embodiments in this specification are not limited thereto.

[0100] In the portion overlapping with the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2 and the stepped layer STPL. In the portion overlapping with the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0101] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may comprise a metal with high reflectivity to facilitate light reflection. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of APC alloy and ITO (ITO / APC / ITO), but the embodiments described herein are not limited thereto.

[0102] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 can be formed based on silicon oxide (SiO2). x The inorganic membranes described herein are not limited to these examples.

[0103] Each of the tenth vias VA10 can be connected to the fourth reflective electrode RL4 exposed by penetrating the tenth interlayer insulating film INS10. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them. Due to the stepped layer STPL, the thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in each of the second sub-pixels SP2 and the third sub-pixel SP3.

[0104] The light-emitting element layer (EML) can be disposed on the light-emitting element backplane (EBP). The EML can include light-emitting elements (LE) and pixel-defining layers (PDL), each of the light-emitting elements (LE) including a first electrode (AND), a light-emitting layer (IL), and a second electrode (CAT).

[0105] The first electrode AND can be disposed on the tenth interlayer insulating film INS10 and can be connected to the tenth via VA10. The first electrode AND can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride thereof. For example, the first electrode AND can be formed of titanium nitride (TiN).

[0106] A pixel-defining layer (PDL) can be disposed on a portion of the first electrode AND. The PDL can cover the edge of the first electrode AND. The PDL is used to separate the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0107] The first light-emitting region EA1 can be defined as the region in which the first electrode AND, the first light-emitting layer IL1, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light-emitting region EA2 can be defined as the region in which the first electrode AND, the second light-emitting layer IL2, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light-emitting region EA3 can be defined as the region in which the first electrode AND, the third light-emitting layer IL3, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0108] The pixel definition layer (PDL) may include a first pixel definition layer (PDL1), a second pixel definition layer (PDL2), and a third pixel definition layer (PDL3). The first pixel definition layer (PDL1) may be disposed on the edge of the first electrode AND, the second pixel definition layer (PDL2) may be disposed on the first pixel definition layer (PDL1), and the third pixel definition layer (PDL3) may be disposed on the second pixel definition layer (PDL2). The first pixel definition layer (PDL1), the second pixel definition layer (PDL2), and the third pixel definition layer (PDL3) may be formed based on silicon oxide (SiO2). x The inorganic membranes described herein are not limited to these examples.

[0109] The light-emitting layer IL may include a first light-emitting layer IL1, a second light-emitting layer IL2, and a third light-emitting layer IL3. The first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3 may emit light of different colors. As an example, the first light-emitting layer IL1 may emit red light, the second light-emitting layer IL2 may emit green light, and the third light-emitting layer IL3 may emit blue light, but this disclosure is not limited thereto.

[0110] The first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3, which are arranged adjacent to each other in the first direction (X-axis direction), can be disconnected by the pixel limiting layer PDL. According to the embodiment, the display panel 410 can prevent leakage current between the sub-pixels SP1, SP2, and SP3 arranged adjacent to each other, and prevent color interference by disconnecting the first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3 arranged adjacent to each other.

[0111] The second electrode CAT can be disposed on the light-emitting layer IL. The second electrode CAT can be a common electrode. The second electrode CAT can be formed of a transparent conductive oxide (“TCO”) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be increased by a microcavity in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0112] The encapsulation layer TFE can be disposed on the light-emitting element layer EML. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. For example, the encapsulation layer TFE may include a first encapsulation layer TFE1 and a second encapsulation layer TFE2.

[0113] A first encapsulation layer TFE1 can be disposed on the second electrode CAT, and a second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1. The first encapsulation layer TFE1 and the second encapsulation layer TFE2 can be formed such that a silicon nitride layer (SiN) is formed therein. x ), silicon oxynitride layer (SiO) x N y ), silicon oxide layer (SiO) x ), titanium oxide layer (TiO) x ) and aluminum oxide layer (AlO x A multilayer membrane structure in which one or more inorganic membranes are stacked alternately.

[0114] The adhesive layer APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The adhesive layer APL can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0115] A cover layer CVL can be applied to an adhesive layer APL. The cover layer CVL can be a glass substrate or comprise a polymer resin. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate, and when it comprises a polymer resin, it can be applied directly to the adhesive layer APL.

[0116] A polarizing plate (POL) can be disposed on one surface of the CVL (container layer). The polarizing plate (POL) can be a structure used to prevent visibility degradation due to reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. As an example, the phase retardation film can be a λ / 4 (quarter-wave) plate, but the embodiments described in this specification are not limited thereto.

[0117] Figure 6 This is a schematic plan view of the mask according to an embodiment. Figure 7 yes Figure 6 A magnified plan view of region A. Figure 6 The mask (or deposition mask) shown in the embodiment can be used for deposition reference. Figure 5 The process of at least a portion of the light-emitting layer IL of the described display panel 410.

[0118] Reference Figure 6 and Figure 7According to the embodiments, the mask MK can be a mask for manufacturing ultra-high resolution displays. As an example, the mask MK can be a mask for manufacturing displays included in extended reality (“XR”) devices such as VR devices, AR devices, or MR devices.

[0119] According to the embodiments, the mask MK can be used to perform sub-pixelation on a silicon wafer rather than on a large substrate used in conventional displays. Figure 5 The deposition process of subpixels SP1, SP2, and SP3 in the image. In the case of a display included in an extended reality device, since the screen of the display is positioned directly in front of the user's eyes, the display can have a small screen rather than a large screen area. Furthermore, since the display is positioned close to the user's eyes, ultra-high resolution is expected. For example, a display included in an extended reality device may require a resolution of approximately 1000 PPI or higher, and preferably an ultra-high resolution of 2000 PPI or higher. Therefore, the mask MK according to the embodiment can be a mask for manufacturing such an ultra-high resolution display. The mask MK according to the embodiment may include, as will be referred to later... Figures 9 to 13 All masks MK1, MK3, MK5, and MK7 are described.

[0120] According to an embodiment, the mask MK may include a mask substrate MSUB.

[0121] The mask substrate MSUB according to an embodiment may include a silicon wafer. Because silicon wafers can be fabricated more finely and precisely than large-area substrates by utilizing techniques developed in semiconductor processes, silicon wafers can be used as substrates for ultra-high resolution displays. The mask MK according to an embodiment can use the same silicon wafer to form pixels on the silicon wafer of such an ultra-high resolution display.

[0122] According to an embodiment, the mask substrate (MSUB) can have a shape corresponding to the silicon wafer of an ultra-high resolution display. For example, the mask substrate (MSUB) can have the same size or shape as the silicon wafer of an ultra-high resolution display. However, the mask substrate (MSUB) is not limited to this, and in another embodiment it can also include a large-area substrate. For example, the mask substrate (MSUB) can also include materials such as glass, quartz, and polymer resin.

[0123] According to the embodiments, the mask MK may include multiple cell regions CA, grid regions GA, and cell perimeter regions CRA.

[0124] According to an embodiment, multiple cell regions CA can be formed, and the multiple cell regions CA can be positioned spaced apart from each other. The cell region CA can be positioned as a portion overlapping with the mask opening COP.

[0125] In a planar view, the cell region CA can be a region overlapping with the mask diaphragm MM. The mask diaphragm MM can include a mask masking element MS and define a pixel opening SOP within the mask diaphragm MM. In a planar view, the mask masking element MS can be integrally formed around the entire pixel opening SOP. In other words, in a planar view, the mask masking element MS can be a pattern integrally formed while exposing the pixel opening SOP.

[0126] According to an embodiment, the mesh region GA can be positioned between the cell region CA and the cell periphery region CRA. In a plan view, the mesh region GA can be positioned to completely surround the cell region CA. In other words, in a plan view, the mesh region GA can completely surround the mask opening COP.

[0127] In a planar view, the grid region GA can be the area overlapping with the scale pattern LP. Multiple scale patterns LP can be set in the area overlapping with the grid region GA. In a planar view, multiple scale patterns LP can surround the mask opening COP and be spaced at regular intervals.

[0128] In a planar view, multiple scale patterns LP may not overlap with the mask diaphragm MM and the mask frame MF. In other words, in a planar view, multiple scale patterns LP may not overlap with the element region CA and the element perimeter region CRA. The main surface of the mask frame MF may be parallel to the X-axis and Y-axis directions. As used herein, a “planar view” is a view in a direction perpendicular to the main surface of the mask frame MF (Z-axis direction).

[0129] According to the embodiment, the cell perimeter region CRA can be positioned around the grid region GA. The cell perimeter region CRA can be positioned around each cell region CA and the grid region GA.

[0130] In the planar view, the outer region CRA of the cell can be the area overlapping with the mask frame MF. The mask frame MF can support the mask MK. In the planar view, the mask frame MF can surround the entire scale pattern LP and the entire mask diaphragm MM. In other words, in the planar view, the mask frame MF can surround the entire mask opening COP.

[0131] Figure 8 It is along Figure 7 The cross-sectional view taken by line X1-X1'.

[0132] Reference Figure 8 According to the embodiment, the mask frame MF can be positioned in the plan view in the portion overlapping with the cell periphery region CRA and the mesh region GA. The mask frame MF may include a mask substrate MSUB, a first upper inorganic layer U1, and a second upper inorganic layer U2.

[0133] In some embodiments, the mask substrate MSUB may include an upper surface s1, a lower surface s2, and a side surface s3. The upper surface s1 may be a surface facing the first upper inorganic layer U1, the lower surface s2 may be a surface opposite to the upper surface s1, and the side surface s3 may be a surface connecting the upper surface s1 and the lower surface s2. The side surface s3 of the mask substrate MSUB may be an inclined surface. This may be due to a portion of the mask substrate MSUB being removed by an etching process during the manufacturing process of the mask MK.

[0134] According to the embodiment, the first upper inorganic layer U1 can be positioned on the mask substrate MSUB. The first upper inorganic layer U1 can contact the upper surface s1 of the mask substrate MSUB and can cover the entire upper surface s1.

[0135] According to an embodiment, the first upper inorganic layer U1 may include a protrusion P1 that protrudes from the side surface s3 of the mask substrate MSUB toward the cell region CA. The protrusion P1 of the first upper inorganic layer U1 may be a portion that protrudes from the side surface s3 of the mask substrate MSUB in a first direction (X-axis direction). Therefore, an undercut can be formed between the side surface s3 of the mask substrate MSUB and the protrusion P1 of the first upper inorganic layer U1.

[0136] The first upper inorganic layer U1 may include an inorganic insulating material. As an example, the first upper inorganic layer U1 may include any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0137] According to the embodiment, the second upper inorganic layer U2 can be positioned on the first upper inorganic layer U1. The second upper inorganic layer U2 can contact the first upper inorganic layer U1 and can cover the entire first upper inorganic layer U1.

[0138] According to an embodiment, the second upper inorganic layer U2 may include a protrusion P2 that protrudes from the side surface s3 of the mask substrate MSUB toward the cell region CA. The protrusion P2 of the second upper inorganic layer U2 may be a portion that protrudes from the side surface s3 of the mask substrate MSUB in a first direction (X-axis direction). Therefore, an undercut can be formed between the side surface s3 of the mask substrate MSUB and the protrusion P2 of the second upper inorganic layer U2.

[0139] The second upper inorganic layer U2 may include an inorganic insulating material. As an example, the second upper inorganic layer U2 may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The second upper inorganic layer U2 may include the same material as the masking element MS, which will be described later. Details will be described later.

[0140] According to the embodiments, the first upper inorganic layer U1 and the second upper inorganic layer U2 can have different stress properties. As an example, when the first upper inorganic layer U1 comprises an inorganic insulating material with compressive stress, the second upper inorganic layer U2 can comprise an inorganic insulating material with tensile stress. The stress of the mask MK1 according to the embodiments can be adjusted by forming the first upper inorganic layer U1 and the second upper inorganic layer U2 with stresses having different physical properties. Furthermore, the first upper inorganic layer U1 and the second upper inorganic layer U2 according to the embodiments can have etch ratios with different physical properties.

[0141] According to the embodiment, the first upper inorganic layer U1 can be omitted. When the first upper inorganic layer U1 is omitted, the second upper inorganic layer U2 can be positioned to contact the upper surface s1 of the mask substrate MSUB.

[0142] The protrusion P1 of the first upper inorganic layer U1 and the protrusion P2 of the second upper inorganic layer U2 can be positioned in the portion overlapping with the grid region GA. In other words, the area where the protrusion P1 of the first upper inorganic layer U1 and the protrusion P2 of the second upper inorganic layer U2 are positioned can be defined as the grid region GA. Since the first upper inorganic layer U1 and the second upper inorganic layer U2 have different etching ratios during the mask MK manufacturing process, the protrusion P1 of the first upper inorganic layer U1 and the protrusion P2 of the second upper inorganic layer U2 can be formed.

[0143] In the portion overlapping with the grid region GA, the protrusion P2 of the second upper inorganic layer U2 can be positioned to contact the protrusion P1 of the first upper inorganic layer U1. In the portion overlapping with the grid region GA, the protrusion P2 of the second upper inorganic layer U2 can protrude towards the cell region CA more than the protrusion P1 of the first upper inorganic layer U1. Therefore, an undercut can be formed between the protrusion P1 of the first upper inorganic layer U1 and the protrusion P2 of the second upper inorganic layer U2.

[0144] According to an embodiment, the mask diaphragm MM can be positioned in the portion overlapping with the cell region CA. The mask diaphragm MM may include a plurality of mask shielding elements MS and define pixel openings SOPs in the mask diaphragm MM.

[0145] Pixel aperture SOPs can be positioned between multiple masking elements MS that are adjacent to each other. Pixel aperture SOPs can be named "holes" or "mask holes". Multiple pixel aperture SOPs can penetrate the mask frame MF along the thickness direction of the mask MK (e.g., the third direction (Z-axis direction)). During the manufacturing process of the mask MK, multiple pixel aperture SOPs can be formed by etching portions of the mask substrate MSUB, the first upper inorganic layer U1, and the second upper inorganic layer U2 from the direction of the lower surface s2 of the mask substrate MSUB.

[0146] The masking element MS can be positioned around the pixel opening SOP. Multiple masking elements MS can be used to mask the substrate to be deposited as the deposited material evaporates from the deposition source inside the deposition apparatus (e.g., Figure 4 The blocking portion of the display panel 410 or back panel substrate. Therefore, the deposition material generated from the deposition source can be deposited on the surface of the substrate to be deposited (e.g., display panel 410 or back panel substrate) through the pixel opening SOP.

[0147] According to an embodiment, the mask masking element MS can be spaced apart from the second upper inorganic layer U2, and the pixel opening SOP is located between the mask masking element MS and the second upper inorganic layer U2. The mask masking element MS and the second upper inorganic layer U2 may comprise the same material. In the manufacturing process of the mask MK, the mask masking element MS and the second upper inorganic layer U2 can be integrally formed and then formed into the shape shown by a subsequent etching process.

[0148] In some embodiments, the height Hms of the masking element MS may be equal to, but is not limited to, the height Hu2 of the second upper inorganic layer U2. As used herein, the “height” of an object may be the length of the object in the Z-axis direction.

[0149] In some embodiments, the masking element MS may have an inverted tapered shape, but is not limited thereto.

[0150] Figure 9 yes Figure 7 A magnified plan view of region C.

[0151] Reference Figure 9 In a plan view, multiple ruler patterns LP can be positioned in the portion that overlaps with the grid area GA.

[0152] In a planar view, multiple scale patterns LP can surround a cell region CA at regular intervals. In other words, in a planar view, multiple scale patterns LP can surround a masking element MS at regular intervals. As an example, in a planar view, the gap (also called the spacing) Wlp between adjacent scale patterns LP can range from 10 nanometers to 1000 nanometers.

[0153] Multiple ruler patterns LP can measure the positional accuracy of each pixel aperture SOP based on the center of each pixel aperture SOP, any portion of the vertices included in the pixel aperture SOP, or any portion of the edges included in the pixel aperture SOP. In embodiments, the ruler patterns LP can be positioned to point to a specific location on each pixel aperture SOP. Because the multiple ruler patterns LP include nanometer-sized gaps, the multiple ruler patterns LP can also be applied to masks MK used in the production of ultra-high resolution display panels. Since the mask MK1 according to the embodiment can automatically measure the positional accuracy of the pixel aperture SOP without a separate measuring device, the mask MK1 is easy to measure.

[0154] Multiple scale patterns LP can be separated by equal intervals Wlp not only in the first direction (X-axis direction) but also in the second direction (Y-axis direction).

[0155] The accompanying drawings show multiple scale patterns LP all having the same length Llp, but this disclosure is not limited thereto. In another embodiment, the scale patterns LP may also have different lengths Llp from each other.

[0156] Figure 10 It is along Figure 9 The cross-sectional view taken from line C1-C1'.

[0157] Reference Figure 10 According to the embodiment, the first upper inorganic layer U1 and the second upper inorganic layer U2 can be stacked in a third direction (Z-axis direction) at the portion overlapping with the cell peripheral region CRA. As described above, the first upper inorganic layer U1 can have a protrusion P1 in the portion overlapping with the grid region GA, and the second upper inorganic layer U2 can have a protrusion P2 in the portion overlapping with the grid region GA. In the portion overlapping with the grid region GA, the protrusion P2 of the second upper inorganic layer U2 can protrude more than the protrusion P1 of the first upper inorganic layer U1 in the direction toward the cell region CA. Therefore, an undercut can be formed between the protrusion P2 of the second upper inorganic layer U2 and the protrusion P1 of the first upper inorganic layer U1.

[0158] In the cross-sectional view, multiple scale patterns LP can be positioned on the second upper inorganic layer U2 in the portion overlapping with the mesh region GA. Multiple scale patterns LP can be in contact with the second upper inorganic layer U2. Multiple scale patterns LP do not need to overlap with the mask substrate MSUB in the third direction (Z-axis direction). Similarly, multiple scale patterns LP do not need to overlap with the mask diaphragm MM in the third direction (Z-axis direction). In other words, multiple scale patterns LP do not need to overlap with the cell region CA and the cell perimeter region CRA.

[0159] In the cross-sectional view, multiple ruler patterns LP can be separated from masking elements MS, and pixel openings SOP are located between the multiple ruler patterns LP and the masking elements MS.

[0160] Multiple scale patterns LP can overlap with the protrusion P2 of the second upper inorganic layer U2 in the third direction (Z-axis direction). The accompanying drawings show multiple scale patterns LP not overlapping with the protrusion P1 of the first upper inorganic layer U1, but this disclosure is not limited thereto. According to an embodiment, the multiple scale patterns LP can also be positioned to overlap with the protrusion P1 of the first upper inorganic layer U1 in the third direction (Z-axis direction).

[0161] In a cross-sectional view, multiple scale patterns LP can be separated by regular intervals Wlp. As an example, in a cross-sectional view, the gap Wlp between adjacent scale patterns LP can range from 10 nanometers to 1000 nanometers.

[0162] In some embodiments, the scale pattern LP may include inorganic insulating material or metallic material.

[0163] For example, when the scale pattern LP includes an inorganic insulating material, the scale pattern LP may include any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0164] In some embodiments, when the scale pattern LP comprises an inorganic insulating material, the height Hlp of the scale pattern LP can be in the range of 0.2 micrometers to 3 micrometers.

[0165] For example, when the scale pattern LP includes metallic materials, the scale pattern LP may include copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0166] In some embodiments, when the scale pattern LP comprises a metallic material, the height Hlp of the scale pattern LP can be in the range of 50 nanometers to 500 nanometers.

[0167] The accompanying drawings show multiple scale patterns LP with the same height Hlp, but this disclosure is not limited thereto. According to embodiments, the height Hlp of each scale pattern LP can be formed differently.

[0168] In the cross-sectional view, the scale pattern LP may include an upper surface m1, a lower surface m2, and a side surface m3. The lower surface m2 of the scale pattern LP may be a surface in contact with the second upper inorganic layer U2, the upper surface m1 of the scale pattern LP may be a surface opposite to the lower surface m2, and the side surface m3 of the scale pattern LP may be a surface connecting the upper surface m1 and the lower surface m2.

[0169] In some embodiments, in a cross-sectional view, the scale pattern LP of mask MK1 can have a cylindrical shape. That is, the upper surface m1 and the lower surface m2 of the scale pattern LP can have the same width. However, the scale pattern LP is not limited to this and can have various shapes depending on the embodiment. Details will be described later.

[0170] Figures 11 to 13 This illustrates other embodiments. Figure 10 Cross-sectional views of various shapes of the ruler pattern.

[0171] Reference Figures 11 to 13 Masks MK3, MK5, and MK7, described later, may have scale patterns LP with different shapes than those of mask MK1 described above. In the following text, the commonalities between mask MK1 and masks MK3, MK5, and MK7 will be omitted, and the differences between mask MK1 and masks MK3, MK5, and MK7 will be described later.

[0172] like Figure 11 As shown, the scale pattern LP included in mask MK3 is the same as that included in mask MK1 (see...). Figure 10 The difference in the scale pattern LP included in the mask MK3 is that the width Wm1 of the upper surface m1 of the scale pattern LP can be smaller than the width Wm2 of the lower surface m2. Furthermore, the side surface m3 of the scale pattern LP included in the mask MK3 can be an inclined surface. That is, in a cross-sectional view, the scale pattern LP included in the mask MK3 can have a trapezoidal shape. This can be due to the removal of a portion of the scale pattern LP by an etching process during the manufacturing process of the mask MK3.

[0173] Multiple scale patterns LP included in the mask MK3 can be separated by regular intervals Wlp. As an example, the gaps Wlp between multiple scale patterns LP can range from 10 nanometers to 1000 nanometers. Redundant descriptions will be omitted.

[0174] like Figure 12 As shown, the scale pattern LP included in mask MK5 is the same as that included in mask MK1 (see...). Figure 10 The difference in the scale pattern LP included in mask MK5 is that the width Wm1 of the upper surface m1 of the scale pattern LP can be greater than the width Wm2 of the lower surface m2. Furthermore, the side surface m3 of the scale pattern LP included in mask MK5 can be an inclined surface. That is, in the cross-sectional view, the scale pattern LP included in mask MK5 can have an inverted tapered shape. This can be due to a portion of the scale pattern LP being removed by an etching process during the manufacturing process of mask MK5.

[0175] Multiple scale patterns LP included in the mask MK5 can be separated by regular intervals Wlp. As an example, the gaps Wlp between multiple scale patterns LP can range from 10 nanometers to 1000 nanometers. Redundant descriptions will be omitted.

[0176] like Figure 13 As shown, the scale pattern LP included in mask MK7 is the same as that included in mask MK1 (see...). Figure 10 The difference in the scale pattern LP is that the side surface m3 includes a first side surface m31 and a second side surface m32. The first side surface m31 of the scale pattern LP can be a surface connected to the upper surface m1, and the second side surface m32 of the scale pattern LP can be a surface connected to the lower surface m2. The upper surface m1 and the lower surface m2 can be connected through the first side surface m31 and the second side surface m32.

[0177] The first side surface m31 and the second side surface m32 of the scale pattern LP included in the mask MK7 can be inclined surfaces, and the inclination angle θm3 formed by the first side surface m31 and the second side surface m32 can be an obtuse angle. This may be due to a portion of the scale pattern LP being removed by an etching process during the manufacturing process of the mask MK7. Other redundant descriptions will be omitted.

[0178] Multiple scale patterns LP included in the mask MK7 can be separated by regular intervals Wlp. As an example, the gaps Wlp between multiple scale patterns LP can range from 10 nanometers to 1000 nanometers. Redundant descriptions will be omitted.

[0179] like Figures 10 to 13 As shown, masks MK3, MK5, and MK7 can include multiple scale patterns LP in the portions overlapping with the grid region GA. The multiple scale patterns LP included in masks MK3, MK5, and MK7 can be spaced apart at nanometer-level intervals. Therefore, masks MK3, MK5, and MK7 can automatically measure the positional accuracy of the pixel opening SOP without separate measurement devices, thus facilitating measurement.

[0180] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0181] Although the present invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the present invention as defined by the appended claims.

Claims

1. A deposition mask, characterized in that, The deposition mask includes a cell region, a cell perimeter region surrounding the cell region, and a grid region positioned between the cell region and the cell perimeter region in a planar view. The deposition mask includes: A mask diaphragm is disposed in the cell region, the mask diaphragm including a mask shielding member and defining a pixel opening in the mask diaphragm; A mask frame is disposed in the peripheral region of the cell and the grid region; and Multiple ruler patterns are set in the grid area. The plurality of scale patterns are adjacent to each other in a direction parallel to the main surface of the mask frame and are spaced apart by equal intervals.

2. The deposition mask according to claim 1, characterized in that, The mask frame includes a mask base disposed in the peripheral region of the unit and an upper inorganic layer positioned on the mask base, and The upper inorganic layer includes a protrusion that protrudes towards the cell region from the side surface of the mask substrate that is positioned towards the cell region. The protrusions of the upper inorganic layer are disposed in the grid area.

3. The deposition mask according to claim 2, characterized in that, The plurality of scale patterns are positioned on the upper inorganic layer, and The plurality of scale patterns overlap with the protrusions of the upper inorganic layer in a direction perpendicular to the main surface of the mask frame.

4. The deposition mask according to claim 3, characterized in that, The height of each of the plurality of scale patterns in the direction perpendicular to the main surface of the mask frame is greater than or equal to 0.2 micrometers and less than or equal to 3.0 micrometers.

5. The deposition mask according to claim 3, characterized in that, The height of each of the plurality of scale patterns in the direction perpendicular to the main surface of the mask frame is greater than or equal to 50 nanometers and less than or equal to 500 nanometers.

6. The deposition mask according to claim 2, characterized in that, Each of the plurality of scale patterns includes a lower surface facing the upper inorganic layer, an upper surface opposite to the lower surface, and a side surface connecting the upper surface and the lower surface. Wherein, the side surface of each of the plurality of scale patterns includes a first side surface connected to the upper surface and a second side surface connected to the lower surface, and The angle of inclination formed by the first side surface and the second side surface is an obtuse angle.

7. The deposition mask according to claim 1, characterized in that, The gap between adjacent ruler patterns in the direction parallel to the main surface of the mask frame is greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.

8. The deposition mask according to claim 1, characterized in that, In the cross-sectional view, each of the plurality of scale patterns has at least one of a cylindrical shape, a trapezoidal shape, and an inverted tapering shape.

9. The deposition mask according to claim 1, characterized in that, At least one of the plurality of ruler patterns is positioned at a predetermined position pointing to the pixel opening.

10. A deposition mask, characterized in that, The deposition mask includes a cell region, a cell perimeter region surrounding the cell region, and a grid region positioned between the cell region and the cell perimeter region in a planar view. The deposition mask includes: A mask diaphragm is disposed in the cell region, the mask diaphragm defining a pixel opening in the mask diaphragm and including a mask shielding member surrounding the pixel opening; A mask frame, disposed in the peripheral region of the cell and the grid region, and defining a mask opening within the mask frame; and Multiple ruler patterns are set in the grid area. In the plan view, the plurality of scale patterns are positioned adjacent to each other and separated by equal intervals. In the planar diagram, the gap between adjacent scale patterns among the plurality of scale patterns is greater than or equal to 10 nanometers and less than or equal to 1000 nanometers.

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