Circuit for voltage reference and cell as circuit pattern

Abstract

The utility model provides a kind of circuit and unit as circuit pattern for voltage reference.The unit includes first device in example, and first device includes first multiple metal oxide semiconductor field effect transistors connected in series.The unit also includes second device, and second device includes second multiple metal oxide semiconductor field effect transistors connected in series.The second device is connected in series with the first device.The second multiple metal oxide semiconductor field effect transistors have second threshold voltage, and the second threshold voltage is higher than first threshold voltage.The unit also includes reference node, and is connected between the first laminated gate device and the second laminated gate device.

Description

Technical Field

[0001] This utility model relates to a circuit for voltage reference and a unit as a circuit pattern. Background Technology

[0002] A precision bandgap voltage reference is an electronic circuit designed to produce a stable and predictable voltage output, unaffected by temperature variations, power supply fluctuations, or time. The voltage variation produced by the reference circuit is minimal despite changes in environmental factors. Therefore, these circuits are well-suited for use in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), sensor measurements, power conditioning, medical devices, and communication equipment. Bandgap voltage references provide stable and accurate measurement voltages for these types of devices. For example, sensors use a reference voltage to compare with the generated voltage that responds to detection conditions. The accuracy of the reference voltage ensures that the sensor will produce accurate readings. Bandgap references combine voltages with positive and negative temperature coefficients (e.g., proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT)) to compensate for each other. The output voltage approximates the theoretical bandgap voltage of the semiconductor used. For example, the bandgap voltage of silicon is approximately 1.25 volts (V). Utility Model Content

[0003] The circuit pattern unit of this embodiment includes a first plurality of metal-oxide-semiconductor (MOSFETs), a second plurality of MOSFETs, and a reference node. The first plurality of MOSFETs are connected in series, with the gate of each MOSFET connected to the first node. The source / drain terminals of one of the first plurality of MOSFETs are connected to the first node, and each of the first plurality of MOSFETs has a first threshold voltage (Vt). The second plurality of MOSFETs are connected in series with the first plurality of MOSFETs, and each of the second plurality of MOSFETs has a second Vt, which is higher than the first Vt. The reference node is connected at the junction of the first plurality of MOSFETs and the second plurality of MOSFETs.

[0004] The voltage reference circuit of this embodiment includes a voltage terminal, a first current mirror, a second current mirror, and a unit. The first current mirror includes three metal-oxide-semiconductor (MOSFETs). The second current mirror is connected to the first and second MOSFETs of the first current mirror. The unit includes a first plurality of MOSFETs, a second plurality of MOSFETs, and a reference node. The first plurality of MOSFETs are connected in series, and the gate of each of the first plurality of MOSFETs is connected to the third MOSFET of the first current mirror. The source / drain terminal of one of the first plurality of MOSFETs is connected to the third MOSFET of the first current mirror. Each of the first plurality of MOSFETs has a first threshold voltage (Vt). The second plurality of MOSFETs are connected in series, and the second plurality of MOSFETs are connected in series with the first plurality of MOSFETs. Each of the second plurality of MOSFETs has a second Vt, which is higher than the first Vt. The reference node is connected at the junction of the first plurality of metal-oxide-semiconductor field-effect transistors and the second plurality of metal-oxide-semiconductor field-effect transistors.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 An exemplary apparatus including a voltage reference circuit is shown according to the disclosed embodiment.

[0007] Figure 2 An exemplary voltage reference circuit according to the disclosed embodiment is shown. The exemplary voltage reference circuit includes... Figure 1 The device's stacked gate unit.

[0008] Figure 3 The following is illustrated according to the disclosed embodiments. Figure 2 Example of a stacked gate cell.

[0009] Figure 4 The following is illustrated according to the disclosed embodiments. Figure 3 Example of a stacked gate device.

[0010] Figure 5A The following is illustrated according to the disclosed embodiments. Figure 2 Example trimming circuit of mid-layer gate cell.

[0011] Figure 5B The following is illustrated according to the disclosed embodiments. Figure 2 Another example embodiment of the trimming circuit 210.

[0012] Figure 6 The following is illustrated according to the disclosed embodiments. Figure 3 Example combination table of mid-layer gate units.

[0013] Figure 7 An example method for outputting a reference voltage according to a disclosed embodiment is shown.

[0014] Figure 8 An example method for adjusting the temperature coefficient of a reference voltage according to a disclosed embodiment is shown. Detailed Implementation

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. Throughout this disclosure, the term "cell" refers to a set of circuit patterns in a design layout used to implement a specific function of the circuit.

[0018] The embodiments disclosed herein pertain to bandgap voltage references with stacked gate configurations. Many bandgap voltage references utilize bipolar junction transistors (BJTs) due to their predictable temperature behavior, low noise, and stable performance. As semiconductor device technology has advanced, the space between contacts has become smaller. Therefore, some modern electronic designs use metal-oxide-semiconductor field-effect transistors (MOSFETs) because BJTs tend to require more space. Accordingly, using MOSFETs in complementary metal-oxide-semiconductor (CMOS) designs helps to preserve circuit space by scaling with other components in the device that also use MOSFETs. These types of MOSFET-only voltage references are used, for example, in communication devices, data converter devices, and other integrated circuits (ICs). Furthermore, MOSFET-only voltage references may utilize PTAT / CTAT cells, which utilize different threshold voltages of the transistor to eliminate temperature dependence of the voltage. In some embodiments, the stacked gate cell voltage can produce a stable voltage over a temperature range of -25°C to 125°C. However, the conventional 3σ inaccuracy of these MOSFET bandgap voltage references alone is approximately 15% to 20%.

[0019] The voltage reference with stacked gate devices described herein includes a first stacked gate device having a plurality of MOSFETs connected in series, and a second stacked gate device having a second plurality of MOSFETs. The second stacked gate device is connected in series with the first stacked gate device, meaning the transistors of the stacked gate device are connected via a common source / drain terminal. Furthermore, the gate terminal of each transistor is connected to a common node. A reference node providing a bandgap voltage reference is connected at the junction of the first and second stacked gate devices. The threshold voltage (Vt) of the second plurality of MOSFETs is higher than that of the first plurality of MOSFETs. These stacked gate devices are used to form a CTAT or PTAT cell for the voltage reference.

[0020] This design increases stability within the cell, resulting in smaller voltage variations. Furthermore, the multi-gate design improves output resistance. The multi-gate design also increases the channel length due to the use of multiple MOSFETs, thereby improving the output reference voltage. With this configuration, the voltage generated by the voltage reference is resistant to temperature fluctuations, and the output 3σ inaccuracy is reduced by 33% to 50%. Voltage regulators, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), precision measurement systems, temperature sensors, bias generators, and memory can use the multi-gate device to obtain the aforementioned benefits. Moreover, the multi-gate device design for voltage reference is compatible with 20nm (N20), 16nm (N16), 10nm (N10), N7, N5, N3, 2nm (N2), and other technology generations.

[0021] Figure 1 An exemplary device 100 including a voltage reference circuit 110 is shown. In the illustrated embodiment, device 100 includes a voltage reference circuit 110 having a stacked gate unit 112. A voltage source 114 is connected to the voltage reference circuit 110. Component 116 uses the voltage reference circuit 110 to perform a function.

[0022] In the illustrated embodiment, the voltage reference circuit 110 includes a multilayer gate unit 112. The voltage reference circuit 110 is configured to generate a bandgap voltage reference, which may be 1.25 volts. 1.25 volts is close to the bandgap voltage of silicon, which is widely used in electronic products. In some embodiments, the voltage is equal to or between 1.2 volts and 1.3 volts. In other embodiments, the voltage is a different voltage, such as the bandgap voltage of different materials. Furthermore, the generated voltage is temperature-independent. When the absolute temperature fluctuates, the voltage reference remains at a substantially the same level. Moreover, the voltage is also resistant to changes in supply power or voltage and changes in electrical load. In some embodiments, the voltage reference circuit 110 generates a voltage that is proportional to temperature, i.e., the voltage increases with increasing absolute temperature, or is complementary to temperature, i.e., the voltage decreases with increasing absolute temperature.

[0023] Component 116 uses the generated voltage reference to perform its design tasks. For example, this component is a memory module that uses the generated voltage for precise write and read operations. In some embodiments, the component is a temperature sensor. If the voltage reference is designed to increase or decrease with absolute temperature, the temperature sensor detects changes in the voltage reference to calculate the current temperature. Other temperature sensors generate voltages that vary with temperature, and the voltage generated by the temperature sensors is compared with a reference voltage from voltage reference circuit 110 to calculate the temperature. In some embodiments, component 116 is a measurement system, such as a multimeter, oscilloscope, or other laboratory equipment. The voltage generated by voltage reference circuit 110 is used to maintain accuracy and prevent drift due to temperature changes. In other embodiments, component 116 is an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC). Voltage reference circuit 110 generates a stable voltage that is used by either converter in the quantization step to achieve accurate conversion between analog and digital signals. The stable voltage reference is used by the converter for reliable and consistent conversion under different operating conditions.

[0024] Furthermore, voltage source 114 is configured to provide various voltages. For example, voltage source 114 may produce a voltage of 1.4 volts or 1.5 volts. A low-voltage bandgap reference may be configured to receive a supply voltage of less than 1 volt from voltage source 114. Other embodiments use 1 volt or 1.2 volts as the supply voltage. In other embodiments, voltage source 114 supplies voltages at different levels to voltage reference circuit 110. In some embodiments, the 3σ inaccuracy produced by voltage reference circuit 110 is between four percent and ten percent.

[0025] Figure 2 Explanation Figure 1 An example voltage reference device with a stacked gate cell 112. The voltage reference circuit 110 is a circuit including the stacked gate cell 112. The stacked gate cell includes stacked gate devices 204 and 206. A reference node (vref) 208 is connected at the junction of the stacked gate 204 and the stacked gate device 206. A temperature coefficient (TC) trimming circuit is also included in the stacked gate device 206. A current source 216 is connected to the stacked gate cell 112. The current source is generated by a MOSFET 224, which is part of a current mirror 226. The current mirror 226 also includes MOSFETs 212 and 214. Furthermore, the voltage reference circuit 110 includes a second current mirror 228, which includes transistors 218 and 220. A resistor 222 is connected to transistor 218 to bias the second current mirror 228, which also affects the bias of the first current mirror 226. Additionally, voltage terminal 230 is connected to voltage source 114.

[0026] Here, the voltage reference circuit 110 includes a multilayer gate unit 112 for outputting a stable voltage signal to the reference node 208. Furthermore, a first multilayer gate device 204 and a second multilayer gate device 206 operate together to generate a stable voltage at the reference node 208. Each of the first and second multilayer gate devices 204 includes a plurality of MOSFETs. The first plurality of MOSFETs in the first multilayer gate device 204 includes a first threshold voltage (Vt). The second multilayer gate device 206 includes a second plurality of MOSFETs having a second Vt, which is higher than the first Vt. The second multilayer gate device 206 having a second plurality of MOSFETs with a higher Vt than the first plurality of MOSFETs enables the multilayer gate unit to maintain a stable voltage at the reference node 208. The voltage calculation formula for the reference node is Vref=Vgs_high*Vt2–Vgs_low*Vt1~Vt2-Vt1, where Vgs_high is the gate-to-source voltage Vgs of the second plurality of MOSFETs in the second stacked gate device, Vt2 is the threshold voltage of each MOSFET in the second plurality of MOSFETs in the second stacked gate device, Vgs_low is the Vgs of each MOSFET in the first plurality of MOSFETs in the first stacked gate device, and Vt1 is the threshold voltage of each MOSFET in the first plurality of MOSFETs in the first stacked gate device.

[0027] Furthermore, the stacked gate design, including the first stacked gate device 204 and the second stacked gate device 206, can increase the output resistance, thereby reducing output voltage variations. In some embodiments, the MOSFETs in the first plurality of MOSFETs and the second plurality of MOSFETs are configured according to... Figure 6 The relevant tables are categorized. In some embodiments, the stacked gate unit 112 is a CTAT unit, whose generated voltage decreases with increasing temperature. This effect is balanced by the corresponding PTAT units formed by the first current mirror 226 and the second current mirror 228.

[0028] The stacked gate cell 112 also includes a TC trimming circuit 210. The TC trimming circuit is connected to the second stacked gate device 206 to modify the temperature dependence of the stacked gate cell 112. Furthermore, the TC trimming circuit 210 adjusts the temperature coefficient of the reference voltage of cell 112 by adjusting the number of effective parallel devices connected in parallel with the second stacked gate device 206. In some embodiments, these parallel devices are the same as or similar to those in the second stacked gate device 206. In some embodiments, the stacked gate cell 112 omits the TC trimming circuit and directly connects Vg in parallel to each MOSFET of the second stacked gate device 206. In some embodiments, the TC trimming circuit 210 adjusts the temperature dependence of the reference voltage at reference node 208. For example, the trimming circuit 210 may form a PTAT cell to balance the CTAT cell.

[0029] A stacked gate unit 112 is connected to a current source 216. The current source 216 includes a MOSFET 224. MOSFET 224 operates as part of a first current mirror 226 to generate the desired current. The current in the current source 216 is driven by MOSFETs 212 and 214, which together constitute an additional portion of the first current mirror 226. In the illustrated embodiment, MOSFETs 212, 214, and 224 are MOSFETs, specifically PMOS (P-channel Metal-Oxide-Semiconductor). However, other embodiments may use NMOS (N-channel Metal-Oxide-Semiconductor) or BJT to form the first current mirror 226 and the current source 216.

[0030] The first current mirror 226 is also connected to the second current mirror 228. The second current mirror 228 further drives the current generated by the current source 216. For example, the magnitude of the current generated by the current source 216 can be changed by changing the resistor 222. In some embodiments, the first current mirror 226, the second current mirror 228, and the resistor 222 work together to generate a voltage that increases with increasing temperature. In some embodiments, these components form a PTAT cell. Therefore, combining the temperature-proportional voltage characteristic generated by the PTAT cell with the inverse relationship of the CTAT cell yields a voltage that is relatively independent of absolute temperature. In some embodiments, the stacked gate cell 112 is a CTAT cell. In some embodiments, MOSFETs 212, 214, 224, 218, and 220 can be other types of transistors, such as BJTs, JFETs (Junction Field-Effect Transistors), or other types of transistors.

[0031] Figure 3 Show Figure 2Example of a multilayer gate unit 112. In the illustrated embodiment, a current source 216 is connected to the drain of the first multilayer gate unit 204 and the gates of both the first multilayer gate unit 204 and the second multilayer gate unit 206.

[0032] In the illustrated embodiment, the first stacked gate device 204 includes a first plurality of MOSFETs connected in series, with the gate of each first plurality of MOSFETs connected to a first node 232. The first node 232 is connected to a current source 216. The source / drain terminal of one of the first plurality of MOSFETs in the first stacked gate device 204 is connected to the first node 232, and the first plurality of MOSFETs have a first threshold Vt. Here, the source / drain terminal may refer to either the source or the drain, depending on the context. In some embodiments, the first node 232 is connected to a different device, such as a voltage source 114. The second stacked gate device 206 includes a second plurality of MOSFETs connected in series. The second stacked gate device 206 is connected in series with the first stacked gate device 204. The second plurality of MOSFETs have a second Vt, which is higher than the first Vt. Furthermore, the source / drain terminal of one of the second plurality of MOSFETs is connected to the source / drain terminal of one of the first plurality of MOSFETs. A reference node 208 is connected to a node where the first plurality of MOSFETs are connected to the second plurality of MOSFETs. Therefore, the reference node is connected at the junction of the first stacked gate device 204 and the second stacked gate device 206.

[0033] Figure 4 Show Figure 3 Examples of stacked gate devices 204 and 206 are shown. In the illustrated embodiments, stacked gate devices 204 and 206 each include four MOSFET transistors. Stacked gate device 204 includes MOSFETs 410, MOSFET 412, MOSFET 414, and MOSFET 416, whose gates are connected to the same node, thus forming a common gate. Similarly, the second stacked gate device 206 includes MOSFETs 418, MOSFET 420, MOSFET 422, and MOSFET 424. Furthermore, the source / drain terminals of MOSFET 410 are connected to the first node 232.

[0034] In some embodiments, the second stacked gate device 206 includes more MOSFETs than the first stacked gate device 204. In the illustrated embodiment, the stacked gate design includes multiple individual transistors connected in series. Each source / drain terminal is connected to the source / drain terminal of an adjacent transistor. In some embodiments, these connections cause the MOSFETs to form a cascode configuration. Including multiple cascade stages can produce increased output resistance. The stacked gate device 204 includes MOSFETs 212, 214, 224, and 410. MOSFET 410 operates in the saturation region. In the saturation region, the drain current is relatively independent of the drain-source voltage. MOSFETs 212, 214, and 224 operate in the linear region during use. In the linear region, the drain current is proportional to the drain-source voltage. The same or similar principles also apply to the second stacked gate device 206. In some embodiments, the first node 232 is connected to a current source 216. In other embodiments, the first node 232 is connected to a voltage source, such as voltage source 114.

[0035] In some embodiments, a stacked gate design is achieved by dividing the gate of a large transistor into "fingers". In a multi-finger transistor, the wide gate of a single transistor is divided into multiple portions called "fingers". These finger structures share the same source and drain regions, but each finger structure has its own gate and is connected in parallel with the other gates. For example, a transistor with a long substrate may have a gate that is separated into parallel finger structures. The region between each finger structure becomes the corresponding source / drain, thereby forming a series of MOSFETs in series. Furthermore, either of the stacked gate devices 204 and 206 may consist of more or fewer transistors than shown. For example, either stacked gate device may include 10 to 40 transistors. In some embodiments, the number of transistors in either stacked gate device is 33. In some embodiments, the number of transistors is 100. Furthermore, the number of transistors in stacked gate device 204 may differ from that in the second stacked gate device 206.

[0036] In the illustrated embodiment, the transistors used for both stacked-gate devices are NMOS. In other embodiments, one or more transistors in the stacked-gate device are PMOS. In some embodiments, each of MOSFETs 410 to 416 is a transistor of the same type and has the same threshold voltage (Vt). For example, MOSFETs 410 to 416 are in conjunction with... Figure 6 The related discussion combinations belong to the same category in Table 600.

[0037] Figure 5A Show Figure 2 Example trimming circuit 210 of the stacked gate unit 112. Here, the TC trimming circuit 210 includes inverters 510 and 512, which are connected to the gate of device 508. Figure 5B Another example of trimming circuit 210 is shown, but schematic diagram 514 includes trimming circuit 210 to illustrate bit inputs used to test different bit input sequences. These input sequences affect the temperature coefficient voltage level at reference node 208.

[0038] In some embodiments, the trimming circuit adjusts the temperature coefficient of the output voltage from unit 112. In some embodiments, the trimming circuit includes two or more inverters, such as inverter 510 and inverter 512. In some embodiments, two or more inverters 510, 512 are connected to the gate of a MOSFET, such as device 508, which is connected in parallel with the second stacked gate device 206. Two or more inverters 510, 512 are also connected to a first node 232. The first node 232 is connected to Vg and current source 216. In other embodiments, the TC trimming circuit 210 generates a stable voltage that is unaffected by temperature. The TC trimming circuit 210 simultaneously performs complementary temperature coefficient (CTAT) and positive temperature coefficient (PTAT) functions to balance the voltage's temperature dependence, causing the CTAT and PTAT functions to cancel each other out.

[0039] In the illustrated embodiment, trimming circuitry 210 is connected to the stacked gate assembly 206, located between the gate terminal of each transistor and the voltage Vg. In the illustrated embodiment, inverters 510 and 512 are connected to the gate of MOSFET 508. An ON bit is input to inverter 510, and inverter 510 outputs an inverted signal to inverter 512. Inverter 512 inputs a corresponding ON signal to MOSFET 508, enabling MOSFET 508. In some embodiments, the gate is a finger connected to an extended substrate, thus enabling MOSFET 418 to turn on or form. Extending the illustrated selection circuitry to each transistor of the second stacked gate assembly 206 enables TC trimming. In some embodiments, the TC trimming circuitry adds an inverter connected to the gate of each transistor, or omits one inverter. By varying the number of inverters connected to each gate of MOSFETs 418 to 424, it is possible to control which transistors are turned on based on the number of trimmed bits, thereby enabling a variable temperature coefficient of the voltage from cell 112. In some embodiments, additional parallel devices similar to MOSFET 508 include connected inverters, such as two inverters 510 and 512.

[0040] Here, device 508 is a parallel transistor of the second stacked gate device 206. In some embodiments, device 508 is a stacked gate device designed identically to the second stacked gate device 206. Furthermore, additional devices are connected in parallel with device 508 and are identical to device 508. In one embodiment, the parallel devices of trimming circuit 210 are connected in parallel. The fingers are connected to Vg via digital circuitry including inverters 510 and 512. The TC trimming circuit 210 digitally selects the devices to be activated. This selection determines the number of devices, such as device 508, connected in parallel to the second stacked gate device 206. These devices may have different characteristics, thereby allowing for adjustment of the temperature coefficient of unit 112.

[0041] In some embodiments, the devices connected in parallel (such as device 508) have different numbers of fingers. For example, the first device may be a single-finger device. Device 508 is connected in parallel with the first device and has two fingers. The resulting circuit would be the illustrated dual inverter circuit, namely inverters 510 and 512, connected to the gates of the parallel devices. In other embodiments, a third device is connected in parallel. The third device has four fingers. In some embodiments, the number of fingers of the selected parallel device corresponds to a trimming bit. For example, bits 0, 1, 2, 3, and 4 correspond to finger numbers of 1, 2, 4, 8, and 16, respectively. These input bits are used by a controller. The controller inputs the selected bit, as shown in schematic diagram 514. For example, if the trimming bit is 5, then x equals 4, and the corresponding device is selected using the trimming circuit shown. Therefore, adjusting the number of fingers of the selected parallel device (such as device 508) results in an adjustment of the temperature coefficient because the finger size is adjusted.

[0042] For example, one embodiment includes five parallel devices similar to device 508. However, each device contains a different number of fingers, and these fingers are of different sizes. Selection bits 0, 1, 2, 3, and 4 control which parallel devices are activated. Due to the variation in the number and size of the fingers, the TC trimming circuit 210 can adapt to a wide temperature range while still ensuring a stable voltage output from the voltage reference circuit 110. In one embodiment, each parallel device is identical to the second stacked gate device 206, and the TC trimming circuit 210 trims the temperature coefficient by adjusting the size of the fingers in the second stacked gate device 206, as the number and size of the fingers will vary depending on the selected parallel device. In some embodiments, the optimal parallel device or apparatus to be activated for TC trimming is determined by testing and observing the voltage as a function of temperature. Once determined, the correct bit sequence is input to the TC trimming circuit 210 to activate the selected device.

[0043] In some embodiments, selecting parallel devices with different numbers of fingers (such as device 508) increases the number of series-connected metal-oxide-semiconductor field-effect transistors (MOSFETs). Therefore, different numbers of MOSFETs in the second stacked gate device 206 can be selected by choosing parallel devices with different numbers of fingers. Other embodiments involve adjusting the size of the fingers, rather than the number, by selecting parallel devices containing MOSFETs with different finger sizes. Size adjustment can also trim the temperature coefficient.

[0044] In some embodiments, MOSFET 508 is connected to a node between reference node 208 and one of the MOSFETs of the second stacked gate device 206. For example, MOSFET 508 is connected to reference node 208 via a source / drain node and then to a node between MOSFETs 422 and 424. Since turning on MOSFET 508 adds a parallel connection to the junction of MOSFETs 422 and 424, it reduces the output resistance of the second stacked gate device 206. In some embodiments, more MOSFETs similar to MOSFET 508 are included and connected to different junctions of the MOSFETs of the second stacked gate device 206. In some embodiments, each junction of the MOSFETs of the second stacked gate device 206 includes a MOSFET connected as described above. Schematic diagram 514 indicates the number of input bits used to indicate the number of MOSFETs to be turned on. In one example, the second stacked gate device 206 includes 100 MOSFETs connected in series. Therefore, schematic diagram 514 indicates the number of bits that can be received as input. For example, the input can be represented as gate<100:0> and ON<100:0>.

[0045] Figure 6 Explanation Figure 3Example combination table of stacked gate cells. In the illustrated embodiment, combination table 600 includes combinations of M1 MOSFETs and M2 MOSFETs to develop the illustrated stacked gate cell 112. In the illustrated embodiment, M1 represents the second stacked gate device 206, and M2 represents the first stacked gate device 204. According to combination table 600, if the MOSFETs of the second stacked gate device 206 are standard threshold voltage (SVT) transistors, then the MOSFETs of the first stacked gate device 204 are one of low threshold voltage (LVT), ultra-low threshold voltage (ULVT), or very low threshold voltage (ELVT) transistors. In other embodiments, combinations of other levels of MOSFETs are used. For example, the second stacked gate device 206 is an LVT transistor, while the first stacked gate device 204 is an ULVT transistor.

[0046] Figure 7 An example method for outputting a reference voltage is illustrated. In the illustrated embodiment, method 700 includes operations 710 to 718 for providing a stable and temperature-insensitive reference voltage.

[0047] In operation 710, a current source is provided. In some embodiments, the provided current source is current source 216. Furthermore, current source 216 includes MOSFET 224 and is part of a first current mirror 226. Proceeding to operation 712, a first plurality of MOSFETs are provided in series to form a first device. The source / drain terminals of one of the first plurality of MOSFETs of the first device are connected to the current source. The first plurality of MOSFETs includes a gate connected to the current source. The first plurality of MOSFETs has a first Vt. In some embodiments, the first plurality of MOSFETs are MOSFETs 410-416. Furthermore, the first device is a first stacked gate device 204.

[0048] In operation 714, a second plurality of MOSFETs connected in series are provided to form a second device. The second device is connected in series with a first stacked gate device. The second plurality of MOSFETs have a second Vt, which is higher than the first Vt. In some embodiments, the second plurality of MOSFETs are MOSFETs 418 to 424, and the second device is a second stacked gate device 206. In some embodiments, the gates of the second plurality of MOSFETs are connected to an inverter. In other embodiments, the gates of the second plurality of MOSFETs are connected to a current source. In some embodiments, the first plurality of MOSFETs are SVT transistors, and the second plurality of MOSFETs are LVT, ULVT, or ELVT transistors.

[0049] In operation 716, a reference node is connected at the junction of the first and second stacked gate devices. In some embodiments, the reference node is reference node 208. Proceeding to operation 718, a voltage signal with reduced voltage variation is output at the reference node. In some embodiments, method 700 further includes using a trimming circuit comprising two or more inverters to adjust the temperature coefficient of a second plurality of MOSFETs. The trimming circuit is trimming circuit 210, and the two or more inverters include inverter 510 and inverter 512. In some embodiments, method 700 includes connecting the MOSFET of the trimming circuit in parallel with the second device and connecting two inverters to the gate of the MOSFET.

[0050] Figure 8 An example method for adjusting the temperature coefficient of a reference voltage according to the disclosed embodiments is described. In the illustrated embodiment, method 800 provides operations 810 to 816 for adjusting the temperature coefficient of the reference voltage.

[0051] In operation 810, a first plurality of MOSFETs having a common gate receive the input voltage. The first plurality of MOSFETs are connected in series with a second plurality of MOSFETs. In some embodiments, the first plurality of MOSFETs are MOSFETs 410 to MOSFETs 416, and the second plurality of MOSFETs are MOSFETs 418 to MOSFETs 424. In some embodiments, the input voltage is received from a first node 232 connected to a current source 216.

[0052] In operation 812, a reference voltage is output at the connection between the first plurality of MOSFETs and the second plurality of MOSFETs. In some embodiments, the reference voltage is output from reference node 208.

[0053] In operation 814, the temperature coefficient of the reference voltage is adjusted. This temperature coefficient is adjusted by connecting one or more MOSFETs in parallel with a second or more MOSFETs. In some embodiments, the one or more MOSFETs are MOSFET508.

[0054] In some embodiments, method 800 includes operation 816. In operation 816, one of the one or more MOSFETs is selected by turning on one or more inverters connected to at least one MOSFET. In some embodiments, the one or more inverters are inverters 510 and 512.

[0055] According to some examples, a cell includes a first plurality of MOSFETs connected in series, with the gate of each of the first plurality of MOSFETs connected to a first node. The source / drain terminals of one of the first plurality of MOSFETs are connected to the first node. Each of the first plurality of MOSFETs has a first threshold voltage (Vt). The cell also includes a second plurality of MOSFETs connected in series with the first plurality of MOSFETs. Each of the second plurality of MOSFETs has a second Vt, which is higher than the first Vt. The cell also includes a reference node connected at the junction of the first plurality of MOSFETs and the second plurality of MOSFETs.

[0056] According to other examples, a circuit includes a voltage terminal (VDD) 230, a first current mirror 226 comprising three MOSFETs, and a second current mirror 228 connected to a first MOSFET and a second MOSFET of the first current mirror 226. The circuit also includes a unit comprising a first plurality of MOSFETs connected in series, with each gate of the first plurality of MOSFETs connected to a third transistor of the first current mirror 226. The source / drain terminal of one of the first plurality of MOSFETs is connected to the third MOSFET of the first current mirror 226. Each of the first plurality of MOSFETs has a first threshold voltage (Vt). The unit also includes a second plurality of MOSFETs connected in series with the first plurality of MOSFETs. Each of the second plurality of MOSFETs has a second Vt, which is higher than the first Vt. The unit also includes a reference node 208 connected at the junction of the first plurality of MOSFETs and the second plurality of MOSFETs.

[0057] According to a further example, a method includes receiving an input voltage by a first plurality of MOSFETs having a common gate. The first plurality of MOSFETs are connected in series with a second plurality of MOSFETs. The method further includes outputting a reference voltage at the connection between the first plurality of MOSFETs and the second plurality of MOSFETs, and adjusting the temperature coefficient of the reference voltage by connecting one or more MOSFETs in parallel with the second plurality of MOSFETs.

[0058] The disclosed embodiment provides a unit as a circuit pattern, comprising: a first plurality of metal-oxide-semiconductor (MOSFETs) connected in series, each of the first plurality of MOSFETs having its gate connected to a first node, wherein the source / drain terminals of one of the first plurality of MOSFETs are connected to the first node, each of the first plurality of MOSFETs having a first threshold voltage (Vt); a second plurality of MOSFETs connected in series, the second plurality of MOSFETs being connected in series with the first plurality of MOSFETs, each of the second plurality of MOSFETs having a second Vt, the second Vt being higher than the first Vt; and a reference node connected at the junction of the first plurality of MOSFETs and the second plurality of MOSFETs.

[0059] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are standard threshold voltage transistors (SVTs), and the first plurality of metal-oxide-semiconductor field-effect transistors are one of low threshold voltage transistors (LVTs), ultra-low threshold voltage transistors (ULVTs), or extremely low threshold voltage transistors (ELVTs).

[0060] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are LVT transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are ULVT transistors or ELVT transistors.

[0061] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are ULVT transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are ELVT transistors.

[0062] In a related embodiment, the unit further includes a trimming circuit configured to adjust the temperature coefficient of the reference voltage at the reference node.

[0063] In a related embodiment, the trimming circuit includes two or more inverters.

[0064] In a related embodiment, the trimming circuit further includes a metal-oxide-semiconductor field-effect transistor (MOSFET) connected in parallel with the second plurality of MOSFETs, wherein two or more of the inverters are connected to the gate of the MOSFET, and wherein the two or more inverters are connected to the first node.

[0065] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors include more metal-oxide-semiconductor field-effect transistors than the first plurality of metal-oxide-semiconductor field-effect transistors.

[0066] The disclosed embodiment provides a circuit for voltage reference, including: a voltage terminal; a first current mirror including three metal-oxide-semiconductor (MOSFETs); a second current mirror connected to the first MOSFET and a second MOSFET of the first current mirror; and a unit including: a first plurality of MOSFETs connected in series, the first plurality of MOSFETs being connected to a third MOSFET of the first current mirror via a gate connected to a third MOSFET of the first current mirror, wherein the source / drain terminal of one of the first plurality of MOSFETs is connected to the third MOSFET of the first current mirror. A plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), each of the first plurality of MOSFETs having a first threshold voltage (Vt); a plurality of second plurality of MOSFETs connected in series, the second plurality of MOSFETs being connected in series with the first plurality of MOSFETs, each of the second plurality of MOSFETs having a second Vt, the second Vt being higher than the first Vt; and a reference node connected at the junction of the first plurality of MOSFETs and the second plurality of MOSFETs.

[0067] In related embodiments, the first plurality of metal-oxide-semiconductor field-effect transistors and the second plurality of metal-oxide-semiconductor field-effect transistors include ten or more metal-oxide-semiconductor field-effect transistors.

[0068] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are standard threshold voltage transistors (SVTs), and the first plurality of metal-oxide-semiconductor field-effect transistors are one of low threshold voltage transistors (LVTs), ultra-low threshold voltage transistors (ULVTs), or extremely low threshold voltage transistors (ELVTs).

[0069] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are LVT transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are ULVT transistors or ELVT transistors.

[0070] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors are ULVT transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are ELVT transistors.

[0071] In a related embodiment, the first current mirror and the second current mirror form a temperature-to-absolute (PTAT) unit.

[0072] In a related embodiment, the circuit further includes a trimming circuit that adjusts the temperature coefficient of the second stacked gate device.

[0073] In a related embodiment, the trimming circuit includes two or more inverters.

[0074] In a related embodiment, the trimming circuit further includes a metal-oxide-semiconductor field-effect transistor (MOSFET), which is connected in parallel with the second plurality of MOSFETs, wherein two or more inverters are connected to the gate of the MOSFET, and wherein the two or more inverters are connected to the first node.

[0075] In related embodiments, the second plurality of metal-oxide-semiconductor field-effect transistors include more metal-oxide-semiconductor field-effect transistors than the first plurality of metal-oxide-semiconductor field-effect transistors.

[0076] The disclosed embodiments provide a method for voltage reference, comprising: receiving an input voltage by a first plurality of metal-oxide-semiconductor (MOSFETs) having a common gate, the first plurality of MOSFETs being connected in series with a second plurality of MOSFETs, each of the first plurality of MOSFETs having a first threshold voltage (Vt); outputting a reference voltage at a connection between the first plurality of MOSFETs and the second plurality of MOSFETs, each of the second plurality of MOSFETs having a second Vt, the second Vt being higher than the first Vt; and adjusting the temperature coefficient of the reference voltage by connecting one or more MOSFETs in parallel with the second plurality of MOSFETs.

[0077] In related embodiments, the method further includes turning on one or more inverters connected to the at least one MOSFET to select at least one of the one or more MOSFETs.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A unit as a circuit pattern, characterized in that, include: A plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) are connected in series, and the gate of each of the plurality of MOSFETs is connected to a first node. The source / drain of one of the plurality of MOSFETs is connected to the first node, and each of the plurality of MOSFETs has a first threshold voltage. The second plurality of metal-oxide-semiconductor field-effect transistors are connected in series and are connected in series with the first plurality of metal-oxide-semiconductor field-effect transistors. Each of the second plurality of metal-oxide-semiconductor field-effect transistors has a second threshold voltage, which is higher than the first threshold voltage. as well as A reference node is connected at the junction of the first plurality of metal-oxide-semiconductor field-effect transistors and the second plurality of metal-oxide-semiconductor field-effect transistors.

2. The unit according to claim 1, characterized in that, The second plurality of metal-oxide-semiconductor field-effect transistors are standard threshold voltage transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are one of low threshold voltage transistors, ultra-low threshold voltage transistors, or very low threshold voltage transistors.

3. The unit according to claim 1, characterized in that, The second plurality of metal-oxide-semiconductor field-effect transistors are low threshold voltage transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are ultra-low threshold voltage transistors or extremely low threshold voltage transistors.

4. The unit according to claim 1, characterized in that, The second plurality of metal-oxide-semiconductor field-effect transistors are ultra-low threshold voltage transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are extremely low threshold voltage transistors.

5. The unit according to claim 1, characterized in that, It also includes a trimming circuit configured to adjust the temperature coefficient of the reference voltage at the reference node.

6. The unit according to claim 1, characterized in that, The trimming circuit includes two or more inverters.

7. A circuit for voltage reference, characterized in that, include: Voltage terminal; The first current mirror consists of three metal-oxide-semiconductor field-effect transistors; The second current mirror is connected to the first metal-oxide-semiconductor field-effect transistor and the second metal-oxide-semiconductor field-effect transistor of the first current mirror; Unit, including: A plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) are connected in series, and the gate of each of the plurality of MOSFETs is connected to a third transistor of the first current mirror. The source / drain of one of the plurality of MOSFETs is connected to the third MOSFET of the first current mirror. Each of the plurality of MOSFETs has a first threshold voltage. A second plurality of metal-oxide-semiconductor (MOSFETs) are connected in series, and the second plurality of MOSFETs are connected in series with the first plurality of MOSFETs. Each of the second plurality of MOSFETs has a second threshold voltage, the second threshold voltage being higher than the first threshold voltage. The reference node is connected at the junction of the first plurality of metal-oxide-semiconductor field-effect transistors and the second plurality of metal-oxide-semiconductor field-effect transistors.

8. The circuit according to claim 7, characterized in that, The first plurality of metal-oxide-semiconductor field-effect transistors and the second plurality of metal-oxide-semiconductor field-effect transistors include ten or more metal-oxide-semiconductor field-effect transistors.

9. The circuit according to claim 8, characterized in that, The second plurality of metal-oxide-semiconductor field-effect transistors are standard threshold voltage transistors, and the first plurality of metal-oxide-semiconductor field-effect transistors are one of low threshold voltage transistors, ultra-low threshold voltage transistors, or very low threshold voltage transistors.

10. The circuit according to claim 8, characterized in that, The second plurality of metal-oxide-semiconductor field-effect transistors include more metal-oxide-semiconductor field-effect transistors than the first plurality of metal-oxide-semiconductor field-effect transistors.

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