circuitry

Abstract

Various embodiments of the present utility model relate to a kind of circuit.The circuit includes the electrostatic discharge protection circuit being arranged along the main surface of substrate, also be arranged along the main surface but with the lateral interval of electrostatic discharge protection circuit internal circuit, and the coupling capacitor being operatively coupled and physically arranged between electrostatic discharge protection circuit and internal circuit.Coupling capacitor includes the first metal component in the first metallization layer formed in the multiple metallization layers arranged on the main surface, and the second metal component also formed in the first metallization layer.The number of metallization layer being arranged between the first metallization layer and the main surface in vertical direction is equal to or less than 1.

Description

Technical Field

[0001] This utility model embodiment relates to a circuit. Background Technology

[0002] This invention generally relates to integrated circuits (ICs), and more specifically to protecting integrated circuits from the risks or failures of electrostatic discharge (ESD) or plasma-induced damage (PID). Integrated circuits are widely used in a variety of applications. The reliability of these integrated circuits can be affected by a variety of factors. These factors may include, for example, ESD events and PID damage. Protection against ESD events and PID damage can be crucial for the proper operation of integrated circuits. Utility Model Content

[0003] One embodiment of this invention provides a circuit. The circuit includes an electrostatic discharge (ESD) protection circuit disposed along the main surface of a substrate. The circuit also includes an internal circuit disposed along the main surface but laterally spaced from the ESD protection circuit. The circuit further includes a coupling capacitor operatively coupled to and physically disposed between the ESD protection circuit and the internal circuit. The coupling capacitor includes a first metal component formed in a first metallization layer containing a plurality of metallization layers disposed on the main surface, and a second metal component also formed in the first metallization layer, wherein the number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than one.

[0004] Another embodiment of this utility model provides a circuit. The circuit includes an electrostatic discharge clip comprising a first charge dissipation component and a second charge dissipation component, disposed along the main surface of a substrate and operably coupled and physically disposed between a power rail and a ground rail. The circuit also includes a decoupling capacitor operably coupled and physically disposed between the power rail and the ground rail. The decoupling capacitor includes a first metal component formed in a first metallization layer comprising a plurality of metallization layers disposed on the main surface, and a second metal component also formed in the first metallization layer, wherein the number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than one.

[0005] Another aspect of this invention provides a method for manufacturing a circuit. The method includes forming an electrostatic discharge (ESD) protection circuit having a first charge dissipation component along a main surface of a substrate. The method further includes forming an internal circuit having a second charge dissipation component along the main surface and laterally spaced from the ESD protection circuit. The method also includes forming a first metallization layer with a plurality of metallization layers on the main surface of the substrate. The method further includes forming a first metal component in the first metallization layer. The method further includes forming a second metal component in the first metallization layer. The method further includes connecting the first metal component to the ESD protection circuit in the first metallization layer as a first charge dissipation component. The method further includes connecting the second metal component to the internal circuit in the first metallization layer as a second charge dissipation component. The method also includes forming one or more other first metal components stacked above and coupled to the first metal component, and respectively disposed in one or more other metallization layers of the plurality of metallization layers, wherein the first metal component and the other first metal components are collectively configured as a first metal plate of a capacitor. The method further includes forming one or more other second metal components stacked on top of and coupled to the second metal component, and also disposed in one or more other metallization layers, wherein the second metal component and the other second metal components are collectively configured as a second metal plate of a capacitor.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is an example circuit diagram illustrating a general circuit that includes both an ESD / PID protection scheme for coupling capacitors and an ESD / PID protection scheme or circuit for decoupling capacitors, according to some embodiments.

[0008] Figure 2 This illustrates, according to some embodiments, for use as... Figure 1 The diagram shows an example circuit diagram illustrating an implementation of an ESD / PID protection scheme or circuit for the coupling capacitor.

[0009] Figure 3 According to some embodiments, it is used for such Figure 2 A cross-sectional view of an implementation of an ESD / PID protection scheme or circuit for the coupling capacitor shown.

[0010] Figure 4 According to some embodiments, it is used for such Figure 3 A more detailed cross-sectional view of an implementation of the ESD / PID protection scheme or circuit for the coupling capacitor shown.

[0011] Figures 5 to 8 According to some embodiments, it is used for Figures 1 to 4 An example of an ESD protection circuit is a charge dissipation component.

[0012] Figure 9 This illustrates, according to some embodiments, for use as... Figure 1 The diagram shows an example circuit diagram illustrating an implementation of an ESD / PID protection scheme or circuit for a decoupling capacitor.

[0013] Figure 10 According to some embodiments, it is used for such Figure 9 A cross-sectional view of an implementation of an ESD / PID protection scheme or circuit for a decoupling capacitor.

[0014] Figure 11 According to some embodiments, it is used for such Figure 10 A more detailed cross-sectional view of an implementation of the ESD / PID protection scheme or circuit for the decoupling capacitor shown.

[0015] Figure 12 Manufacturing according to some embodiments Figure 2 Example flowchart of the circuit method in the example. Detailed Implementation

[0016] This utility model provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the utility model. These are, of course, merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity, and not to indicate any relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0018] The reliability of these integrated circuits (ICs) can be affected by a variety of factors. These factors can include, for example, electrostatic discharge (“ESD”) events and plasma-induced damage (“PID”) risks. Protecting ICs from ESD events and PID risks can be critical for the proper operation of ICs. ESD events can cause a brief surge of charge within an IC, potentially leading to IC failure. Because ESD events can occur in various situations, such as during manufacturing, assembly, testing, and field operation, protecting ICs from ESD events is crucial for their proper operation. PID generally refers to the adverse effects that occur when plasma interacts with materials, particularly in semiconductor manufacturing processes. Plasma is a highly ionized gas commonly used in various stages of semiconductor manufacturing for etching, deposition, and cleaning. PID can cause reliability issues affecting all process generations.

[0019] This disclosure provides various embodiments of the circuit. In some embodiments, the circuit includes an electrostatic discharge (ESD) protection circuit disposed along a main surface of a substrate, an internal circuit also disposed along the main surface but laterally spaced from the ESD protection circuit, and a coupling capacitor operatively coupled to and physically disposed between the ESD protection circuit and the internal circuit. The coupling capacitor includes a first metal component formed in a first metallization layer among a plurality of metallization layers disposed on the main surface; and a second metal component also formed in the first metallization layer. The number of metallization layers disposed in the vertical direction between the first metallization layer and the main surface is equal to or less than one.

[0020] In some embodiments, the electrostatic discharge protection circuit includes a first charge dissipation component and a second charge dissipation component. A first metal component is coupled to the first charge dissipation component, and a second metal component is coupled to the second charge dissipation component. In some embodiments, the coupling capacitor is a metal-oxide-metal (“MOM”) capacitor or a metal-insulator-metal (“MIM”) capacitor. The coupling capacitor is located between the signal output of the signal circuit and the signal input of the internal circuit for coupling them. ESD or PID charge imbalance may exist on the two metal plates of the coupling capacitor, which may lead to ESD or PID failure. In some embodiments, the two metal plates of the coupling capacitor are coupled to an ESD protection scheme or device located at the lower metallization layer or horizontally, thus creating a leakage path to release charge accumulated on the MOM or MIM metal plates of the coupling capacitor, for example, during plasma processing. In this way, the potential difference across the coupling capacitor caused by the plasma process is limited or eliminated, thereby advantageously reducing or eliminating the PID risk or failure of the coupling capacitor, and thus improving the quality of the circuit.

[0021] In other embodiments, another circuit includes an electrostatic discharge clamp and a decoupling capacitor. The electrostatic discharge clamp is operatively coupled and physically disposed between a power rail and a ground rail, and includes a first charge dissipation component and a second charge dissipation component, both disposed along the main surface of the substrate. The decoupling capacitor is operatively coupled and physically disposed between the power rail and the ground rail. The decoupling capacitor includes a first metal component formed in a first metallization layer among a plurality of metallization layers disposed on the main surface; and a second metal component also formed in the first metallization layer. In some embodiments, the first metal component is coupled to the first charge dissipation component, and the second metal component is coupled to the second charge dissipation component. The number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than one. In this way, the potential difference across the decoupling capacitor caused by the plasma process is limited or eliminated, thereby advantageously reducing or eliminating the PID risk or failure of the decoupling capacitor, and thus improving the quality of the circuit.

[0022] Figure 1 This is an example circuit diagram illustrating a general circuit 100 including an ESD / PID protection scheme (or circuit) 100A for a coupling capacitor 10 and an ESD / PID protection scheme 100B (or circuit) for a decoupling capacitor 20, according to some embodiments. In some embodiments, the coupling capacitor 10 or the decoupling capacitor 20 is a metal-oxide-metal (“MOM”) capacitor or a metal-insulator-metal (“MIM”) capacitor. Both MIM and MOM capacitors are widely used capacitor types in electronic circuits, particularly integrated circuits (ICs).

[0023] In MIM capacitors, the capacitor structure consists of a metal-insulator-metal stack. The insulating layer is typically made of a dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or a high-k dielectric. MIM capacitors are widely used in radio-frequency (RF) and analog integrated circuits due to their high capacitance density, low leakage current, and excellent high-frequency performance, and are commonly used in filters, oscillators, impedance matching circuits, and other applications. In MOM capacitors, the capacitor structure consists of a metal-oxide-metal stack. The insulating layer is particularly an oxide layer, typically silicon dioxide (SiO2) or a high-k dielectric. MOM capacitors are also used in integrated circuits, especially analog and mixed-signal circuits, and offer advantages such as high capacitance density, good stability, and compatibility with standard CMOS processes. MOM capacitors can be used in various analog circuits, such as voltage references, filters, and amplifiers. Both MIM and MOM capacitors have their advantages, and the choice can be made based on specific circuit requirements, process compatibility, and performance considerations.

[0024] like Figure 1 As shown, in some embodiments, the ESD / PID protection circuit 100A includes a coupling capacitor 10 operatively coupled to the electrostatic discharge protection circuit 30 and the internal circuit 50, and physically disposed between the electrostatic discharge protection circuit 30 and the internal circuit 50. In some embodiments, the coupling capacitor 10 is operatively coupled between the output of the signal circuit 70 and the input of the internal circuit 50. In some embodiments, the signal circuit 70 includes the electrostatic discharge protection circuit 30 (e.g., as shown in the figure). Figure 3 (As shown). In some embodiments, the electrostatic discharge protection circuit 30 includes a primary electrostatic discharge protection circuit 30A and a secondary electrostatic discharge protection circuit 30B connected in parallel. In some embodiments, the primary electrostatic discharge protection circuit 30A and the secondary electrostatic discharge protection circuit 30B each include a dissipative component (e.g., a diode) 32, or two components (e.g., a diode) connected in series. Figure 1 (as shown) or more dissipative components (e.g., diodes) 32. In some embodiments, the coupling capacitor 10 is operatively coupled to the signal circuit 70 via a resistor 35. In some embodiments, the electrostatic discharge protection circuit 30 and the internal circuitry 50 are operatively coupled and physically disposed between the power rail 40A and the ground rail 40B.

[0025] In some embodiments, in the early stages of the manufacturing process of circuit 100A, the first metal plate of coupling capacitor 10 (e.g., Figure 2 A portion of the 10A) is coupled to the electrostatic discharge protection circuit 30, and the second metal plate of the coupling capacitor 10 (e.g., Figure 2A portion of 10B in the coupling capacitor is coupled to a dissipative component of the internal circuitry 50. In this way, a leakage path for the coupling capacitor 10 is created at an earlier stage at the lower metallization layer, thereby releasing the charge accumulated on the metal plate of the coupling capacitor 10, thus limiting the potential across the coupling capacitor 10, and advantageously reducing or eliminating ESD / PID risks or failures. (See reference...) Figures 2 to 4 More details are described regarding the ESD / PID protection circuit 100A involving the coupling capacitor 10.

[0026] Also Figure 1 As shown, the ESD / PID protection circuit 100B includes a decoupling capacitor 20 operably coupled and physically disposed between the power rail 40A and the ground rail 40B, and an electrostatic discharge clip 60 also operably coupled and physically disposed between the power rail 40A and the ground rail 40B. In some embodiments, the electrostatic discharge clip 60 includes a transistor 65 (also... Figure 9 (In some embodiments, the electrostatic discharge clip 60 includes a triggering device (or an active triggering device) 80. In other embodiments, the electrostatic discharge clip 60 is coupled to the triggering device 80.)

[0027] In some embodiments, in the early stages of the manufacturing process of circuit 100B, the two metal plates of decoupling capacitor 20 ( Figure 9 At least a portion of 20A and 20B of the decoupling capacitor 20 is coupled to the electrostatic discharge clamp 60. In this way, the leakage path of the decoupling capacitor 20 is reduced at an earlier stage in the lower metallization layer (e.g., Figure 10 A device is created at M0 or M1 in the decoupling capacitor 20 to release the charge accumulated on the metal plate of the decoupling capacitor 20, for example during plasma processing, thereby limiting the potential across the decoupling capacitor 20 and thus advantageously reducing or eliminating the ESD / PID risk or failure of the decoupling capacitor 20. (Refer to...) Figures 9 to 11 More details are described regarding the ESD / PID protection circuit 100B involving decoupling capacitor 20.

[0028] Figure 2 This illustrates, according to some embodiments, for use as... Figure 1 An example circuit diagram of an embodiment of the ESD / PID protection circuit 100A of the coupling capacitor 10 shown. Figure 3 According to some embodiments, it is used for such Figure 2 A cross-sectional view of an embodiment of the ESD / PID protection circuit 100A of the coupling capacitor 10 shown. Figure 4 According to some embodiments, it is used for such Figure 3 A more detailed cross-sectional view of an embodiment of the ESD / PID protection circuit 100A of the coupling capacitor 10 shown.

[0029] like Figures 2 to 4As shown, in some embodiments, the ESD / PID protection circuit 100A includes an electrostatic discharge protection circuit 30 disposed along the main surface 90F of the substrate 90, an internal circuit 50 also disposed along the main surface 90F but laterally spaced from the electrostatic discharge protection circuit 30, and a coupling capacitor 10 operatively coupled between the electrostatic discharge protection circuit 30 and the internal circuit 50 and physically disposed between the electrostatic discharge protection circuit 30 and the internal circuit 50. The coupling capacitor 10 is a MIM or MOM capacitor and includes a first metal plate 10A coupled to the electrostatic discharge protection circuit 30, a second metal plate 10B coupled to the internal circuit 50, and a dielectric material 10C between the first metal plate 10A and the second metal plate 10B.

[0030] like Figure 3 As shown, the electrostatic discharge protection circuit 30 is disposed within a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) above the main surface 90F of the substrate 90, and includes a first dissipation component 32 disposed along the main surface 90F of the substrate 90. The internal circuit 50 is disposed within a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mx) also above the main surface 90F but laterally spaced from the electrostatic discharge protection circuit 30, and includes a second dissipation component 52 disposed along the main surface 90F of the substrate 90. In some embodiments, the first dissipation component 32 is an active ESD channel (OD), and the second dissipation component 52 is an active internal channel (OD). A coupling capacitor 10 is physically disposed between the electrostatic discharge protection circuit 30 and the internal circuit 50, and includes a first metal plate 10A, a second metal plate 10B, and a dielectric material 10C between the first metal plate 10A and the second metal plate 10B.

[0031] Also Figure 3 As shown, in some embodiments, a first metal plate 10A is coupled to a first dissipative component 32 of the electrostatic discharge protection circuit 30, and a second metal plate 10B is coupled to a second dissipative component 52 of the internal circuitry 50. Both the first dissipative component 32 and the second dissipative component 52 are located at a lower metallization layer (e.g., M1). This creates leakage paths 31 and 51 for the metal plates 10A and 10B of the coupling capacitor 10 at an earlier stage and at a lower metallization layer to release accumulated charge on the metal plates 10A and 10B. This limits the potential across the coupling capacitor 10, thereby advantageously reducing or eliminating the ESD / PID risk or failure of the coupling capacitor 10.

[0032] like Figure 4As shown, the electrostatic discharge protection circuit 30 includes a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 90F of the substrate 90, and a first dissipation component 32 disposed along the main surface 90F of the substrate 90. The internal circuit 50 includes a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) also disposed on the main surface 90F but laterally spaced from the electrostatic discharge protection circuit 30, and a second dissipation component 52 disposed along the main surface 90F of the substrate 90. In some embodiments, the first dissipation component 32 is an active ESD channel (OD), and the second dissipation component 52 is an active internal channel (OD). A coupling capacitor 10 is physically disposed between the electrostatic discharge protection circuit 30 and the internal circuit 50, and includes a first metal plate 10A, a second metal plate 10B, and a dielectric material 10C between the first metal plate 10A and the second metal plate 10B. The first metal plate 10A includes a plurality of first metal components located within a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 90F of the substrate 90, and the second metal plate 10B includes a plurality of second metal components located within a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 90F of the substrate 90. In some embodiments, the first metal components include metal wires and / or metal vias of the first metal plate 10A coupled to each other and jointly serving as coupling capacitor 10, and the second metal components include metal wires and / or metal vias of the second metal plate 10B coupled to each other and jointly serving as coupling capacitor 10.

[0033] In some embodiments, the first metal plate 10A is coupled to the first dissipation component 32 of the electrostatic discharge protection circuit 30 at the lowest metallization layer (e.g., M0) via a first metal component (e.g., M0, VD, and MD), and the second metal plate 10B is also coupled to the second dissipation component 52 (e.g., OD) of the internal circuit 50 at the lowest metallization layer (e.g., M0) via a second metal component (e.g., M0, VD, and MD). Figure 4 Not shown in the image.

[0034] In other embodiments, such as Figure 4 As shown, the first metal plate 10A is coupled to the first dissipation component 32 of the electrostatic discharge protection circuit 30 via a first metal component (e.g., M1, VIA0, M0, VD, and MD) at the lower metallization layer (e.g., M0) adjacent to the lowest metallization layer (e.g., M0). The second metal plate 10B is also coupled to the second dissipation component 52 of the internal circuit 50 via a second metal component (e.g., M1, VIA0, M0, VD, and MD) at the lower metallization layer (e.g., M1) adjacent to the lowest metallization layer (e.g., M0).

[0035] Figures 5 to 8According to some embodiments, it is used for Figures 1 to 4 Examples of ESD protection circuits include charge dissipation components (e.g., Figure 2 32). In some embodiments and as in Figure 5 As shown, the charge dissipation component can be configured as a reverse diode 532 including a cathode terminal 540 and an anode terminal 545. In some embodiments, the cathode terminal 540 is connected to a first metal plate (e.g., Figure 2 (10A in the middle), and the anode terminal 545 is connected to the ground rail (e.g., Figure 2 (40B in the example). In other embodiments, the cathode terminal 540 is connected to a power rail (e.g., ). Figure 2 (40A in the middle), and the anode terminal 545 is connected to the first metal plate (e.g., Figure 2 (10A in the middle).

[0036] In some embodiments and such Figure 6 As shown, the charge dissipation component can be configured as a series of diodes 650. The number of diodes in the series of diodes 650 can vary depending on the embodiment. In some embodiments, the number of diodes in the series of diodes 650 can depend on the amount of residual charge to be dissipated. Furthermore, in some embodiments, the series of diodes 650 can be connected such that the anode terminal 655 of the first diode in the series of diodes 650 is connected to a ground rail (e.g., Figure 2 (40B in the series), and the cathode terminal 660 of the first diode is connected to the anode terminal of the next diode in the series (e.g., the second diode). The cathode of the second diode can be connected to the anode of the third diode in the series, and so on. The cathode terminal 665 of the last diode in the series of diodes 650 can be connected to a power rail (e.g., 40B in the series), and the cathode terminal 660 of the first diode is connected to the anode terminal of the next diode in the series (e.g., the second diode). Figure 2 (40A in the middle).

[0037] In some embodiments and such Figure 7 As shown, the charge dissipation component can be configured as an NMOS diode 770. The NMOS diode 770 may include a first terminal (e.g., drain terminal) 775, a second terminal (e.g., source terminal) 780, and a third terminal (e.g., gate terminal) 785. In other embodiments, and as... Figure 8 As shown, the charge dissipation component can be configured as a PMOS diode 890. The PMOS diode 890 may include a first terminal (e.g., a drain terminal) 875, a second terminal (e.g., a source terminal) 880, and a third terminal (e.g., a gate terminal) 885.

[0038] Figure 9 This illustrates, according to some embodiments, for use as... Figure 1An example circuit diagram of an exemplary implementation of the ESD / PID protection circuit 100B for the decoupling capacitor 20 is shown. Figure 10 According to some embodiments, it is used for such Figure 9 A cross-sectional view of an embodiment of the ESD / PID protection circuit 100B of the decoupling capacitor 20 shown. Figure 11 According to some embodiments, it is used for such Figure 10 A more detailed cross-sectional view of an embodiment of the ESD / PID protection circuit 100B of the decoupling capacitor 20 shown.

[0039] like Figures 9 to 11 As shown, in some embodiments, the ESD / PID protection circuit 100B includes an electrostatic discharge clip 60 operably coupled between the power rail 40A and the ground rail 40B and physically disposed between the power rail 40A and the ground rail 40B, and a decoupling capacitor 20 operably coupled between the power rail 40A and the ground rail 40B and physically disposed between the power rail 40A and the ground rail 40B. Figure 9 As shown, in some embodiments, the ESD / PID protection circuit 100B further includes a triggering device 80 configured to detect electrostatic discharge (ESD) events or plasma-induced damage (PID) events, and configured to activate the electrostatic discharge clip 60 in response to a detected ESD or PID event. In some embodiments, the electrostatic discharge clip 60 includes a transistor 65, which includes a first terminal (e.g., source) S connected to a power rail 40A, a second terminal (e.g., drain) D connected to a ground rail 40B, and a third terminal (e.g., gate) G connected to the output of the triggering device 80.

[0040] like Figures 10 to 11 As shown, in some embodiments, the electrostatic discharge clip 60 includes a first charge dissipation component 42A and a second charge dissipation component 42B, both disposed along the main surface 95F of the substrate 95. In some embodiments, each of the first charge dissipation component 42A and the second charge dissipation component 42B includes one of a reverse diode, an NMOS diode, or a PMOS diode.

[0041] In some embodiments, such as Figure 10 As shown, the first charge dissipation component 42A includes (or is coupled to) an active region (OD) of the power rail 40A, and the second charge dissipation component 42B includes (or is coupled to) an active region (OD) of the ground rail 40B.

[0042] In other embodiments, the first charge dissipation component 42A is the active region of the electrostatic discharge clip 60 (e.g., Figure 9The source region "S" in the image, and the second charge dissipation component 42B is another active region of the electrostatic discharge clip 60 (such as the source region "S" in the image). Figure 9 The drain region "D" in the middle.

[0043] like Figure 10 As shown, the power rail (or circuit) 40A includes multiple metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 95F of the substrate 95, and the first dissipation component 42A is disposed along the main surface 95F of the substrate 95. The ground rail (or circuit) 40B also includes multiple metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 95F of the substrate 95, and the second dissipation component 42B is also disposed along the main surface 95F of the substrate 95.

[0044] In some embodiments, the first dissipative component 42A is an active ESD channel (OD) of the power supply circuit 40A, and the second dissipative component 42B is an active ESD channel (OD) of the ground circuit 40B. A decoupling capacitor 20 is physically disposed between the power supply circuit 40A and the ground circuit 40B, and includes a first metal plate 20A, a second metal plate 20B, and a dielectric material 20C between the first metal plate 20A and the second metal plate 20B.

[0045] Also Figure 10 As shown, in some embodiments, the first metal plate 20A of the decoupling capacitor 20 is coupled to the first dissipation component 42A of the power supply circuit 40A, and the second metal plate 20B of the decoupling capacitor 20 is coupled to the second dissipation component 42B of the ground circuit 40B, both at the lower metallization layer (e.g., M1) of a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn). In this way, leakage paths 41A and 41B for the metal plates 20A and 20B of the decoupling capacitor 20 are created at an earlier stage of the fabrication of the circuit 100B and at the lower metallization layer to release the charge accumulated on the metal plates 20A and 20B, thus limiting the potential across the decoupling capacitor 20, thereby advantageously reducing or eliminating the ESD / PID risk or failure of the decoupling capacitor 20.

[0046] like Figure 11As shown, the power supply circuit 40A includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn) disposed on the main surface 95F of the substrate 95, and a first dissipation component 42A disposed along the main surface 95F of the substrate 95. The ground circuit 40B includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn) also disposed on the main surface 95F but laterally spaced from the power supply circuit 40A, and a second dissipation component 42B disposed along the main surface 95F of the substrate 95. In some embodiments, the first dissipation component 42A is an active ESD channel (OD) of the power supply circuit 40A, and the second dissipation component 42B is an active ESD channel (OD) of the ground circuit 40B. A decoupling capacitor 20 is physically disposed between the power supply circuit 40A and the ground circuit 40B, and includes a first metal plate 20A, a second metal plate 20B, and a dielectric material 20C between the first metal plate 20A and the second metal plate 20B. The first metal plate 20A includes a plurality of first metal components located in a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 95F of the substrate 95, and the second metal plate 20B includes a plurality of second metal components located in a plurality of metallization layers (e.g., M0, M1, M2, ..., and Mn) disposed on the main surface 95F of the substrate 95. In some embodiments, the first metal components include metal wires and / or metal vias and together serve as the first metal plate 20A of the decoupling capacitor 20, and the second metal components include metal wires and / or metal vias and together serve as the second metal plate 20B of the decoupling capacitor 20.

[0047] In some embodiments, the first metal plate 20A of the decoupling capacitor 20 is coupled to the first dissipation component (e.g., OD) 42A of the power supply circuit 40A at the lowest metallization layer (e.g., M0) via a first metal component (e.g., M0, VD, and MD), and the second metal plate 20B of the decoupling capacitor 20 is coupled to the second dissipation component (e.g., OD) 42B of the ground circuit 40B, also at the lowest metallization layer (e.g., M0), via a second metal component (e.g., M0, VD, and MD). Figure 11 As shown in the image.

[0048] In other embodiments, such as Figure 11As shown, the first metal plate 20A of the decoupling capacitor 20 is coupled to the first dissipation component 42A of the power supply circuit 40A at the lower metallization layer (e.g., M1) adjacent to the lowest metallization layer (e.g., M0) via a first metal component (e.g., M1, VIA0, M0, VD, and MD), and the second metal plate 20B of the decoupling capacitor 20 is coupled to the second dissipation component 42B of the ground circuit 40B at the lower metallization layer (e.g., M1) adjacent to the lowest metallization layer (e.g., M0).

[0049] In this way, leakage paths 41A and 41B for the first metal plate 20A and the second metal plate 20B of the decoupling capacitor 20 are created at an earlier manufacturing stage and at a lower metallization layer to release the charge accumulated thereon, thereby limiting the potential across the decoupling capacitor 20, thereby advantageously reducing or eliminating the ESD / PID risk or failure of the decoupling capacitor 20.

[0050] Figure 12 Manufacturing according to some embodiments Figures 2 to 4 The flowchart below illustrates an example of the method for circuit 100A. It should be noted that method 1200 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 12 The operation order of method 1200 can be changed, and can be... Figure 12 Method 1200 provides additional operations before, during, and after, and some other operations can be simply described here.

[0051] like Figures 2 to 4 As shown, the circuit 100A manufactured by method 1200 may include an electrostatic discharge protection circuit 30 having a first charge dissipation component 32 disposed along the main surface 90F of the substrate 90, an internal circuit 50 having a second charge dissipation component 52 also disposed along the main surface 90 and laterally spaced from the electrostatic discharge protection circuit 30, and a coupling capacitor 10 laterally disposed between the electrostatic discharge protection circuit 30 and the internal circuit 50. In some embodiments, each of the first charge dissipation component 32 and the second charge dissipation component 52 is selected from a reverse diode, an NMOS diode, or a PMOS diode. The coupling capacitor 10 includes a first metal plate 10A and a second metal plate 10B, both of which are vertically disposed within a plurality of metallization layers (e.g., M0, M1, M2, ... Mn) above the main surface 90.

[0052] refer to Figures 2 to 4 and Figure 12Method 1200 begins with operation 1202, which forms an electrostatic discharge (ESD) protection circuit 30 having a first charge dissipation component 32 along the main surface 90F of the substrate 90.

[0053] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1204, operation 1204 forming an internal circuit 50 having a second charge dissipation component 52, the second charge dissipation component 52 being along the main surface 90F and laterally spaced from the ESD protection circuit.

[0054] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1206, in which a first metallization layer (e.g., M0 or M1) of a plurality of metallization layers (e.g., M0, M1, M2, ... Mn) is formed on the main surface 90F of the substrate 90.

[0055] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1208, in which a first metal component is formed in the first metallization layer. The first metal component is configured as part of the first metal plate 10A of the coupling capacitor 10.

[0056] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1210, in which a second metal component is formed in the first metallization layer. The second metal component is configured as part of the second metal plate 10B of the coupling capacitor 10.

[0057] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1212, in which the first metal component is connected in the first metallization layer to the first charge dissipation component 32 of the ESD protection circuit 30.

[0058] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1214, in which the second metal component is connected in the first metallization layer to the second charge dissipation component 52 of the internal circuit 50.

[0059] Next, refer to Figures 2 to 4 and Figure 12Method 1200 proceeds to operation 1216, operation 1216 forming one or more other first metal components stacked on top of the first metal component and coupled to the first metal component, and respectively disposed in one or more other metallization layers of the metallization layer, so that the first metal component and the other first metal components together constitute the first metal plate 10A of the capacitor 10.

[0060] Next, refer to Figures 2 to 4 and Figure 12 Method 1200 proceeds to operation 1218, operation 1218 forming one or more other second metal components stacked on top of and coupled to the second metal component, and also disposed in one or more other metallization layers, so that the second metal component and the other second metal components together constitute the second metal plate 10B of the capacitor 10.

[0061] In this way, Figure 3 The leakage paths 31 and 51 can also be used to release the charge accumulated on portions of the first metal plate 10A and the second metal plate 10B formed in the upper metallization layer (e.g., M2, M3, ... Mn) above the lower metallization layer (e.g., M0 or M1), thereby limiting the potential across the coupling capacitor 10 and advantageously reducing or eliminating the ESD / PID risk or failure of the coupling capacitor 10. In some embodiments, the number of metallization layers disposed in the vertical direction between the first metallization layer (e.g., M0 or M1) and the main surface 90F of the substrate 90 is equal to or less than 1.

[0062] According to some aspects of this disclosure, a circuit is disclosed. The circuit includes an electrostatic discharge (ESD) protection circuit disposed along a main surface of a substrate, an internal circuit also disposed along the main surface but laterally spaced from the ESD protection circuit, and a coupling capacitor operatively coupled to and physically disposed between the ESD protection circuit and the internal circuit. The coupling capacitor includes a first metal component formed in a first metallization layer of a plurality of metallization layers disposed on the main surface, and a second metal component also formed in the first metallization layer. The number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than one.

[0063] In some embodiments, the capacitor is disposed between the output of the signal circuit and the input of the internal circuit. In some embodiments, the electrostatic discharge protection circuit includes a first charge dissipation component; and a second charge dissipation component, wherein a first metal component is coupled to the first charge dissipation component, and wherein a second metal component is coupled to the second charge dissipation component. In some embodiments, each of the first charge dissipation components is selected from the group consisting of a reverse diode, an NMOS diode, or a PMOS diode. In some embodiments, each of the second charge dissipation components is selected from the group consisting of a reverse diode, an NMOS diode, or a PMOS diode. In some embodiments, the coupling capacitor further includes: one or more other first metal components stacked above and coupled to the first metal component, and disposed in one or more other metallization layers of a plurality of metallization layers, wherein the first metal component and the other first metal components are collectively configured as a first metal plate of the coupling capacitor; and one or more other second metal components stacked above and coupled to the second metal component, and also disposed in one or more other metallization layers, wherein the second metal component and the other second metal components are collectively configured as a second metal plate of the coupling capacitor. In some embodiments, each of the first metal component and the other first metal components includes a metal wire or a metal via. In some embodiments, each of the second metal component and other second metal components includes a metal wire or a metal through-hole.

[0064] According to some other aspects of this disclosure, another circuit is disclosed. The circuit includes an electrostatic discharge clip comprising a first charge dissipation component and a second charge dissipation component, disposed along the main surface of a substrate and operatively coupled and physically disposed between a power rail and a ground rail; and a decoupling capacitor operatively coupled and physically disposed between the power rail and the ground rail. The decoupling capacitor includes a first metal component formed in a first metallization layer of a plurality of metallization layers disposed on the main surface, and a second metal component also formed in the first metallization layer. The number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than one.

[0065] In some embodiments, a first metal component is coupled to a first charge dissipation component, and a second metal component is coupled to a second charge dissipation component. In some embodiments, the circuit further includes a triggering device configured to activate an electrostatic discharge clamp in response to an electrostatic discharge (ESD) event or a plasma-induced damage (PID) event. In some embodiments, the electrostatic discharge clamp includes a transistor having a first terminal connected to a power rail, a second terminal connected to a ground rail, and a third terminal connected to an output of the triggering device. In some embodiments, the first charge dissipation component includes one of a reverse diode, an NMOS diode, or a PMOS diode. In some embodiments, the second charge dissipation component includes one of a reverse diode, an NMOS diode, or a PMOS diode. In some embodiments, the decoupling capacitor further includes: one or more other first metal components stacked above and coupled to the first metal component, and disposed in one or more other metallization layers of a plurality of metallization layers, wherein the first metal component and the other first metal components are collectively configured as a first metal plate of the decoupling capacitor; and one or more other second metal components stacked above and coupled to the second metal component, and also disposed in one or more other metallization layers, wherein the second metal component and the other second metal components are collectively configured as a second metal plate of the decoupling capacitor. In some embodiments, each of the first metal component and other first metal components includes a metal wire or a metal through-hole. In some embodiments, each of the second metal component and other second metal components includes a metal wire or a metal through-hole.

[0066] According to further aspects of this disclosure, a method for manufacturing a circuit is disclosed. The circuit includes a coupling capacitor having a first metal plate and a second metal plate respectively disposed within a plurality of metallization layers disposed on a main surface of a substrate. The method includes: forming an electrostatic discharge protection circuit along the main surface of the substrate, wherein the electrostatic discharge protection circuit includes a first charge dissipation component; forming an internal circuit along the main surface of the substrate, wherein the internal circuit includes a second charge dissipation component; forming a first metal component in the first metallization layer of the plurality of metallization layers, configured as part of the first metal plate of the capacitor; also forming a second metal component in the first metallization layer, configured as part of the second metal plate of the capacitor; connecting the first metal component to the first charge dissipation component of the electrostatic discharge protection circuit; and connecting the second metal component to the second charge dissipation component of the internal circuit.

[0067] In some embodiments, the number of metallization layers disposed vertically between the first metallization layer and the main surface is equal to or less than 1. In some embodiments, each of the first charge dissipation component and the second charge dissipation component is selected from the group consisting of a reverse diode, an NMOS diode, or a PMOS diode.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A circuit, characterized in that, include: An electrostatic discharge protection circuit is disposed along the main surface of the substrate; The internal circuitry is also arranged along the main surface, but is laterally spaced from the electrostatic discharge protection circuitry. as well as A coupling capacitor is operatively coupled to and physically disposed between the electrostatic discharge protection circuit and the internal circuit. The coupling capacitor mentioned above includes: The first metal component is formed in a first metallization layer of a plurality of metallization layers disposed on the main surface; as well as A second metal component is also formed in the first metallization layer, wherein the number of metallization layers disposed in the vertical direction between the first metallization layer and the main surface is equal to or less than 1.

2. The circuit according to claim 1, characterized in that, The coupling capacitor is positioned between the output of the signal circuit and the input of the internal circuit.

3. The circuit according to claim 1, characterized in that, The electrostatic discharge protection circuit includes: First charge dissipation component; and Second charge dissipation component, The first metal component is coupled to the first charge dissipation component, and the second metal component is coupled to the second charge dissipation component.

4. The circuit according to claim 1, characterized in that, The coupling capacitor further includes: One or more other first metal components, stacked on top of and coupled to the first metal component, and respectively disposed in one or more other metallization layers of the plurality of metallization layers, wherein the first metal component and the other first metal components are collectively configured as the first metal plate of the coupling capacitor; and One or more other second metal components are stacked on top of and coupled to the second metal component, and are also disposed in the one or more other metallization layers, wherein the second metal component and the other second metal components are collectively configured as the second metal plate of the coupling capacitor.

5. A circuit, characterized in that, include: An electrostatic discharge clamp, including a first charge dissipation component and a second charge dissipation component, is disposed along the main surface of a substrate and is operatively coupled to and physically disposed between a power rail and a ground rail. as well as A decoupling capacitor is operatively coupled and physically disposed between the power rail and the ground rail. The decoupling capacitor mentioned above includes: The first metal component is formed in a first metallization layer of a plurality of metallization layers disposed on the main surface; as well as A second metal component is also formed in the first metallization layer, wherein the number of metallization layers disposed in the vertical direction between the first metallization layer and the main surface is equal to or less than 1.

6. The circuit according to claim 5, characterized in that, The first metal component is coupled to the first charge dissipation component, and the second metal component is coupled to the second charge dissipation component.

7. The circuit according to claim 5, characterized in that, Also includes: A triggering device is configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event or a plasma-induced damage event.

8. The circuit according to claim 7, characterized in that, The electrostatic discharge clamp includes a transistor, which has a first terminal connected to the power rail, a second terminal connected to the ground rail, and a third terminal connected to the output of the triggering device.

9. The circuit according to claim 5, characterized in that, The first charge dissipation component includes one of a reverse diode, an NMOS diode, or a PMOS diode.

10. The circuit according to claim 5, characterized in that, The second charge dissipation component includes one of a reverse diode, an NMOS diode, or a PMOS diode.

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