Low-voltage ESD limitation using high-voltage components

Abstract

ESD protection component that features the following: • a first current path (108) extending between a first circuit node (106A) and a second circuit node (106B) and containing a trigger element (110); • a second current path (112) extending between the first circuit node (106A) and the second circuit node (106B), wherein the second current path (112) contains a shunt element; • a switching element configured to trigger a current flow through the shunt element on the basis of both a state of the triggering element (110) and a state of the switching element; and • a latch-up protection circuit (702), wherein the latch-up protection circuit (702) comprises the following: a secondary switching element (706) configured for selectively coupling a second basin area (316) of the shunt element to the first circuit node (106A).

Description

[0001] An ESD pulse (ESD - Electrostatic Discharge) is a sudden and unexpected discharge of voltage and / or current that transfers energy from an external body, such as a human body, to an electronic component. ESD pulses can damage electronic components, for example, by "burning out" a transistor's gate oxide in the case of high voltage, or by "melting" an active area of ​​a component in the case of high current, resulting in a junction failure.

[0002] As will be understood in more detail below, the present disclosure relates to improved ESD protection techniques that can dissipate the power from incident ESD events more robustly into a smaller circuit footprint than conventional techniques.

[0003] US 7 872 840 B1 discloses an ESD protection circuit for an EEPROM erase pin with a snapback device for discharging high ESD currents.

[0004] US patent 2010 / 0302693A1 discloses an ESD protection circuit comprising a clamping circuit, Zener diodes, a transistor made from a DMOS, a transistor made from an IGBT, and resistors.

[0005] CN 101 916 760 A discloses a protective structure with silicon-controlled electrostatic discharge (ESD) for effectively avoiding a latch-up effect, comprising a silicon-controlled device and a control circuit, wherein the control circuit is connected to the silicon-controlled device and controls the switching on and off of the silicon-controlled device.

[0006] US 2003 / 0076636A1 discloses an ESD protection circuit comprising a first ESD detection circuit electrically connected between the I / O pad and the VSS power connector, a second ESD detection circuit electrically connected between the I / O pad and the VDD power connector, a P-STSCR comprising a first lateral SCR and a P-trigger node, and an N-STSCR comprising a second lateral SCR and an N-trigger node.

[0007] An ESD protection component according to claim 1 is provided. Further embodiments are described in the dependent claims.

[0008] In various embodiments, an ESD protection device is provided which has the following: a first current path extending between a first circuit node and a second circuit node and containing a triggering element; a second current path extending between the first circuit node and the second circuit node, wherein the second current path contains a shunting element; and a switching element configured to trigger a current flow through the shunting element based on both a state of the triggering element and a state of the switching element.

[0009] In one embodiment, the ESD protection component can have a DeMOS transistor with a gate electrode coupled to an output of the triggering element, a drain region coupled to the first circuit node, and a source region coupled to a first well of the shunt element.

[0010] In yet another configuration, the first tub can be a p-tub.

[0011] In yet another embodiment, the shunt element can include a controllable silicon rectifier.

[0012] In another embodiment, the SCR can have the following: an anode coupled to the first circuit node; a cathode coupled to the second circuit node and a trigger tap corresponding to the first well of the shunt element.

[0013] In yet another embodiment, the shunt element can incorporate an IGBT.

[0014] In yet another embodiment, the IGBT can have the following: a gate electrode coupled to an output of the triggering element; an anode coupled to the first circuit node; and a cathode coupled to the second circuit node.

[0015] In yet another embodiment, the IGBT can contain a first well with a well contact.

[0016] In yet another configuration, the first tub can be a p-tub.

[0017] In yet another embodiment, the shunt element can have the following: a first flat implantation area arranged in a second basin comprising an n-basin, wherein the first flat implantation area has a p-type conductivity and forms a first shunt connection of the shunt element; and a second flat implantation area arranged in the first basin area and spaced apart from the first flat implantation area, wherein the second flat implantation area has an n-type conductivity and wherein the second flat implantation area forms a second shunt connection of the shunt element.

[0018] In yet another embodiment, the ESD protection component may further comprise: a first STI area at the first flat implantation area; and a third flat implantation area at the first STI area, wherein the first STI area is located between the first flat implantation area and the third flat implantation area.

[0019] In yet another embodiment, the ESD protection component can further comprise the following: a gate electrode arranged above the first and second trays and a gate dielectric arranged between the gate electrode and the first tray.

[0020] In yet another embodiment, the ESD protection component can further comprise: a first STI area at the first flat implantation area; a third flat implantation area at the first STI area, wherein the first STI area is located between the first flat implantation area and the third flat implantation area; and a second STI area at the third flat implantation area and arranged below the gate electrode.

[0021] In yet another embodiment, the ESD protection component can further comprise a latch-up protection circuit, wherein the latch-up protection circuit comprises: a secondary switching element configured for selectively coupling a second basin area of ​​the shunt element to the first circuit node.

[0022] In yet another configuration, the second tub area can be an n-tub.

[0023] In yet another embodiment, the ESD protection component can further comprise the following: a level converter circuit with an input coupled to the triggering element and an output coupled to an input of the secondary switching element.

[0024] In another embodiment, a p-shaped channel of the shunt element can be coupled to the second circuit node.

[0025] In yet another embodiment, the shunt element can have a first shunt connection coupled to the first circuit node and a second shunt connection coupled to the second circuit node.

[0026] In yet another embodiment, the switching element can include a control connection coupled to an output of the triggering element, a first switching connection coupled to the first circuit node, and a second switching connection coupled to the first trough of the shunt element.

[0027] In various embodiments, an ESD protection component is provided comprising: a trigger element for detecting an ESD pulse; a switching element coupled to the trigger element; and an IGBT coupled to the trigger element with a substrate area coupled to the switching element, wherein the IGBT is configured to selectively activate or deactivate a current flow through the IGBT based on a state of the trigger element and a state of the switching element.

[0028] In one embodiment, the IGBT may further comprise: a first flat implantation area, with a first conductivity type and arranged in an n-well; a second flat implantation area, arranged in the substrate region and spaced apart from the first flat implantation area, wherein the second flat implantation area has a second conductivity type opposite to the first; a gate electrode arranged above the substrate region between the first flat implantation area and the second flat implantation area; and a gate dielectric arranged between the gate electrode and the substrate region.

[0029] In yet another embodiment, the ESD protection component may further comprise: a first STI area at the first flat implantation area; and a third flat implantation area at the first STI area, wherein the first STI area is located between the first flat implantation area and the third flat implantation area.

[0030] In another embodiment, the switching element can include a DeMOS transistor.

[0031] In various embodiments, a method for ESD protection is provided which includes: detecting an ESD pulse; supplying a trigger signal to a DeMOS device to generate a pump signal and supplying the pump signal to a substrate area of ​​an IGBT to enable current flow through the IGBT.

[0032] In one embodiment, the trigger signal and the pump signal can be applied simultaneously to enable a current flow between an anode and a cathode of the IGBT.

[0033] Exemplary embodiments of the invention are shown in the figures and are explained in more detail below. Fig. Figure 1A shows an ESD protection component with a triggering element and a switching element which collectively trigger a shunt element according to some embodiments. Fig. Figure 1B shows a cross-section of an example in which a switching element is implemented as a DeNMOS device according to some embodiments. Fig. Figures 2A to 2D show examples where a shunt element takes the form of a controllable silicon rectifier (SCR - Silicon Controlled Rectifier) ​​according to some embodiments. Fig. Figure 3A shows an example where a shunt element takes the form of an IGBT (Insulated Gate Bipolar Transistor). Fig. Sections 3B to 3C show circuit diagrams according to the example of Fig. 3A. Fig. 4A shows an example where an N+ region in an N-type tank is assigned to the IGBT of Fig. 3A is added to implement an SCR-IGBT shunt element. Fig. Sections 4B to 4C show circuit diagrams according to the example of Fig. 4A. Fig. 5A to 5B exhibit IU characteristics of conventional ESD techniques, which suffer from a low gain factor and relatively low current handling capability. Fig. Figure 5C shows IU characteristics of an ESD component according to some embodiments. Fig. Figure 6A shows an example where an N+ IGBT region is connected to a P+ IGBT region with respect to Fig. 4A is swapped. Fig. Sections 6B to 6C show circuit diagrams according to the example of Fig. 6A. Fig. Figure 7A shows an example where a latch-up protection circuit is used relative to the embodiment of Fig. 6A has been added. Fig. Sections 7B to 7C show circuit diagrams according to the example of Fig. 7A. Fig. Figure 8 shows a procedure in flowchart format according to some embodiments.

[0034] The present invention will now be described with reference to the accompanying drawing figures, in which the same reference numerals are used throughout to refer to the same elements and in which the structures and components shown are not necessarily drawn to scale.

[0035] Fig. Figure 1A shows an exemplary circuit 100, which includes an electrostatic discharge (ESD) circuit 102 and an ESD protection circuit 104, both electrically coupled to a first circuit node 106A and a second circuit node 106B. The circuit 100 can be composed of discrete components or can be an integrated circuit and includes the first circuit node 106A and the second circuit node 106B (e.g., a DC supply voltage pin and a ground pin, respectively). The ESD protection circuit 104 includes a first current path 108, which extends between the first circuit node 106A and the second circuit node 106B and includes a trip element 110 arranged thereon. A second current path 112 also extends between the first circuit node 106A and the second circuit node 106B and is parallel to the first current path 108.The second current path 112 contains a shunt element 114, such as a controllable silicon rectifier (SCR) or an IGBT, as described herein, for example. The shunt element 114 has a first shunt terminal 116 coupled to the first circuit node 106A, a second shunt terminal 118 coupled to the second circuit node 106B, and a third shunt terminal 120 coupled to a substrate region within the shunt element 114. A switching element 122 has a first switching terminal 130 coupled to the first circuit node 106A, a second switching terminal 132 coupled to the substrate region via the third shunt terminal 120, and a control terminal 134 coupled to an output of the trip element 110.

[0036] In some embodiments, such as those in which the shunt element 114 is, for example, a controllable silicon rectifier (SCR), a voltage applied to the third shunt terminal 120 determines whether current flow between the first shunt terminal 116 and the second shunt terminal 118 is enabled or disabled. For example, if the voltage applied to the substrate region in the shunt element 114 via the third shunt terminal 120 exceeds a trip voltage of the SCR or the shunt element 114, the SCR or the shunt element 114 may allow current flow between the first shunt terminal 116 and the second shunt terminal 118, thereby preventing an incident ESD pulse from reaching an electrostatically sensitive circuit 102, as shown by arrow 128.In some embodiments, such as those where the shunt element 114 is, for example, an IGBT, a voltage applied to the well area via the third shunt terminal 120 in the shunt element 114 can increase the gain and the current flow through the shunt element 114 much more than conventional components, as explained in more detail herein. This, in turn, helps to deflect an incident ESD pulse from an electrostatically sensitive circuit 102, as shown by arrow 128.

[0037] Fig. Figure 1B shows a cross-section through an exemplary DeMOS (Drain Extended Metal Oxide Semiconductor) component 150, which can be used as a switching element 122 according to some embodiments. The DeMOS component 150, which in the example of Fig. A DeMOS device of the n-type (DeNMOS) 1B comprises a source electrode 158, a drain electrode 160 (e.g., N+ regions), a body region 152 (e.g., p-well region), and a drain expansion region 154 (e.g., n-well region) arranged in a semiconductor substrate 156. Regions 162 with shallow trench insulation (STI) and a body contact region 164 (e.g., P+ region) are also formed over the drain expansion region 154 located within the semiconductor substrate 156. A conductive electrode 166 is formed over a channel region 168 located between the source electrode 158 and the drain electrode 160. The conductive electrode 166 is electrically isolated from the channel region 168 by a gate dielectric 170.

[0038] During operation, a conductive channel selectively forms in channel region 168 depending on whether the voltage between the conductive electrode 166 and the source electrode 158 is greater or less than a threshold voltage of the DeNMOS 150. If this voltage is above the threshold voltage, channel region 168 is conductive, and charge carriers can flow from the source electrode 158 through channel region 168, through the drain expansion region 154, and into the drain electrode 160. Thus, the drain expansion region 154 can, in a sense, act as a resistor to help reduce large voltages, mitigate hot carrier effects, and the like. In this way, the DeNMOS 150 facilitates Fig. 1B ensures reliable operation when included in ESD protection circuits. The following figures depict a DeMOS component, such as the one shown in Fig. The DeNMOS component 150 shown in 1B is used as a switching element (e.g., 122 in Fig. 1A). However, it is understood that in other embodiments not shown, other switching elements (e.g. MOSFETs, BJTs) may be used.

[0039] The Fig. 2A-2D show an example of an ESD protection circuit 200, in which a shunt element (e.g. 114 of Fig. 1) takes the form of a controllable silicon rectifier (SCR) 202. The SCR 202 includes a cathode 204, an anode 206, and a p-type trigger tap 208. The anode 206 is coupled to the first circuit node 106A, and the cathode 204 is coupled to the second circuit node 106B. The p-type trigger tap 208, which represents a substrate region (in this example, a trough region) in the SCR, is coupled to a source region of the DeNMOS (Drain Extended n-Type Metal Oxide Semiconductor) device 210.

[0040] In the absence of an ESD pulse 124, the triggering element 110 remains switched off and accordingly delivers a low voltage at its output 126. This low voltage, which is below a threshold voltage V THThe presence of an ESD pulse in the DeNMOS transistor 210 generates a non-conducting, high-impedance state within the DeNMOS transistor 210. Thus, as long as no ESD pulse is present, the second source electrode of the DeNMOS 210 is floating, and the SCR 202 remains in a high-impedance or "blocking" state. During this time, normal operating voltages flow to the electrostatically sensitive circuit 102 at the first circuit node 106A and the second circuit node 106B. For example, if the first circuit node 106A carries a supply voltage of 5 volts DC and the second circuit node 106B carries a supply voltage of 0 volts DC, the electrostatically sensitive circuit 102, in the absence of an ESD pulse 124, sees a bias voltage of 5 volts and operates as intended.

[0041] However, if an ESD pulse occurs at a positive ESD voltage relative to ground, the trigger element 110 detects the ESD pulse 124 and increases the voltage at its output 126 above V TH of the DeNMOS 210, which puts the DeNMOS transistor 210 into a conducting state and couples the p-tap 208 to the first circuit node 106A (e.g., the 5-volt DC supply voltage pin). Coupling the first circuit node 106A to the p-tap 208 causes the SCR 202 to conduct current. Thus, power from the incident ESD pulse 124 passes through the SCR 202 and along the low-impedance path indicated by arrow 128. In this way, the power of the ESD pulse 124 is deflected away from the electrostatically sensitive circuit 102, which has a relatively high impedance, thereby preventing damage to the electrostatically sensitive circuit 102.

[0042] The Fig. Figures 2B-2C show schematic views of exemplary SCRs 202B and 202C, such as the SCR 202. The SCR 202B contains a pair of tightly coupled bipolar junction transistors (BJTs); namely, an NPN transistor 210 and a PNP transistor 212. Fig. 2B-2C are equivalent in terms of their functionality, although the structural details of their specific layouts or cross-sections may vary depending on the manufacturing process used. Fig. Figure 2D shows an exemplary cross-sectional view of the SCR 202D, which is equivalent to the Fig. The SCR 202D can be 2A-2C. It comprises a first well region 214 with a first conductivity type (e.g., p-well) and a second well region 216 with a second conductivity type (e.g., n-well). The first and second well regions 214, 216 are formed in a semiconductor substrate 218. A first flat implantation area 220 (e.g., P+) can act as an anode 206, and a second flat implantation area 222 (e.g., N+) can act as a cathode 204. A third flat implantation area 224 (e.g., P+) acts as a contact to the first well region 214. and a fourth shallow implantation area 226 (e.g. N+) acts as a contact to the second trough area 216. The first, second and third shallow trench isolation (STI - Shallow Trench Isolation) areas 228, 230, 232 are also arranged within the semiconductor substrate 218.

[0043] It goes without saying that the doping conductivities in Fig. 2D can be "swapped". A shallow N+ implantation area and shallow P+ implantation areas can be interchanged in conjunction with n-well and p-well regions. The same applies to other cross-sectional schemes and cross-sectional configurations described herein. Furthermore, depending on the polarity of expected ESD pulses, the type of doping conductivities in Fig. 2A-2D can also be reversed. For example, in some implementations to protect against negative ESD pulses (measured with respect to ground), the direction of the SCR 202 could also be reversed, etc.

[0044] Fig. Figure 3 shows an example where, relative to Fig. 2D a gate electrode 302 has been added and a fourth flat implantation area (226 in Fig. 2D) was removed, so that the shunt element (e.g. 114 in Fig. 1) now assumes the form of an IGBT (Insulated Gate Bipolar Transistor) 300. A gate dielectric 304 electrically insulates the gate electrode 302 from a channel region 306 in the first well region 312 arranged within the semiconductor substrate 218. The first flat implantation region 308 can now act as an IGBT anode, and the second flat implantation region 310 can now act as a cathode formed in the first well region 312. A third flat implantation region 314 acts as a contact to the first well region 312, while a second well region 316 is potential-free. The first trench insulation region 228 and the third shallow trench insulation region (STI - Shallow Trench Isolation) 232 are also arranged in the substrate 218.

[0045] The Fig. 3B-3C show diagrams that are equipped with Fig. 3A match. Thus, it illustrates Fig. 3B the functional electrical connections 300B between the semiconductor regions of Fig. 3A in the IGBT 300, and Fig. 3C illustrates a corresponding circuit diagram 300C for Fig. 3B. Although the Fig. 3B-3C in terms of their functionality Fig. While 3A equivalents may differ slightly in their structural details of specific layouts or cross-sections depending on the manufacturing process used, the structural details may vary during production. Fig. 3A varies.

[0046] During the operation of the circuit of Fig. 3A applies a voltage pulse to the trigger element 110 when the ESD pulse 124 is detected. This high-voltage pulse is applied to the gate electrode 302, which forms a conductive channel in the channel region 306. This conductive channel is not sufficient on its own to allow current flow between the anode 308 and the cathode 310; however, the IGBT 300 contains a pair of BJTs. The trigger signal also causes the formation of a conductive channel in the DeNMOS 210, which in turn couples the p-tub 312 to the first circuit node 106A (e.g., the DC supply voltage). This “pumping” of the IGBT-p-well 312 activates the BJTs in the IGBT 300 and short-circuits the power of the incident ESD pulse 124 through the IGBT 300 and away from the electrostatically vulnerable circuit 102.

[0047] Fig. 4A shows an example where, relative to the example of Fig. 3A, a fourth shallow implantation area 402 (e.g., N+) has been added, which acts as a contact to the second basin area 316. An additional shallow trench isolation area (STI) 404 has also been added. The IGBT 400 of Fig. The 4A works essentially in the same way as the IGBT 300 from Fig. 3A, except that the n-tub 316 is actively biased instead of remaining potential-free, as in Fig. 3A. How the embodiment of Fig. 3A applies a high-voltage pulse to the trigger element 110 when an ESD pulse 124 is detected. This high-voltage pulse is applied to the gate electrode 302, which forms a conductive channel in the channel region 306. The trigger signal also causes a conductive channel to form in the DeNMOS (Drain-Extended n-Type Metal Oxide Semiconductor) 210, which in turn couples the p-tub 312 to the first circuit node 106A (e.g., DC supply voltage). This "pumping" of the IGBT p-tub 312 activates the BJTs and short-circuits the power of the incident ESD pulse 124 through the IGBT 300 and away from the electrostatically sensitive circuit 102.

[0048] The Fig. 4B-4C show diagrams that are equipped with Fig. 4A match. Thus, it illustrates Fig. 4B the functional electrical connections 400B between the semiconductor areas of Fig. 4A in the IGBT 400, and Fig. 4C illustrates a corresponding circuit diagram 400C for Fig. 4B. Although the Fig. 4B-4C in terms of their functionality Fig. While 4A equivalent, the structural details of their specific layouts or cross-sections may vary slightly from 4A depending on the manufacturing process used.

[0049] Compared to conventional approaches, the arrangement of Fig. 4A is advantageous because the p-cup "pumping" can significantly improve the gain of the BJTs in the IGBT and thus dissipate the power of the incident ESD pulse 124 more effectively, especially if the circuit 102 is designed to operate at low voltages (e.g., below 5 V). Fig. Figures 5A-5B show the current-voltage characteristics (IU) for conventional ESD devices, which suffer from a low gain and low current handling capability at low voltages. For example, with low-voltage limiting and gate voltages of approximately 3.5 V, the following applies: Fig. 5A-5B (see number 502) the fault current for the ESD component is in the range of approximately 0.1 mA / µm-0.2 mA / µm (see number 504). In contrast, Fig. 5C, which has the IU characteristics for an ESD circuit 300 as in Fig. As described in Figure 3A, the fault current for a gate voltage of 3.5 V (see Figure 506) is approximately 10 mA / µm (see Figure 508), representing an increase in current handling capability of approximately fiftyfold in the low-voltage context. In many applications, designing for ESD currents of 10 mA / µm leads to very area-efficient ESD device solutions, and in such applications, the footprint of the ESD devices can instead be reduced (e.g., by a factor of approximately 50). Thus, the embodiment of Fig. 4A can be implemented in several ways to provide a good balance in terms of improved current handling capability and reduced circuit footprint compared to conventional solutions.

[0050] Fig. Figure 6A shows an embodiment of an ESD protection circuit with an IGBT 600, wherein the first and second flat implantation areas 602, 604 (N+ and P+ respectively) are relative to Fig. 4A are swapped. The functionality is essentially the same as in Fig. 4A described. Fig. 6B-6C show with Fig. 6A matching diagrams. Thus, it shows Fig. 6B the functional electrical connections 600B between the semiconductor regions of Fig. 6A in IGBT 600 and Fig. 6C shows a corresponding circuit diagram 600C for Fig. 6B. Although the Fig. 6B-6C regarding their functionality Fig. 6A equivalent, the structural details of their respective layouts or cross-sections may differ during manufacturing depending on the manufacturing process used. Fig. 6A may vary slightly.

[0051] Fig. Figure 7A shows an example of an ESD protection device that includes a latch-up protection circuit 702. The latch-up protection circuit 702 includes a level shifter 704 and a DePMOS (drain-extended p-type metal oxide semiconductor) transistor 706 (which can also be referred to as a secondary switching element). The level shifter 704 has an input terminal coupled to an output of the trigger element 110 and an output coupled to an input terminal of the DePMOS 706. The DePMOS 706 has a source electrode coupled to the first circuit node 106A and a drain electrode coupled to the N+ region 602. For illustrative purposes, the embodiment of Fig. 7A with regard to Fig. The IGBT 600 described in section 6A is shown, although other IGBT configurations could also be used.

[0052] During operation, the level shifter converts an input signal with a first voltage range (e.g., 0 V logic low and 1.2 V logic high) to a second, higher voltage range (e.g., 3.8 V logic low and 5.0 V logic high). This is used to meet reliability constraints, such as when the gate-source voltage should not exceed 1.2 V (abs). The DePMOS 706 is configured to selectively couple a second IGBT well 316 to the first circuit node 106A based on whether a voltage level at the output of the level shifter circuit 704 has a predetermined relationship with a voltage threshold of the DePMOS 706. For example, in the absence of an ESD pulse at its output, the level shifter 704 provides a low voltage, which turns on the DePMOS 706. This couples the n-tub 316 to the first circuit node 106A (e.g. a DC supply voltage) to limit the probability of a latch-up.In contrast, when an ESD pulse 124 occurs, the trigger element 110 increases the voltage at its output, and the level shifter 704 increases its output voltage accordingly. This switches off the DePMOS 706, so that the IGBT 700 acts like a controllable silicon rectifier (SCR) to effectively divert the energy of the ESD pulse 124 away from the electrostatically sensitive circuit.

[0053] The Fig. 7B-7C show with Fig. 7A matching diagrams. This shows Fig. 7B the functional electrical connections 600B between the semiconductor regions of Fig. 7A in the IGBT 700, and Fig. 7C shows a corresponding circuit diagram 600C for Fig. 7B. Although the Fig. 7B-7C in terms of their functionality Fig. 7A equivalent, the structural details of their respective layouts or cross-sections may differ during manufacturing depending on the manufacturing process used. Fig. 7A may vary slightly. Even though the latch-up protection circuit 702 is used in the context of Fig. As shown in Figures 7A-7C, it is understood that the latch-up protection circuit can be used in combination with any of the other embodiments described or illustrated herein and is not limited to Fig. 7A-7C is limited.

[0054] Fig. Figure 8 shows a method for ESD (Electrostatic Discharge) protection using an IGBT device according to some embodiments.

[0055] In the 802, a trigger element such as an RC trigger element detects an ESD pulse that hits an electrostatically sensitive circuit.

[0056] In the 804, a trigger element supplies a trigger signal to a gate terminal of the IGBT and to a gate terminal of a DeNMOS pump transistor (Drain Extended n-Type Metal Oxide Semiconductor). If, for example, an ESD pulse is detected, the trigger signal voltage can be increased accordingly. Conversely, if no ESD pulse is detected, the trigger signal voltage can remain constant (e.g., low).

[0057] In the 806, the DeNMOS pump delivers a pump signal, based on the trigger signal, to a basin area of ​​the IGBT. This pump signal can allow current to flow between the anode and cathode of the IGBT, thereby diverting power from the ESD pulse away from the electrostatically sensitive circuit. In many cases, the trigger signal and the pump signal can be delivered simultaneously.

[0058] It is understood that some embodiments relate to an ESD protection device for protecting a circuit from an ESD event. The circuit is electrically connected to a first and a second circuit node. The ESD protection device includes a first current path extending between the first and second circuit nodes and containing a trip element arranged thereon. A second current path extends between the first and second circuit nodes and runs parallel to the first current path. The second current path includes a shunt element with a first shunt terminal coupled to the first circuit node, a second shunt terminal coupled to the second circuit node, and a first sump.A switching element contains a control terminal coupled to an output of the triggering element, a first switching terminal coupled to the first circuit node, and a second switching terminal coupled to the first basin area.

[0059] Some embodiments relate to an ESD protection device. The ESD protection device includes a trigger element for detecting an ESD pulse and a switching element. The switching element comprises a first switching terminal, a second switching terminal, and a control terminal. The control terminal is coupled to an output of the trigger element and controls the current flow between the first and second switching terminals. The ESD protection device also includes an IGBT having a gate electrode coupled to an output of the trigger element and a first well region coupled to the second switching terminal.

[0060] Several further embodiments relate to a method for ESD protection using an IGBT. In this method, an ESD pulse striking an electrostatically sensitive circuit is detected. A trigger signal is selectively activated based on the detection of the ESD pulse and supplied to a gate terminal of the IGBT. A pump signal, based on the trigger signal, is supplied to a well region of the IGBT to allow current flow between an anode and cathode of the IGBT, thereby diverting power from the ESD pulse away from the electrostatically sensitive circuit.

[0061] With particular regard to the various functions performed by the components or structures (assemblies, components, circuits, systems, etc.) described above, the terms used to describe such components (including reference to a “means”), unless otherwise specified, shall correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention shown herein.While a particular feature of the invention may have been disclosed with respect to only one of several implementations, such a feature may also be combined with one or more other features of the other implementations, as may be desirable and advantageous for any given or particular application. Furthermore, to the extent that the terms "containing," "includes," "having," "featuring," "with," or variants thereof are used either in the detailed description or in the claims, such terms shall be inclusive in a manner similar to the term "comprising."

Claims

[1] ESD protection component comprising the following: • a first current path (108) extending between a first circuit node (106A) and a second circuit node (106B) and containing a trigger element (110); • a second current path (112) extending between the first circuit node (106A) and the second circuit node (106B), wherein the second current path (112) contains a shunt element; • a switching element configured to trigger a current flow through the shunt element on the basis of both a state of the triggering element (110) and a state of the switching element; and • a latch-up protection circuit (702), wherein the latch-up protection circuit (702) comprises the following: a secondary switching element (706) configured for selectively coupling a second basin area (316) of the shunt element to the first circuit node (106A). [2] ESD protective component according to claim 1, wherein the second tray area (316) is an n-tray. [3] ESD protection component according to claim 1 or 2, further comprising: a level converter circuit (704) with an input coupled to the triggering element and an output coupled to an input of the secondary switching element. [4] ESD protection element according to one of claims 1 to 3, wherein a p-tub (312) of the shunt element is coupled to the second circuit node (106B). [5] ESD protection element according to one of claims 1 to 4, wherein the shunt element has a first shunt connection coupled to the first circuit node (106A) and a second shunt connection coupled to the second circuit node (106B). [6] ESD protection component according to one of claims 1 to 5, wherein the switching element comprises a control terminal coupled to an output of the triggering element (110), a first switching terminal coupled to the first circuit node and a second switching terminal coupled to the first well of the shunt element.

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