A device for reinforcing beidou time
By using a multi-dimensional feature analysis device with components such as BeiDou antennas and FPGAs, the time synchronization error problem of the BeiDou navigation system under non-sensory deception signals was solved, realizing fast and accurate deception signal identification, reducing the false judgment rate and resource requirements, and expanding application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YANTAI CHIJIU CLOCK WATCH
- Filing Date
- 2025-06-30
- Publication Date
- 2026-06-16
AI Technical Summary
The existing BeiDou navigation system is difficult to accurately identify under the attack of spoofing signals without being noticed, which leads to the accumulation of time synchronization errors. Moreover, the existing technology is highly complex and has a high misjudgment rate, making it unable to effectively identify spoofing signals.
The device, composed of components such as Beidou antenna, receiver, microcontroller, and FPGA, performs multi-dimensional feature analysis through multipliers, accumulators, and comparators. By combining position difference, temperature, and crystal oscillator operating time, it can quickly distinguish between real and deceptive signals, reducing detection difficulty and false positive rate.
It has improved the anti-spoofing capability of the BeiDou Navigation Satellite System, reduced the false alarm rate and resource requirements, expanded application scenarios, improved the real-time performance of the system, and controlled costs.
Smart Images
Figure CN224366201U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a device for strengthening the BeiDou time, belonging to the technical field of signal processing equipment for satellite navigation. Background Technology
[0002] With the rapid development of the BeiDou Navigation Satellite System, navigation, positioning, and timing technologies have become critical infrastructure. However, the security of the BeiDou Navigation Satellite System faces numerous challenges under various deception and interference environments, especially against imperceptible spoofing attacks. These imperceptible spoofing signals gradually guide the receiver clock to accumulate deviations from the true time through subtle offsets. While difficult to detect in the short term, long-term accumulation can lead to serious time synchronization errors. For systems requiring high-precision time synchronization, such as satellite communications and UAV navigation, even microsecond-level or nanosecond-level time offsets can have severe consequences.
[0003] Currently, the following solutions exist for anti-spoofing technology against BeiDou:
[0004] 1. While time hardening technology employs multiple signals selected via radio frequency (RF) front-ends, this method of signal acquisition is complex and results in weak signal strength. The RF power divider outputs the signal to different signal processing modules, further weakening the already weak satellite signal. This can unnecessarily impact the reception and processing of normal signals in the absence of interference. Furthermore, with advancements in spoofing techniques, this technology cannot effectively cover potential interference and deception.
[0005] 2. People use single differences in signal characteristics to identify spoofing signals, such as carrier-to-noise ratio or signal spectrum. This method is simple to process, but as spoofing techniques develop and the degree to which they simulate real signal characteristics increases, it often fails to identify spoofing signals.
[0006] 3. People use methods such as threshold detection to strengthen the BeiDou time, and statistical characteristics such as signal strength, correlation, and multi-peak detection to detect deception. However, imperceptible deception gradually guides the receiver clock to deviate from the true time through subtle offsets, which can submerge normal signals in the deceptive signals, making threshold detection methods ineffective.
[0007] 4. To address this, many researchers utilize complex intelligent classification algorithms, such as SVM and LSTM, trained on large-scale data to improve the ability to identify deceptive signals. While the detection results are good, the computational complexity is high, requiring significant computing resources. Utility Model Content
[0008] The purpose of this invention is to address the shortcomings of the existing technology and provide a BeiDou time hardening device. This device abandons the conventional hardening technology at the radio frequency end, improves detection performance and reduces the false judgment rate, overcomes the technical challenge of identifying non-sensory deception signals, enhances the real-time performance of the system, effectively controls costs, and expands application scenarios.
[0009] The present invention relates to a BeiDou time reinforcement device, which is characterized by including:
[0010] Beidou antenna, Beidou receiver, first microcontroller, second microcontroller, Flash memory, ARM processor, FPGA, whole-second delay circuit, analog switch, output circuit, crystal oscillator assembly, crystal oscillator working time memory, ground-based augmentation system;
[0011] The Beidou antenna's output is connected to the Beidou receiver. The Beidou receiver's output is connected to the first microcontroller, the whole-second delay circuit, and the second microcontroller. The first microcontroller's input is connected to the ground-based augmentation system, and its output is connected to the Flash memory. The second microcontroller's input is connected to the Flash memory, and its output is connected to the FPGA. The whole-second delay circuit's output is connected to an analog switch. The analog switch's output is connected to the output circuit. The FPGA's input is connected to the crystal oscillator assembly and the crystal oscillator's operating time memory. The ARM processor communicates with the FPGA and the crystal oscillator's operating time memory. The FPGA's output is connected to the analog switch.
[0012] The FPGA includes an input / output block, a data preprocessing module, a multiplier MUL, an accumulator ACC, a comparator, and a communication interface, all connected in sequence at their output terminals.
[0013] The beneficial effects of this utility model are as follows:
[0014] (1) By multiplying and accumulating operations and comparing thresholds, the detection difficulty is reduced.
[0015] This invention utilizes a multiplier to process multiple sets of signal data simultaneously; an accumulator to balance detection sensitivity and latency; and a threshold comparison-based real-time decision-making detection device, suitable for low-complexity, low-latency embedded real-time detection scenarios.
[0016] (2) Multidimensional feature joint analysis to enhance anti-deception ability
[0017] The device of this invention uses signal characteristics of position difference, temperature, and working time. Through a Beidou receiver, crystal oscillator assembly, crystal working time memory, and FPGA, the three-dimensional data obtained by these hardware components are analyzed. This makes up for the limitations of relying on a single difference in signal characteristics, accurately captures the subtle features of deception signals, quickly distinguishes between real signals and deception signals, and effectively solves the problem of identifying non-perceptible deception signals.
[0018] (3) Improve detection performance and reduce false positive rate
[0019] This invention utilizes an FPGA for comprehensive judgment, leveraging the high-speed parallel processing capabilities of the FPGA through multipliers, accumulators, and comparators. Compared to traditional threshold detection methods, this invention offers higher sensitivity and accuracy, improving detection performance and reducing false positive and false negative rates.
[0020] (4) Reduced resource demand
[0021] The device of this invention utilizes FPGA to further improve the execution efficiency of detection, thereby achieving efficient and real-time deception detection.
[0022] (5) Reduced costs and expanded application scenarios
[0023] Because the device of this invention requires a smaller FPGA platform, it reduces costs and expands application scenarios. Attached Figure Description
[0024] Figure 1 : A structural block diagram of a BeiDou time reinforcement device according to this utility model;
[0025] Figure 2 Schematic diagram of FPGA. Detailed Implementation
[0026] The following detailed description of the present invention is provided with reference to the accompanying drawings.
[0027] This embodiment provides a BeiDou time hardening device, see attached diagram. Figure 1-2 The system includes a Beidou antenna 1, a Beidou receiver 2, a first microcontroller 3, a second microcontroller 4, a Flash memory 5, an ARM processor 6, an FPGA 7, an integer second delay circuit 8, an analog switch 9, an output circuit 10, a crystal oscillator assembly 11, a crystal oscillator operating time memory 12, and a ground-based augmentation system 13. The output of the Beidou antenna 1 is connected to the Beidou receiver 2. The output of the Beidou receiver 2 is connected to the first microcontroller 3, the integer second delay circuit 8, and the second microcontroller 4. The input of the first microcontroller 3 is connected to the ground-based augmentation system 13, and its output is connected to the Flash memory 5. The input of the second microcontroller 4 is connected to the Flash memory 5, and its output is connected to the FPGA 7. The output of the integer second delay circuit 8 is connected to the analog switch 9. The output of the analog switch 9 is connected to the output circuit 10. The input of the FPGA 7 is connected to the crystal oscillator assembly 11 and the crystal oscillator operating time memory 12. The ARM processor 6 communicates with the FPGA 7 and the crystal oscillator operating time memory 12. The output of the FPGA 7 is connected to the analog switch 9.
[0028] FPGA7 includes an input / output block 14, a data preprocessing module 15, a multiplier MUL 16, an accumulator ACC 17, a comparator 18, and a communication interface 19, all connected in sequence at their output terminals.
[0029] Beidou antenna 1 is used to receive Beidou signals; Beidou receiver 2 is used to calculate the position and time of the received Beidou signals, which include real satellite signals as well as spoofing or interference signals; ground-based augmentation system 13 is used to receive Beidou ground-based augmentation signals;
[0030] The first microcontroller 3 is used to calculate and accurately calibrate the antenna position and write it into the Flash memory;
[0031] The second microcontroller 4 is used to calculate the difference between the actual position and the position received by Beidou, and obtain the position difference;
[0032] Flash memory 5 is used to store precise antenna position information;
[0033] ARM processor 6 is used for:
[0034] 1. Save the cumulative crystal oscillator operating time.
[0035] 2. If the device loses power, the ARM processor records and saves the working time of the crystal oscillator at that time. After power is restored, the ARM processor module transfers the working time data saved before the power failure to the crystal oscillator working time memory, so that it continues to accumulate, ensuring that the recording of the working time is accurate and uninterrupted.
[0036] FPGA7 uses the multiply-accumulate-add (MAC) operation as its core computing unit for:
[0037] 1. Receive the position difference from the second microcontroller 4.
[0038] 2. Receive the temperature from the crystal oscillator assembly 11 and the accumulated operating time from the crystal oscillator operating time memory 12.
[0039] 3. Perform signal threshold comparison calculations to distinguish between normal signals and deceptive signals;
[0040] The whole-second delay circuit is implemented using FPGA7 to delay the received Beidou PPS by 1 second to compensate for the delay in the inference calculation process of FPGA7 and ensure that the output PPS signal is synchronized with the actual PPS.
[0041] Analog switch 9 is used to receive the time / PPS from the whole-second delay circuit and the spoofing status detection result (normal / spoofing) from the FPGA:
[0042] 1. If a non-spoofing signal is detected, the receiver processes it through a full-second delay circuit and outputs the time / PPS signal.
[0043] 2. If a spoofing signal is detected, an alarm signal will be output to alert downstream devices.
[0044] Output circuit 10: The delayed PPS and time / alarm signals are transmitted through this module;
[0045] Crystal oscillator assembly 11 is used to provide an oscillation source, and the built-in temperature sensor is used to provide the ambient temperature of the crystal oscillator to the FPGA;
[0046] The crystal oscillator operating time memory 12 is used to accumulate the operating time of the crystal oscillator. Before power failure, the operating time data is transferred to the ARM processor for storage.
[0047] The FPGA7 uses multiply-accumulate-add (MAC) operations as its core hardware computing unit and performs signal detection (normal / spoofing) through threshold comparison. The process is as follows:
[0048] The input / output block is used to receive raw data from external inputs, such as position difference ΔP, temperature T, and operating time t.
[0049] Data preprocessing uses dual-port RAM for data caching, normalization, and noise reduction.
[0050] The multiplier (MUL) is configured with three DSP48E2 slices to perform parallel multiplication, used to calculate ΔP×W1, T×W2, and t×W. 3。
[0051] Among them, the weights W1, W2, and W3 are predefined values;
[0052] The accumulator (ACC) uses an adder tree for the final output:
[0053] MAC out =Σ(ΔP×W1+ T×W2+ t×W3) + bias
[0054] Here, the bias is a predefined value;
[0055] Comparator for MAC out Comparison with threshold ω: If MAC out If -ω> 0, output 1 (normal signal); otherwise, output 0 (deceptive signal).
[0056] The communication interface is used to output the judgment result (0 / 1) to analog switch 9.
[0057] This invention abandons the conventional radio frequency hardening technology, improves detection performance and reduces the false judgment rate, overcomes the technical problem of non-intrusive deception signal recognition, enhances the real-time performance of the system, effectively controls costs, and expands application scenarios.
Claims
1. A device for hardening BeiDou time, characterized in that... include: The system comprises a BeiDou antenna, a BeiDou receiver, a first microcontroller, a second microcontroller, a Flash memory, an ARM processor, an FPGA, an integer-second delay circuit, an analog switch, an output circuit, a crystal oscillator assembly, a crystal oscillator operating time memory, and a ground-based augmentation system. The output of the BeiDou antenna is connected to the BeiDou receiver. The output of the BeiDou receiver is connected to the first microcontroller, the integer-second delay circuit, and the second microcontroller. The input of the first microcontroller is connected to the ground-based augmentation system, and its output is connected to the Flash memory. The input of the second microcontroller is connected to the Flash memory, and its output is connected to the FPGA. The output of the integer-second delay circuit is connected to the analog switch. The output of the analog switch is connected to the output circuit. The input of the FPGA is connected to the crystal oscillator assembly and the crystal oscillator operating time memory. The ARM processor communicates with the FPGA and the crystal oscillator operating time memory. The output of the FPGA is connected to the analog switch.
2. The device for strengthening BeiDou time according to claim 1, characterized in that... The FPGA includes an input / output block, a data preprocessing module, a multiplier MUL, an accumulator ACC, a comparator, and a communication interface, all connected in sequence at their output terminals.