Detection and protection circuit for a display panel
By combining a timing controller, level shifter, clock counter, and power manager, the problem of abnormal gate voltage caused by the lack of blanking area signal in the LCD panel under variable refresh rate mode was solved, realizing automatic detection and real-time protection, and improving production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SDP GLOBAL (CHINA) CO LTD
- Filing Date
- 2025-06-10
- Publication Date
- 2026-06-16
AI Technical Summary
In the existing technology, the GOA circuit of the liquid crystal display panel lacks an automatic detection mechanism in variable refresh rate mode, which leads to the absence of blanking area signal and causes abnormal gate voltage, resulting in display defects such as image retention or flickering. Moreover, relying on manual oscilloscope detection is inefficient.
By employing a combination of timing controller, level shifter, clock counter, and power manager, the system automatically detects the integrity of the global clock signal by acquiring the number of global clock signal cycles in real time and comparing it with a preset number of cycles. It also controls the working state of the power manager to prevent abnormal gate voltage and replaces manual oscilloscope testing.
It enables automatic detection of global clock signal integrity, reduces gate voltage anomalies caused by missing blanking region signals, improves debugging and production efficiency, and simplifies the testing process.
Smart Images
Figure CN224366532U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a detection and protection circuit for a display panel. Background Technology
[0002] The GOA (Gate on Array) circuit of a liquid crystal display panel drives the gate line refresh via the GCK (Gate Clock) signal. However, different designs have different requirements for the GCK output in the blanking area (i.e., the non-effective image period during image display): some designs need to stop the output to save power, while others need to output continuously to maintain the gate voltage. Existing technology relies on the manual configuration of the TCON (timing controller) chip, selecting whether to output the GCK signal in the blanking area through registers.
[0003] However, the existing methods described above have significant limitations: if the TCON is misconfigured (e.g., the Blanking area should output but doesn't), there may be no issues in standard refresh rate mode, but in variable refresh rate (VRR) mode, an extended Blanking area may lead to insufficient gate voltage, causing ghosting or flickering horizontal lines on the display panel. Furthermore, due to the lack of an automatic detection mechanism for GCK output, engineers must manually verify the signal waveform using an oscilloscope, a cumbersome process that makes real-time monitoring difficult and severely impacts debugging and production efficiency. Utility Model Content
[0004] In view of the above, it is necessary to provide a detection and protection circuit for a display panel that can automatically detect the integrity of the global clock signal, reduce gate voltage abnormalities caused by missing blanking area signals, and replace manual oscilloscope testing to improve debugging efficiency.
[0005] This application provides a detection and protection circuit for a display panel, including a timing controller, a level shifter, a clock counter, and a power manager. The first output terminal of the timing controller is connected to the input terminal of the level shifter, the input terminal of the clock counter is connected to at least one output terminal of the level shifter, the output terminal of the clock counter is connected to the input terminal of the timing controller, and the second output terminal of the timing controller is connected to the input terminal of the power manager. The clock counter is used to acquire the number of cycles of the global clock signal output from at least one output terminal of the level shifter and output the number of cycles to the timing controller. The timing controller is used to control the working state of the power manager according to the comparison result of the number of cycles and a preset number of cycles, wherein the preset number of cycles is equal to the sum of the number of cycles required for the global clock signal to perform line scanning drive in the effective display area and blanking area of the display panel.
[0006] In the detection and protection circuit of the display panel of this application, the number of global clock signal cycles output by the level converter is obtained in real time by a clock counter and fed back to the timing controller. The timing controller compares this number of cycles with the preset number of cycles (the total number of cycles required for the effective display area + blanking area) and controls the working state of the power manager according to the result. This can automatically detect the integrity of the global clock signal (whether it covers the complete row scan cycle), reduce the gate voltage abnormality caused by the missing blanking area signal (such as ghosting / flickering in VRR mode), and replace manual oscilloscope detection and improve debugging efficiency.
[0007] In some embodiments, the timing controller includes a control module for controlling the operating state of the power manager by adjusting the voltage of the input / output interface of the timing controller.
[0008] In some embodiments, the power manager is used for power management of the display panel. The operating state of the power manager includes outputting power voltage and stopping outputting power voltage. If the number of cycles is greater than or equal to a preset number of cycles, the operating state of the power manager is controlled by the timing controller to output power voltage. If the number of cycles is less than the preset number of cycles, the operating state of the power manager is controlled by the timing controller to stop outputting power voltage.
[0009] In some embodiments, multiple outputs of the level converter are connected to a gate driver disposed on the display panel.
[0010] In some embodiments, multiple outputs of the level converter are connected to multiple inputs of the timing controller, and multiple outputs of the timing controller are connected to a gate driver disposed on the display panel.
[0011] In some embodiments, the timing controller outputs a gate enable signal and a gate shift signal to a level converter via a first output terminal. The level converter is used to output a global clock signal based on the gate enable signal and the gate shift signal.
[0012] In some embodiments, the level converter has 8 output terminals for outputting a global clock signal, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 lines, the blanking area of the display panel is set to 90 lines, and the preset number of cycles is equal to 282.
[0013] In some embodiments, the level converter has 8 output terminals for outputting global clock signals, the timing controller has 8 input terminals for receiving global clock signals and 8 output terminals for outputting global clock signals, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 lines, the blanking area of the display panel is set to 90 lines, and the preset number of cycles is equal to 282.
[0014] In some embodiments, the output of the power manager is connected to the gate driver via a bus.
[0015] In some embodiments, at least one clock counter is integrated into a timing controller, and the input of each clock counter is connected to one output of a level shifter. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit of the display panel according to the first embodiment of this application.
[0017] Figure 2 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit of the display panel according to the second embodiment of this application.
[0018] Figure 3 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit of the display panel according to the third embodiment of this application.
[0019] Figure 4 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit of the display panel according to the fourth embodiment of this application.
[0020] Explanation of main component symbols
[0021] 100. Detection and protection circuit; 11. Timing controller; 12. Level converter; 13. Clock counter; 14. Power manager; 15. Gate driver; 111. Control module.
[0022] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0023] In the description of the embodiments in this application, the words "exemplary," "or," and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary," "or," and "for example" is intended to present the relevant concepts in a specific manner.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It should be understood that, unless otherwise stated, " / " in this application means "or". For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "At least one" refers to one or more. "More than one" refers to two or more. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, and a, b, and c (seven cases).
[0025] It should also be noted that the terms "first" and "second" in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.
[0026] The core of the integrated gate actuator (GOA) technology commonly used in LCD panels lies in the driving and control of the horizontal scanning signal (also known as the GCK global clock signal). This signal is responsible for sequentially activating the gate lines of the panel to refresh the image. Different manufacturers' GOA circuit designs have fundamentally different requirements for the GCK signal output in the horizontal blanking region: some designs require completely stopping the GCK signal output in the blanking region to reduce power consumption, while others require continuously providing the GCK signal in the blanking region to maintain stable gate voltage and charge integrity. This difference necessitates that the timing control chip be compatible with both output modes.
[0027] To meet the aforementioned diverse panel requirements, current mainstream technologies rely on the software-configurable functionality of the timing control chip (TCON). Specifically, the TCON allows users to select between two operating modes by setting internal registers or software instructions: Mode 1 actively stops the output of the GCK signal in the row blanking area; Mode 2 continuously outputs the GCK signal throughout the entire row blanking area. Engineers must manually select and set the correct TCON operating mode during the debugging or production phase, based on the specific panel specifications and design drawings.
[0028] In existing technologies, when TCON is incorrectly set to have no GCK output in the blanking zone, but the panel actually requires a continuous signal, the image usually does not show obvious abnormalities at the standard refresh rate due to the extremely short blanking time. However, with the introduction of modern display technology's Variable Refresh Rate (VRR) mode, the blanking zone duration changes dynamically in this mode. In the low refresh rate scenario of VRR, the lack of GCK signal during the significantly extended blanking period will lead to insufficient gate voltage maintenance, which in turn induces image defects such as ghosting, flickering, and abnormal horizontal lines.
[0029] Furthermore, the existing circuit architecture lacks automatic detection and feedback mechanisms, making it difficult to identify in real time whether the actual GCK signal output from the Level Shift circuit behaves as expected in the blanking region. The only way for engineers to confirm the correctness of the GCK signal (especially the blanking region output state) is to use an external oscilloscope for waveform capture and manual visual inspection. This not only requires interrupting production or disassembling equipment, a complex and time-consuming process, but also makes efficient, real-time monitoring and diagnosis difficult during manufacturing or on-site maintenance.
[0030] Therefore, this application provides a detection and protection circuit for a display panel, which can automatically detect the integrity of the global clock signal, reduce gate voltage anomalies caused by missing blanking area signals, and can replace manual oscilloscope testing, improving debugging efficiency. Some embodiments will be described below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0031] Figure 1 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit 100 of the display panel according to the first embodiment of this application.
[0032] like Figure 1As shown, an embodiment of this application provides a detection and protection circuit 100 that can be used for a display panel. Specifically, the detection and protection circuit 100 can be used to detect whether the global clock signal of the display panel covers the cycle required for a complete row scan of the display panel and to perform power-off protection when an abnormality occurs. In embodiments of this application, the detection and protection circuit 100 may include a timing controller 11, a level converter 12, a clock counter 13, and a power manager 14. The first output terminal of the timing controller 11 is connected to the input terminal of the level converter 12. The input terminal of the clock counter 13 is connected to at least one output terminal of the level converter 12. The output terminal of the clock counter 13 is connected to the input terminal of the timing controller 11. The second output terminal of the timing controller 11 is connected to the input terminal of the power manager 14. The clock counter 13 is used to acquire the number of cycles of the global clock signal output from at least one output terminal of the level converter 12 and output the number of cycles to the timing controller 11. The timing controller 11 is used to control the working state of the power manager 14 according to the comparison result of the number of cycles and a preset number of cycles. The preset number of cycles is equal to the sum of the number of cycles required for the global clock signal to perform line scanning drive in the effective display area and blanking area of the display panel.
[0033] The timing controller 11 can send at least one of the following signals to the level converter 12 via its first output terminal: GCK, CPV (Clock Pulse Voltage, also known as the gate movement signal), or STV (Start Vertical, also known as the frame start signal). The second output terminal of the timing controller 11 is a preset I / O interface, which is connected to the power manager 14 and controls the operating state of the power manager 14, such as whether to output power supply voltage, by outputting a level signal.
[0034] In other embodiments, the timing controller 11 may not need to supply a global clock signal to the level converter 12. As described above, the timing controller 11 can output a gate-on signal and a gate-shift signal to the level converter 12 via a first output terminal, and the level converter 12 can be used to output a global clock signal based on the gate-on signal and the gate-shift signal. In this case, the timing controller 11 outputs a gate-on signal (STV) and a gate-shift signal (CPV) to the level converter 12, which synthesizes the global clock signal (GCK). This allows the required global clock signal to be synthesized from the basic timing signals (i.e., CPV and STV), reducing the design complexity of the timing controller 11 and improving signal immunity. In other words, the level converter 12 in this embodiment can integrate the function of synthesizing the global clock signal (GCK).
[0035] The clock counter 13 acquires the number of global clock signal cycles output by the level converter 12 in real time and feeds it back to the timing controller 11. The timing controller 11 compares this number of cycles with the preset number of cycles (the total number of cycles required for the effective display area + blanking area) and controls the working state of the power manager 14 according to the result. This can automatically detect the integrity of the global clock signal (whether it covers the complete row scan cycle), reduce grid voltage abnormalities caused by missing blanking area signals (such as ghosting / flickering in VRR mode), and replace manual oscilloscope detection and improve debugging efficiency.
[0036] In some embodiments, the power manager 14 can be used for power management of the display panel. The operating state of the power manager 14 can include outputting power supply voltage and stopping outputting power supply voltage. Specifically, if the number of cycles of the global clock signal is greater than or equal to a preset number of cycles, the operating state of the power manager 14 is controlled by the timing controller 11 to output power supply voltage; if the number of cycles of the global clock signal is less than the preset number of cycles, the operating state of the power manager 14 is controlled by the timing controller 11 to stop outputting power supply voltage. In this case, the timing controller 11 switches the operating state of the power manager 14 according to the cycle count comparison result: when the number of cycles is greater than or equal to the preset value, it controls the power manager 14 to output power supply voltage; when the number of cycles is less than the preset value, it controls the power manager 14 to stop outputting voltage. This allows for proactive power-off when the global clock signal is incomplete (such as when the blanking area signal is missing), reducing display failures caused by gate drive abnormalities, while ensuring power supply stability when the signal is normal.
[0037] In some embodiments, the preset number of cycles for the global clock signal, which is also the total number of cycles required to cover a complete row scan of the display panel, can be determined based on the type of the display panel, refresh rate, number of rows in the AA area (i.e., the effective display area), number of rows in the blanking area, and number of GCK channels. For example, taking a 4K display panel as an example, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 rows, and the total number of cycles required for the effective display area is approximately 270. The blanking area of the display panel is set to 90 rows, and the total number of cycles required for the blanking area is approximately 12. The level converter 12 has 8 output terminals for outputting the global clock signal (i.e., 8 GCK channels that can be input to the display panel), so the preset number of cycles can be equal to the sum of the total number of cycles required for the effective display area and the total number of cycles required for the blanking area, which is 282.
[0038] In the embodiments of this application, the type of display panel may include, but is not limited to, one of HD (High Definition), FHD (Full High Definition), QHD (Quad High Definition, also known as 2K screen), UHD (Ultra High Definition, also known as 4K screen) or 8K screen.
[0039] Figure 2 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit 100 of the display panel according to the second embodiment of this application.
[0040] In some embodiments, such as Figure 2 As shown, the timing controller 11 may include a control module 111, meaning the timing controller 11 can integrate control functions. The control module 111 can be a microcontroller or microprocessor, and it can be used to control the operating state of the power manager 14 by adjusting the voltage of its input / output interfaces. In this case, the control module 111 of the timing controller 11 directly controls whether the power manager 14 outputs power voltage to the display panel by adjusting the voltage of its input / output interfaces. This enables rapid control of the power manager 14 by level signals, simplifies the circuit response chain, and improves the real-time performance of protection actions.
[0041] In some embodiments, such as Figure 2 As shown, the clock counter 13 can also be integrated into the timing controller 11. Furthermore, multiple clock counters 13 can be integrated into the timing controller 11, meaning at least one clock counter 13 is integrated into the timing controller 11. The input terminal of each clock counter 13 is connected to one output terminal of the level converter 12. In this case, the clock counter 13 is integrated inside the timing controller 11, and its input terminal is directly connected to the output terminal of the level converter 12, which can reduce external components and improve the integration of signal detection and noise immunity.
[0042] Figure 3 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit 100 of the display panel according to the third embodiment of this application.
[0043] In some embodiments, such as Figure 3 As shown, multiple output terminals of the level converter 12 can be connected to the gate driver 15 disposed on the display panel. In this case, the multiple output terminals of the level converter 12 are directly connected to the gate driver 15 on the display panel to realize the parallel distribution of the global clock signal to the gate driver 15 and ensure the synchronization of the area driving.
[0044] In some embodiments, the level converter 12 may have 8 output terminals for outputting a global clock signal, and the refresh rate of the display panel may be 60Hz, the effective display area of the display panel may be set to 2160 lines, the blanking area of the display panel may be set to 90 lines, and the preset number of cycles may be equal to 282.
[0045] Figure 4 This is a schematic diagram of the circuit structure and connection relationship of the detection and protection circuit 100 of the display panel according to the fourth embodiment of this application.
[0046] In other embodiments, such as Figure 4 As shown, multiple output terminals of the level converter 12 can be connected to multiple input terminals of the timing controller 11, and multiple output terminals of the timing controller 11 are connected to the gate driver 15 disposed on the display panel. In this case, the output terminals of the level converter 12 are connected to the input terminals of the timing controller 11, and then the output terminals of the timing controller 11 are connected to the gate driver 15. The timing controller 11 can act as a signal relay node to reassemble the global clock signal output by the level converter 12 before inputting it into the display panel, thereby enhancing the centralized control capability and anti-interference capability of the global clock signal.
[0047] In some embodiments, the level converter 12 may have 8 output terminals for outputting global clock signals, the timing controller 11 may have 8 input terminals for receiving global clock signals and 8 output terminals for outputting global clock signals, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 lines, the blanking area of the display panel is set to 90 lines, and the preset number of cycles is equal to 282.
[0048] In some embodiments, the gate driver 15 can be disposed in the glass substrate of the display panel, that is, the gate driver 15 can be integrated into the glass substrate of the display panel through GOA (Gate on Array) technology.
[0049] In the embodiments of this application, such as Figure 3 or Figure 4 As shown, since all eight global clock signals (GCK1 to GCK8) are output from the same source, it is possible to determine whether all global clock signals are abnormal by detecting one of the global clock signals (such as GCK1). Therefore, clock counter 13 can be set to one, thereby reducing hardware costs.
[0050] In some embodiments, the output of the power manager 14 can be connected to the gate driver 15 via a bus (such as an I2C bus). In this case, the power manager 14 supplies power to the gate driver 15 via the bus, thereby enabling centralized management of the gate drive power, reducing wiring complexity, and ensuring power supply consistency.
[0051] In summary, this application automatically determines signal integrity by counting the global clock signal cycle in real time and comparing it with a preset value, thereby controlling the power supply to protect the display panel. At the same time, this application can also replace manual detection and prevent display abnormalities caused by missing blanking zone signals (especially in VRR mode), thereby improving system reliability and production efficiency.
[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.
Claims
1. A detection and protection circuit for a display panel, characterized in that, The system includes a timing controller, a level shifter, a clock counter, and a power manager. A first output of the timing controller is connected to the input of the level shifter. The input of the clock counter is connected to at least one output of the level shifter, and the output of the clock counter is connected to the input of the timing controller. A second output of the timing controller is connected to the input of the power manager. The clock counter is used to acquire the number of cycles of a global clock signal output from at least one output of the level shifter and output the number of cycles to the timing controller. The timing controller is used to control the operating state of the power manager based on a comparison between the number of cycles and a preset number of cycles, wherein the preset number of cycles is equal to the sum of the number of cycles required for the global clock signal to perform line scan driving in the effective display area and blanking area of the display panel.
2. The detection and protection circuit for the display panel according to claim 1, characterized in that, The timing controller includes a control module, which is used to control the operating state of the power manager by adjusting the voltage of the input / output interface of the timing controller.
3. The detection and protection circuit for the display panel according to claim 1, characterized in that, The power manager is used for power management of the display panel. The working state of the power manager includes outputting power voltage and stopping outputting power voltage. If the number of cycles is greater than or equal to the preset number of cycles, the working state of the power manager is controlled by the timing controller to output power voltage. If the number of cycles is less than the preset number of cycles, the working state of the power manager is controlled by the timing controller to stop outputting power voltage.
4. The detection and protection circuit for the display panel according to claim 1, characterized in that, The multiple output terminals of the level converter are connected to the gate driver disposed on the display panel.
5. The detection and protection circuit for the display panel according to claim 1, characterized in that, The multiple output terminals of the level converter are connected to the multiple input terminals of the timing controller, and the multiple output terminals of the timing controller are connected to the gate driver disposed on the display panel.
6. The detection and protection circuit for the display panel according to claim 1, characterized in that, The timing controller outputs a gate start signal and a gate move signal to the level converter through the first output terminal. The level converter is used to output the global clock signal according to the gate start signal and the gate move signal.
7. The detection and protection circuit for the display panel according to claim 4, characterized in that, The level converter has 8 output terminals for outputting the global clock signal, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 lines, the blanking area of the display panel is set to 90 lines, and the preset number of cycles is equal to 282.
8. The detection and protection circuit for the display panel according to claim 5, characterized in that, The level converter has 8 output terminals for outputting the global clock signal, the timing controller has 8 input terminals for receiving the global clock signal and 8 output terminals for outputting the global clock signal, the refresh rate of the display panel is 60Hz, the effective display area of the display panel is set to 2160 lines, the blanking area of the display panel is set to 90 lines, and the preset number of cycles is equal to 282.
9. The detection and protection circuit for the display panel according to claim 4 or 5, characterized in that, The output of the power manager is connected to the gate driver via a bus.
10. The detection and protection circuit for the display panel according to claim 1, characterized in that, At least one of the clock counters is integrated into the timing controller, and the input of each clock counter is connected to one output of the level converter.