A novel low-temperature polysilicon goa circuit, cascaded circuit and display device
By employing a novel low-temperature polysilicon GOA circuit in the display panel array substrate, and using the first and second clock signal lines to replace the VDDE and VDDO signal lines, timing control of the pull-down module is achieved. This solves the problem of excessive trace area occupied by the GIP circuit, increases wiring space, and facilitates line adjustment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TRULY (RENSHOU) HIGH-END DISPLAY TECH LTD
- Filing Date
- 2025-06-03
- Publication Date
- 2026-06-16
AI Technical Summary
The existing display panel array substrate's GIP circuit occupies a large amount of trace area, resulting in the distance between the GIP circuit module and the panel edge being too small, which is not conducive to subsequent circuit adjustments.
A novel low-temperature polysilicon GOA circuit is adopted, which electrically connects the first clock signal line and the second clock signal line to the pull-down module to perform timing control on the pull-down module. The first clock signal line and the second clock signal line are used to replace the traditional VDDE and VDDO signal lines, saving wiring space.
By reducing the number of traces, the wiring space was increased, which solved the problem of the insufficient distance between the GIP circuit module and the edge of the panel, making subsequent circuit adjustments easier.
Smart Images
Figure CN224366533U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of GIP technology for display panels, and in particular to a novel low-temperature polycrystalline silicon GOA circuit, cascade circuit and display device. Background Technology
[0002] GIP technology, or Gate in Panel, is a technology that moves the shift register circuit from the IC gate circuit to the panel, integrating the scanning chip onto the display panel. For example... Figure 1 GIP utilizes existing thin-film transistor liquid crystal display (TFT-LCD) array processes to fabricate the gate row scan drive signal circuitry on the display panel. By providing control signals to the panel, it achieves the gate drive function, generating multi-level scan signals to select display pixels. This simplifies the drive circuitry, which was originally external to the sides of the panel, and hides it inside the panel, enabling the display to achieve a narrower bezel design, improving the product's aesthetics and screen-to-body ratio.
[0003] The GIP circuits of the display panel array are generally located on both sides of the screen, occupying a large amount of trace area. This makes the GIP circuit modules very close to the edge of the panel. However, since there is a limit to the distance between the GIP and the edge of the panel, if the distance between the GIP circuit module and the edge of the panel is too small, it will be difficult to make subsequent adjustments. Utility Model Content
[0004] The existing display panel array substrate's GIP circuit occupies a large amount of trace area, resulting in the distance between the GIP circuit module and the panel edge being too small, which is not conducive to subsequent circuit adjustments.
[0005] To address the aforementioned issues, a novel low-temperature polysilicon GOA circuit, cascaded circuit, and display device are proposed. By electrically connecting the first and second clock signal lines to the pull-down module, timing control of the pull-down module is achieved. The first and second clock signal lines replace the traditional VDDE and VDDO signal lines, saving wiring space in the GOA circuit. This solves the problem that the existing display panel array substrate's GIP circuit occupies a large amount of wiring area, resulting in an excessively small distance between the GIP circuit module and the panel edge, which is detrimental to subsequent circuit adjustments.
[0006] Firstly, a novel low-temperature polycrystalline silicon GOA circuit includes:
[0007] Pull-up module;
[0008] Drop-down module;
[0009] Output module;
[0010] Start signal line;
[0011] First clock signal line and second clock signal line;
[0012] The start signal line is electrically connected to the first end of the pull-up module;
[0013] The first clock signal line is electrically connected to the first terminal of the pull-down module and the first terminal of the output module, respectively.
[0014] The second end of the pull-up module, the second end of the pull-down module, and the second end of the output module are all connected to a common connection point;
[0015] The second clock signal line is electrically connected to the third terminal of the pull-down module, and the fourth terminal of the pull-down module is electrically connected to the output terminal of the output module.
[0016] In conjunction with the novel low-temperature polycrystalline silicon GOA circuit described in this utility model, in a first possible embodiment, the first clock signal line and the second clock signal line are respectively used to output the inverted first clock drive timing and the second clock drive timing.
[0017] The first clock drive timing sequence and the second clock drive timing sequence are respectively used to drive the pull-down module after the output module outputs a high level.
[0018] In conjunction with the first possible embodiment of this utility model, in the second possible embodiment, the drop-down module includes:
[0019] First dropdown unit and second dropdown unit;
[0020] After the first pull-down unit and the second pull-down unit are connected in parallel, they are electrically connected to the output terminal of the output module, and are electrically connected to the common contact point through the output module, for pulling down the level of the common contact point and the output terminal.
[0021] Secondly, a cascaded circuit of a novel low-temperature polycrystalline silicon GOA circuit includes multiple novel low-temperature polycrystalline silicon GOA circuits as described in the first aspect, wherein the novel low-temperature polycrystalline silicon GOA circuits are cascaded together, and the cascaded circuit further includes:
[0022] First clock cascade and second clock cascade;
[0023] The first clock cascade line is connected to the first clock signal line of each of the novel low-temperature polysilicon GOA circuits to obtain a first timing signal;
[0024] The second clock cascade line is connected to the second clock signal line of each of the novel low-temperature polysilicon GOA circuits to obtain the second timing signal.
[0025] In conjunction with the cascaded circuit of the novel low-temperature polycrystalline silicon GOA circuit described in the second aspect of this utility model, in a first possible embodiment, the cascaded circuit further includes:
[0026] Start signal cascading;
[0027] The startup signal cascade line is connected to the startup signal line of the novel low-temperature polycrystalline silicon GOA circuit in the first row.
[0028] In conjunction with the cascaded circuit of the novel low-temperature polycrystalline silicon GOA circuit described in the second aspect of this utility model, in a second possible embodiment, the cascaded interconnection of the novel low-temperature polycrystalline silicon GOA circuits includes:
[0029] The output terminal of the output module in the previous row is electrically connected to the start terminal of the pull-up module in the next row.
[0030] Thirdly, a display device includes the cascaded circuit described in the second aspect.
[0031] The novel low-temperature polycrystalline silicon GOA circuit, cascaded circuit, and display device described in this utility model achieve timing control of the pull-down module by electrically connecting the first clock signal line and the second clock signal line to the pull-down module. By using the first clock signal line and the second clock signal line to replace the traditional VDDE and VDDO signal lines, the wiring space of the GOA circuit is saved. This solves the problem that the existing display panel array substrate's GIP circuit occupies a large amount of wiring area, resulting in an excessively small distance between the GIP circuit module and the panel edge, which is not conducive to subsequent circuit adjustment. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of the overall layout of the display device in this application;
[0034] Figure 2 This is a schematic diagram of the module circuit structure of the low-temperature polycrystalline silicon GOA circuit in the prior art;
[0035] Figure 3 This is a module circuit structure diagram of a specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application;
[0036] Figure 4This is a module circuit structure diagram of another specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application;
[0037] Figure 5 It is a modular circuit structure diagram of a cascaded circuit in the prior art;
[0038] Figure 6 This is a schematic diagram of the modular circuit structure of the cascaded circuit in this application;
[0039] Figure 7 This is a circuit schematic diagram of a specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application. Detailed Implementation
[0040] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0042] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0043] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0045] The existing display panel array substrate's GIP circuitry occupies a large amount of trace area, resulting in an insufficient distance between the GIP circuit module and the panel edge, which is detrimental to subsequent circuit adjustments. For example... Figure 2 and Figure 5 , Figure 2 This is a modular circuit structure diagram of a low-temperature polycrystalline silicon GOA circuit in the prior art. Figure 5 This is a modular circuit structure diagram of a cascaded circuit in existing technology; in Figure 2 and Figure 5 In this circuit, two signal lines, VDDE and VDDO, are used to control the pull-down module to pull down the level of the common contact P and the output terminal Gout of the output module, thus preventing display abnormalities.
[0046] To address the aforementioned issues, a novel low-temperature polycrystalline silicon GOA circuit, cascaded circuit, and display device are proposed.
[0047] Firstly, a novel low-temperature polycrystalline silicon GOA circuit, such as... Figure 3 , Figure 3 This is a module circuit structure diagram of a specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application; it includes a pull-up module, a pull-down module, an output module, a start signal line STV; a first clock signal line CK1 and a second clock signal line CK1B; the start signal line STV is electrically connected to the first terminal of the pull-up module; the first clock signal line CK1 is electrically connected to the first terminal of the pull-down module and the first terminal of the output module respectively; the second terminals of the pull-up module, the pull-down module, and the output module are all connected to a common connection point P; the second clock signal line CK1B is electrically connected to the third terminal of the pull-down module, and the fourth terminal of the pull-down module is electrically connected to the output terminal Gout of the output module.
[0048] In this embodiment, by electrically connecting the first clock signal line CK1 and the second clock signal line CK1B to the pull-down module, timing control of the pull-down module is achieved. The first clock signal line CK1 and the second clock signal line CK1B replace the traditional VDDE and VDDO signal lines, saving wiring space in the GOA circuit. This solves the problem that the existing display panel array substrate's GIP circuit occupies a large amount of wiring area, resulting in the distance between the GIP circuit module and the panel edge being too small, which is not conducive to subsequent line adjustment.
[0049] In this embodiment, the first clock signal line CK1 and the second clock signal line CK1B are used to replace the traditional VDDE and VDDO signal lines to control the pull-down module, reducing wiring and increasing wiring space.
[0050] Furthermore, the first clock signal line CK1 and the second clock signal line CK1B are used to output the inverted first clock drive timing and the second clock drive timing, respectively; the first clock drive timing and the second clock drive timing are used to drive the pull-down module after the output module outputs a high level.
[0051] The first clock signal line CK1 and the second clock signal line CK1B alternately output high levels. After the output module outputs the drive signal, the first clock signal line CK1 outputs the first clock drive timing to drive the pull-down module. After the output module outputs the drive signal, the second clock signal line CK1B outputs the second clock drive timing to drive the pull-down module.
[0052] Furthermore, such as Figure 4 , Figure 4 This is a module circuit structure diagram of another specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application; the pull-down module includes a first pull-down unit and a second pull-down unit; the first pull-down unit and the second pull-down unit are connected in parallel and electrically connected to the output terminal Gout of the output module, and are electrically connected to the common contact P through the capacitor of the output module, for pulling down the level of the common contact P and the level of the output terminal Gout of the output module.
[0053] In this embodiment, after the output terminal Gout outputs the gate drive signal, as follows: Figure 7 , Figure 7 This is a circuit schematic diagram of a specific embodiment of the novel low-temperature polycrystalline silicon GOA circuit in this application, and its circuit structure is as follows. Figure 7 As shown, the first pull-down unit includes transistors T4 and T6, and the second pull-down unit includes transistors T5 and T7. Transistors T4 and T6 are connected in parallel and electrically connected to the output terminal Gout of the output module, and are also electrically connected to the common contact P through capacitor C1. Transistors T5 and T7 are connected in parallel and electrically connected to the output terminal Gout of the output module, and are also electrically connected to the common contact P through capacitor C1. During the display process, the first clock signal line CK1 and the second clock signal line CK1B replace the traditional VDDE and VDDO signal lines, alternately outputting high-level pulses. Transistors T4 and T6 and transistors T5 and T7 are alternately turned on to transmit the low-level VGL to the level of the common contact P and the output terminal Gout of the output module.
[0054] Secondly, a novel cascaded circuit for low-temperature polycrystalline silicon GOA circuits, such as... Figure 6 , Figure 6This is a schematic diagram of the cascaded circuit module in this application. It includes multiple novel low-temperature polysilicon GOA circuits of the first aspect, which are cascaded together. The cascaded circuit further includes: a first clock cascade line 120 and a second clock cascade line 130; the first clock cascade line 120 is connected to the first clock signal line CK1 of each novel low-temperature polysilicon GOA circuit to obtain a first timing signal; the second clock cascade line 130 is connected to the second clock signal line CK1B of each novel low-temperature polysilicon GOA circuit to obtain a second timing signal.
[0055] Furthermore, the cascaded circuit also includes a start signal cascade line 110; the start signal cascade line 110 is connected to the start signal line STV of the novel low-temperature polysilicon GOA circuit in the first row.
[0056] Furthermore, the novel low-temperature polycrystalline silicon GOA circuits are cascaded together, with the output terminal Gout of the output module in the previous row electrically connected to the start terminal of the pull-up module in the next row.
[0057] Thirdly, a display device includes the cascaded circuitry of the second aspect.
[0058] The novel low-temperature polysilicon GOA circuit, cascaded circuit, and display device implementing this utility model electrically connect the first clock signal line CK1 and the second clock signal line CK1B to the pull-down module to perform timing control of the pull-down module. By using the first clock signal line CK1 and the second clock signal line CK1B to replace the traditional VDDE and VDDO signal lines, the wiring space of the GOA circuit is saved. This solves the problem that the existing display panel array substrate's GIP circuit occupies a large amount of wiring area, resulting in the distance between the GIP circuit module and the panel edge being too small, which is not conducive to subsequent circuit adjustment.
[0059] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A novel low-temperature polycrystalline silicon GOA circuit, characterized in that, include: Pull-up module; Drop-down module; Output module; Start signal line; First clock signal line and second clock signal line; The start signal line is electrically connected to the first end of the pull-up module; The first clock signal line is electrically connected to the first terminal of the pull-down module and the first terminal of the output module, respectively. The second end of the pull-up module, the second end of the pull-down module, and the second end of the output module are all connected to a common connection point; The second clock signal line is electrically connected to the third terminal of the pull-down module, and the fourth terminal of the pull-down module is electrically connected to the output terminal of the output module.
2. The novel low-temperature polycrystalline silicon GOA circuit according to claim 1, characterized in that, The first clock signal line and the second clock signal line are respectively used to output the inverted first clock drive timing and the second clock drive timing; The first clock drive timing sequence and the second clock drive timing sequence are respectively used to drive the pull-down module after the output module outputs a high level.
3. The novel low-temperature polycrystalline silicon GOA circuit according to claim 2, characterized in that, The drop-down module includes: First dropdown unit and second dropdown unit; After the first pull-down unit and the second pull-down unit are connected in parallel, they are electrically connected to the output terminal of the output module, and are electrically connected to the common contact point through the output module, for pulling down the level of the common contact point and the output terminal.
4. A novel cascaded circuit for a low-temperature polycrystalline silicon GOA circuit, characterized in that, The circuit includes a novel low-temperature polycrystalline silicon GOA circuit as described in any one of claims 1-3, wherein the novel low-temperature polycrystalline silicon GOA circuits are cascaded together, and the cascaded circuit further includes: First clock cascade and second clock cascade; The first clock cascade line is connected to the first clock signal line of each of the novel low-temperature polysilicon GOA circuits to obtain a first timing signal; The second clock cascade line is connected to the second clock signal line of each of the novel low-temperature polysilicon GOA circuits to obtain the second timing signal.
5. The cascaded circuit of the novel low-temperature polycrystalline silicon GOA circuit according to claim 4, characterized in that, The cascaded circuit also includes: Start signal cascading; The startup signal cascade line is connected to the startup signal line of the novel low-temperature polycrystalline silicon GOA circuit in the first row.
6. The cascaded circuit of the novel low-temperature polycrystalline silicon GOA circuit according to claim 4, characterized in that, The novel low-temperature polycrystalline silicon GOA circuits are interconnected, including: The output terminal of the output module in the previous row is electrically connected to the start terminal of the pull-up module in the next row.
7. A display device, characterized in that, Includes the cascaded circuit as described in any one of claims 4-6.