Display device

Abstract

A display device includes a substrate; a first transistor over the substrate; a second transistor over and overlapping with the first transistor; and an anode electrode over the second transistor and connected to the first transistor, wherein the first transistor includes a first active pattern over the substrate, and a gate electrode over and overlapping with the first active pattern, and wherein the second transistor includes a first lower electrode over the gate electrode, an upper electrode over the first lower electrode and including a first opening overlapping with the first lower electrode, a second active pattern over the upper electrode and connected to the first lower electrode through the first opening, and a first gate wiring over and overlapping with the second active pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0078722, filed on June 18, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0111443, filed on August 20, 2024, with the entire contents of each of the two Korean patent applications incorporated herein by reference. Technical Field

[0003] One or more embodiments of this utility model relate to a display device (e.g., to a pixel), a display device including the pixel, and an electronic device including the display device. Background Technology

[0004] With the growing interest in information displays, research and development of display devices has been ongoing and actively carried out. Utility Model Content

[0005] One or more aspects of embodiments of this disclosure are directed to high-resolution display devices having improved pixel integration density.

[0006] One or more aspects of embodiments of this disclosure relate to pixels included in display devices and / or electronic devices.

[0007] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of embodiments of this disclosure.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first transistor on the substrate (e.g., disposed on the substrate); a second transistor on the first transistor (disposed on the first transistor) and overlapping the first transistor; and an anode electrode on the second transistor (disposed on the second transistor) and connected to the first transistor, wherein the first transistor includes: a first active pattern on the substrate (e.g., disposed on the substrate); and a gate electrode on the first active pattern (e.g., disposed on the first active pattern) and overlapping the first active pattern, and the second transistor includes: a first lower electrode on the gate electrode (e.g., disposed on the gate electrode); an upper electrode on the first lower electrode (e.g., disposed on the lower electrode) and including a first opening overlapping the first lower electrode; a second active pattern on the upper electrode (e.g., disposed on the upper electrode) and connected to the first lower electrode through the first opening; and a first gate wiring on the second active pattern (e.g., disposed on the second active pattern) and overlapping the second active pattern.

[0009] In one or more embodiments, the first active pattern may include low-temperature polycrystalline silicon (LTPS), and the second active pattern may include oxide semiconductor.

[0010] In one or more embodiments, the display device may further include: a first active layer including a first active pattern; a first gate layer including a gate electrode; a second gate layer between the first gate layer and a first lower electrode (e.g., disposed between the first gate layer and the first lower electrode); a lower conductive layer including a first lower electrode; an upper conductive layer including an upper electrode; a second active layer including a second active pattern; and a third gate layer including a first gate wiring.

[0011] In one or more embodiments, the display device may further include a third transistor that is in the same layer as the second transistor (e.g., arranged in the same layer).

[0012] In one or more embodiments, the third transistor may include: a second lower electrode, included in a lower conductive layer and spaced and / or separated from the first lower electrode (e.g., spaced apart or separated); an upper electrode, on the second lower electrode (e.g., disposed on the second lower electrode), and including a second opening overlapping the second lower electrode; a third active pattern, included in a second active layer, spaced and / or separated from the second active pattern (e.g., spaced apart or separated), connected to the second lower electrode through the second opening, and including an oxide semiconductor; and a second gate wiring, included in a third gate layer, spaced and / or separated from the first gate wiring (e.g., spaced apart or separated), and overlapping the third active pattern.

[0013] In one or more embodiments, the second gate layer may overlap with the gate electrode, and the overlapping gate electrode and the second gate layer may form (e.g., constitute) a first capacitor.

[0014] In one or more embodiments, the second gate layer may overlap with the first lower electrode, and the overlapping second gate layer and the first lower electrode may form (e.g., constitute) a second capacitor.

[0015] In one or more embodiments, the first lower electrode and the gate electrode may be connected to each other.

[0016] In one or more embodiments, the display device may further include a first conductive layer on a third gate layer (e.g., disposed on a third gate layer) and include power supply wiring for transmitting an initialization voltage and data wiring for transmitting a data voltage.

[0017] In one or more embodiments, the display device may further include a second conductive layer between the first conductive layer and the anode electrode (e.g., disposed between the first conductive layer and the anode electrode).

[0018] In one or more embodiments, the lower conductive layer can be connected to the first active layer through at least one first contact hole, and the lower conductive layer can be connected to the second conductive layer through at least one second contact hole.

[0019] In one or more embodiments, the first contact hole and the second contact hole may overlap each other.

[0020] In one or more embodiments, the data wiring may overlap with the upper electrode, and the overlapping upper electrode and data wiring may form (e.g., constitute) a third capacitor.

[0021] In one or more embodiments, the display device may further include: a first lower metal layer between a substrate and a first active layer (e.g., disposed between the substrate and the first active layer); and a second lower metal layer between the first lower metal layer and the first active layer (e.g., disposed between the first lower metal layer and the first active layer).

[0022] In one or more embodiments, the first lower metal layer and the second lower metal layer may overlap each other, and the overlapping first lower metal layer and the second lower metal layer may form (e.g., constitute) a fourth capacitor.

[0023] In one or more embodiments, a data voltage may be applied to a first lower metal layer, and a second lower metal layer may be electrically connected to an upper conductive layer via a second gate layer.

[0024] In one or more embodiments, the second gate layer can be connected to the second lower metal layer via a third contact hole and to the upper conductive layer via a fourth contact hole.

[0025] In one or more embodiments, the third contact hole and the fourth contact hole may overlap each other.

[0026] According to one or more embodiments of this disclosure, a pixel includes: a first transistor connected between a first power supply voltage node to which a first power supply voltage is applied and a first node, and having a gate electrode connected to a second node; a second transistor connected between the second node and a third node, and having a gate electrode connected to a first gate electrode line, to which a first gate electrode signal is applied; a third transistor connected between the third node and the first node, and having a gate electrode connected to a second gate electrode line, to which a second gate electrode signal is applied; a first capacitor connected between an initialization voltage node to which an initialization voltage is applied and the second node; a second capacitor connected between a data line to which a data signal is applied and the third node; and a light-emitting element connected between the first node and the second power supply voltage node to which a second power supply voltage is applied, wherein the first transistor is a P-type transistor, and both the second and third transistors (e.g., simultaneously) are N-type transistors.

[0027] According to one or more embodiments of this disclosure, an electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device includes: a substrate; a first transistor on the substrate; a second transistor on and overlapping the first transistor; and an anode electrode on the second transistor and connected to the first transistor. The first transistor includes: a first active pattern on the substrate; and a gate electrode on and overlapping the first active pattern. The second transistor includes: a first lower electrode on the gate electrode; an upper electrode on the first lower electrode and including a first opening overlapping the first lower electrode; a second active pattern on the upper electrode and connected to the first lower electrode through the first opening; and a first gate wiring on and overlapping the second active pattern.

[0028] Specific details of one or more embodiments will be provided in the detailed description and accompanying drawings.

[0029] According to the above embodiments, when a first transistor comprising polysilicon and a second transistor comprising oxide semiconductor overlap each other in a planar view, and are arranged on different layers and share the same electrode, and contact holes for electrically connecting corresponding electrodes overlap each other, the pixel integration density is increased, thereby enabling a high-resolution display device. For example, when the first transistor (polysilicon) and the second transistor (oxide semiconductor) overlap in a planar view, and contact holes on different layers share the same electrode, the pixel integration density is increased, thereby enabling a high-resolution display device.

[0030] Additionally, by increasing the capacitance of the second capacitor connected to the data wiring that transmits the data voltage, the transmission rate of the data voltage to the first transistor can be increased, and variations in the data voltage transmission rate can be minimized or reduced. For example, increasing the capacitance of the second capacitor connected to the data wiring increases the transmission rate of the data voltage to the first transistor and minimizes or reduces variations in the transmission rate.

[0031] The aspects and / or effects of the embodiments are not limited to those described above, and one or more other aspects and / or effects are also included in this disclosure. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to illustrate the principles of this disclosure. The above and / or other aspects of this disclosure will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings.

[0033] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0034] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A circuit diagram of one of the multiple sub-pixels.

[0035] Figure 3 This illustrates one or more embodiments according to the present disclosure. Figure 1 A floor plan of the display panel.

[0036] Figure 4 This illustrates one or more embodiments according to the present disclosure. Figure 3 A cross-sectional view of the display panel.

[0037] Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 3 A cross-sectional view of the display panel.

[0038] Figures 6 to 26 Each is an illustration of one or more embodiments according to this disclosure. Figure 3 A layout diagram of a magnified portion of the display area of ​​the display panel.

[0039] Figure 27 This is a block diagram illustrating a display system according to one or more embodiments of the present disclosure.

[0040] Figure 28 This illustrates one or more embodiments according to the present disclosure. Figure 27 A perspective view of an application example of the display system.

[0041] Figure 29 This illustrates a user-wearable device according to one or more embodiments of the present disclosure. Figure 28 A diagram of a head-mounted display device. Detailed Implementation

[0042] The embodiments of this disclosure may be modified in one or more suitable ways and may have various forms, and exemplary embodiments are shown in the accompanying drawings and will be described in more detail in the specification. However, this is not intended to limit this disclosure to any particular form and should be understood to include all modifications, equivalents, and substitutions falling within the spirit and scope of this disclosure.

[0043] In describing the accompanying drawings, similar reference numerals are used for similar components. In the drawings, for clarity of this disclosure, the dimensions of structures may be illustrated as larger than their actual dimensions. Terms such as "first," "second," etc., may be used to describe one or more suitable components, but such components should not be limited by such terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0044] In this disclosure, terms such as “include(s) / including,” “comprise(s) / comprising,” or “have(has) / having” are intended to specify the presence of the described features, quantities, steps, operations, components, parts, and / or one or more (e.g., any suitable) combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or one or more (e.g., any suitable) combinations thereof. When a layer, film, region, plate, or other element is said to be “on” another element, it includes not only embodiments where the element is directly on the other element, but also embodiments where there are one or more intervening elements between them. In contrast, if (e.g., when) an element is said to be “directly on” another element, then there are no intervening elements between them. In this disclosure, if (e.g., when) a layer, film, region, plate, or other element is said to be “formed” on another element, the direction of formation is not limited to an upward direction, but also includes transverse or downward formation. Additionally, if (for example, when) a layer, film, region, plate or other element is said to be "below" another element, it includes embodiments in which said element is "directly below" another element and embodiments in which there is an intervening element between them.

[0045] In the following description, exemplary embodiments and other details of the present disclosure, which are readily understood by those skilled in the art, will be described in more detail with reference to the accompanying drawings. In the following description, singular expressions include plural expressions unless it is obvious from the context that they are limited to the singular; for example, the singular forms “a,” “an,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, when describing embodiments of the present disclosure, the use of “may” means “one or more embodiments of the present disclosure.”

[0046] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0047] refer to Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0048] The display panel DP includes sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn. n and m are positive integers.

[0049] Subpixels (SPs) can generate light of two or more colors. For example, each subpixel SP can generate light such as red, green, blue, cyan, magenta, and / or yellow.

[0050] Two or more sub-pixels SP can form a pixel PXL. For example, as shown... Figure 1 As shown, in one or more embodiments, pixel PXL may include three sub-pixels SP. Therefore, pixel PXL may emit one or more suitable colors and brightness levels of light based on a combination of light emitted from each of the plurality of sub-pixels SP included in pixel PXL.

[0051] Gate driver 120 is connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 may output gate signals to the first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In one or more embodiments, gate control signal GCS may include a start signal indicating the start of each frame and / or a horizontal synchronization signal, etc.

[0052] In one or more embodiments, the gate driver 120 may be arranged on one side of the display panel DP. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and such drivers may be arranged on one side and the other side of the display panel DP, respectively. In this way, the gate driver 120 may be arranged around the display panel DP in one or more suitable forms according to embodiments.

[0053] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In one or more embodiments, data control signal DCS may include source start signal, source shift clock, and / or source output enable signal, etc.

[0054] The data driver 130 can receive voltage from the voltage generator 140. Using the received voltage, the data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0055] In one or more embodiments, gate driver 120 and data driver 130 may each include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0056] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of the display device DD, such as gate driver 120, data driver 130, and controller 150. Voltage generator 140 can generate multiple voltages by receiving an input voltage from outside the display device DD and adjusting the received voltage.

[0057] In one or more embodiments, voltage generator 140 can generate a first power supply voltage and a second power supply voltage. The generated first and second power supply voltages can be supplied to sub-pixels SP via power line PL. In one or more embodiments, at least one of the first and second power supply voltages can be provided externally to the display device DD.

[0058] Additionally, voltage generator 140 can provide one or more suitable and / or designed voltages and / or signals. For example, in one or more embodiments, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, in one or more embodiments, during sensing operations that sense the electrical characteristics of transistors and / or light-emitting elements in sub-pixel SP, a set or predetermined reference voltage can be applied to first data lines DL1 to nth data lines DLn, and voltage generator 140 can generate said reference voltage and transmit said reference voltage to data driver 130. For example, during display operations for displaying images in display panel DP, common pixel control signals can be applied to sub-pixel SP, and voltage generator 140 can generate these pixel control signals. In one or more embodiments, voltage generator 140 can provide pixel control signals to sub-pixel SP via pixel control line PXCL. Although Figure 1 The pixel control line PXCL is shown connected between the voltage generator 140 and the display panel DP, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. In such an embodiment, pixel control signals can be transmitted from the voltage generator 140 to the pixel control line PXCL via the gate driver 120.

[0059] The controller 150 can control the overall operation of the display device DD. The controller 150 receives input image data IMG and the corresponding control signal CTRL from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0060] The controller 150 can convert input image data IMG into a format suitable for a display device DD or a display panel DP and output image data DATA. In one or more embodiments, the controller 150 can arrange the input image data IMG on a row-by-row basis to fit sub-pixels SP and output image data DATA.

[0061] Two or more components of the data driver 130, voltage generator 140, and controller 150 (e.g., selected from two or more components of the data driver 130, voltage generator 140, and controller 150) can be implemented on a single integrated circuit. Figure 1As shown, in one or more embodiments, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In these embodiments, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In one or more embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit (DIC).

[0062] Figure 2 This illustrates one or more embodiments according to the present disclosure. Figure 1 A circuit diagram of one of multiple sub-pixels. Figure 2 The diagram schematically illustrates the arrangement in Figure 1 The sub-pixels SPij in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixel SP.

[0063] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0064] The light-emitting element (LD) is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN is connected to... Figure 1 The first power line among multiple power lines PL receives the first power supply voltage supplied from the first power line. The second power supply voltage node VSSN is connected to a different power line. Figure 1 The second power line of the first power line among multiple power lines PL receives a second power supply voltage supplied from the second power line. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0065] The light-emitting element LD is connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to the first power supply voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to the second power supply voltage node VSSN. The light-emitting element LD is configured to emit light based on the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0066] Sub-pixel circuit SPC can be connected to Figure 1 The first gate line GL1 to the m-th gate line GLm, and connected to the i-th gate line GLi. Figure 1The j-th data line DLj is one of the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC is configured to control the light-emitting element LD based on the signals received through these signal lines.

[0067] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In one or more embodiments, as... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, if (for example, when) the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to gate signals received through these sub-gate lines.

[0068] The sub-pixel circuit SPC can receive data signals via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of a plurality of gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2.

[0069] To perform these operations, the sub-pixel circuit (SPC) may include pixel circuitry, such as transistors and one or more capacitors.

[0070] The transistors of the sub-pixel circuit SPC may include P-type (P) transistors and / or N-type (N) transistors. In one or more embodiments, the transistors of the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In one or more embodiments, the transistors of the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, and / or oxide semiconductors, etc.

[0071] For example, in one or more embodiments, the sub-pixel circuit SPC may include a first transistor T1 to a third transistor T3, a first capacitor C1, and a second capacitor C2.

[0072] The first transistor T1 may be connected between the first power supply voltage node VDDN and the first node N1. Additionally, the first transistor T1 may have a gate electrode connected to the second node N2. For example, in one or more embodiments, the first transistor T1 may be a drive transistor that generates drive current. In these embodiments, the first transistor T1 may be a P-type transistor.

[0073] The second transistor T2 can be connected between the second node N2 and the third node N3. Additionally, the second transistor T2 can have a gate electrode connected to the first sub-gate line SGL1. For example, in one or more embodiments, the first gate signal received through the first sub-gate line SGL1 can be a write gate signal. In these embodiments, the second transistor T2 can be an N-type transistor.

[0074] The third transistor T3 can be connected between the third node N3 and the first node N1. Additionally, the third transistor T3 can have a gate electrode connected to the second sub-gate line SGL2. For example, in one or more embodiments, the second gate signal received through the second sub-gate line SGL2 can be a compensation gate signal. In these embodiments, the third transistor T3 can be an N-type transistor.

[0075] The first capacitor C1 can be connected between the initialization voltage node VINTN to which the initialization voltage is applied and the second node N2. The second capacitor C2 can be connected between the data line DLj to which the data signal is applied and the third node N3. The data signal transmission rate can vary depending on the capacitance of the second capacitor C2. For example, as the capacitance of the second capacitor C2 increases, the data signal transmission rate can be increased.

[0076] Therefore, the light-emitting element LD can be connected between the first node N1 connected to the first transistor T1 and the second power supply voltage node VSSN, and can generate light with a brightness corresponding to the data signal.

[0077] Figure 3 This illustrates one or more embodiments according to the present disclosure. Figure 1 A floor plan of the display panel.

[0078] refer to Figure 3 The display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays the image through the display area DA. The non-display area NDA is arranged around the display area DA.

[0079] The display panel DP includes subpixels in the display area DA. Subpixels can be arranged on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Two or more subpixels can form a pixel PXL. For illustration, it is assumed that a pixel PXL includes two subpixels SP1 and SP2.

[0080] Each of the first sub-pixel SP1 and the second sub-pixel SP2 can generate light of one or more suitable colors (such as red, green, blue, cyan, magenta, or yellow).

[0081] Each of the first sub-pixel SP1 and the second sub-pixel SP2 may include at least one light-emitting element configured to generate light. In one or more embodiments, the light-emitting elements of the first sub-pixel SP1 and the second sub-pixel SP2 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1 and the second sub-pixel SP2 may generate blue light. In one or more embodiments, the light-emitting elements of the first sub-pixel SP1 and the second sub-pixel SP2 may generate light of different colors.

[0082] Self-emitting display panels (such as light-emitting diode (LED) display panels that use micron- or nano-sized light-emitting diodes as light-emitting elements or organic light-emitting display panels (OLED panels) that use organic light-emitting diodes as light-emitting elements) can be used as display panel DP.

[0083] In the non-display area NDA, sub-pixels SP can be arranged (see...). Figure 1 ) components. Wiring connected to the sub-pixel SP (such as...) Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL can be arranged in the non-display area NDA.

[0084] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 may be arranged in the non-display area NDA of the display panel DP. In one or more embodiments, the gate driver 120 may be arranged in the non-display area NDA. In these embodiments, such as Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 can be implemented as a driver integrated circuit (DIC) separate from the display panel (DP), and the driver integrated circuit (DIC) can be connected to wiring arranged in the non-display area (NDA). In one or more embodiments, the gate driver 120 can be implemented together with the data driver 130, voltage generator 140, and controller 150 as a single integrated circuit separate from the display panel (DP).

[0085] In one or more embodiments, the display area DA may have one or more suitable shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, or an ellipse.

[0086] In one or more embodiments, the display panel DP may have a flat display surface. In one or more embodiments, the display panel DP may have a rounded display surface, or at least partially rounded display surface. In one or more embodiments, the display panel DP may be bendable, foldable, or rollable. In these embodiments, the display panel DP and / or the substrate SUB of the display panel DP may include a material with flexible properties.

[0087] Figure 4 This illustrates one or more embodiments according to the present disclosure. Figure 3 A cross-sectional view of the display panel.

[0088] refer to Figure 4 The display panel DP may include a substrate SUB, and a pixel circuit layer PCL, a display element layer DPL, and an optical function layer LFL that are sequentially stacked on the substrate SUB on a third direction DR3 that intersects with the first direction DR1 and the second direction DR2.

[0089] The substrate SUB can be made of an insulating material such as glass or resin. For example, in one or more embodiments, the substrate SUB may include a glass substrate. In one or more embodiments, the substrate SUB may include a polyimide (PI) substrate. In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes.

[0090] In one or more embodiments, the substrate SUB may be made of a flexible material that allows bending or folding, and may have a single-layer or multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments of this disclosure are not limited to these materials.

[0091] The pixel circuit layer (PCL) is disposed on the substrate (SUB). The PCL may include an insulating layer and semiconductor electrodes and conductive electrodes disposed between the insulating layers. The conductive electrodes of the PCL can be used as circuit elements and / or wiring, etc.

[0092] The circuit elements of the pixel circuit layer PCL may include Figure 1 The sub-pixel circuit SPC for each of the multiple sub-pixels SP (see [link]). Figure 2 For example, the circuit elements of the pixel circuit layer PCL can be provided as transistors and one or more capacitors for the sub-pixel circuit SPC.

[0093] The wiring of the pixel circuit layer (PCL) may include wiring connected to the sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include one or more suitable signal lines and / or voltage lines required to drive the display element layer (DPL).

[0094] The display element layer (DPL) is arranged on the pixel circuit layer (PCL). The display element layer (DPL) may include the light-emitting elements of the sub-pixels (SP).

[0095] An optical functional layer (LFL) may be disposed on a display element layer (DPL). The LFL may include a light conversion pattern with color conversion particles and / or a light scattering pattern with scattering particles. For example, the color conversion particles may include quantum dots. Quantum dots can change the wavelength (or color) of light emitted from the display element layer (DPL). In one or more embodiments, the LFL may also include a light scattering pattern with scattering particles. In one or more embodiments, neither a light conversion pattern nor a light scattering pattern may be provided.

[0096] In one or more embodiments, the optical functional layer (LFL) may further include a color filter layer containing a color filter. The color filter can selectively transmit light of a specific wavelength (or a specific color). In one or more embodiments, a color filter layer may not be provided.

[0097] In one or more embodiments, a window may be provided on the optical functional layer (LFL) to protect the exposed surface (or upper surface) of the display panel (DP). The window protects the display panel (DP) from external impacts. The window may be coupled to the optical functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from glass substrates, plastic films, and plastic substrates. This multilayer structure may be formed by a continuous process or an adhesive process using adhesive layers. In one or more embodiments, all or part of the window may be flexible.

[0098] Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 3 A cross-sectional view of the display panel.

[0099] refer to Figure 5 The display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light function layer LFL. The substrate SUB, pixel circuit layer PCL, display element layer DPL, and light function layer LFL may each be similar to a reference layer. Figure 4 The substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and optical function layer (LFL) are configured as described below. Further details will not be provided.

[0100] The input sensing layer (ISL) can detect user input on the upper surface (or display surface) of the display panel (DP). The input sensing layer (ISL) may include a configuration suitable for detecting external objects such as a user's hand or pen. For example, in one or more embodiments, the input sensing layer (ISL) may include touch electrodes.

[0101] Figures 6 to 26 Each is an illustration of one or more embodiments according to this disclosure. Figure 3 A layout diagram of a magnified portion of the display area of ​​the display panel. Figures 6 to 26 Each is only shown Figure 3 The pixel circuit layer (PCL) of the display panel (see Figure 4 ) layout diagram.

[0102] For example, Figures 6 to 26 The structure arranged in the first sub-pixel region SPA1 and the second sub-pixel region SPA2 adjacent to the first sub-pixel region SPA1 is described, wherein the structures are respectively placed in the first sub-pixel region SPA1 and the second sub-pixel region SPA2. Figure 3 The first sub-pixel SP1 and the second sub-pixel SP2. The second sub-pixel SP2 may have a structure that is symmetrical with respect to the structure of the first sub-pixel SP1 with respect to an imaginary line of symmetry.

[0103] refer to Figure 6 A first lower metal layer UBML can be disposed on a substrate. The first lower metal layer UBML may include a main portion BDP and a bridging portion BRP disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The main portion BDP and the bridging portion BRP can be integrally formed. The bridging portion BRP extends in the second direction DR2, and the main portion BDP can be connected to another adjacent sub-pixel in the second direction DR2 via the bridging portion BRP.

[0104] exist Figure 3 In the non-display area NDA, the first lower metal layer UBML can be connected via the second gate layer GAT2, which will be described in more detail later (see [link to NDA]). Figure 13 ) Received data voltage. In this respect, the data voltage can be represented by... Figure 2 The value of the data signal transmitted by the data line DLj.

[0105] refer to Figure 7 The second lower metal layer (BML) can be placed in the first lower metal layer (UBML) (see...). Figure 6 The second lower metal layer BML may include a shielding electrode BMLa disposed in the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and a first capacitor electrode BMLb disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0106] The shielding electrode BMLa can be connected between the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and can extend to other adjacent sub-pixel regions in the first direction DR1. The first capacitor electrode BMLb can be spaced apart from the shielding electrode BMLa (e.g., spaced apart or separated), and can be arranged in an island shape.

[0107] refer to Figure 8 The shielding electrode BMLa can shield the first transistor T1 (see...). Figure 12 This will be described in more detail later. The shielding electrode BMLa overlaps with the first transistor T1 and can shield the first transistor T1 from multiple voltages that affect the first transistor T1 (such as the data voltage transmitted by the first lower metal layer UBML). Therefore, the shielding electrode BMLa can ensure the operational reliability of the first transistor T1.

[0108] First lower metal layer UBML (see...) Figure 6 ) and the second lower metal layer BML (see Figure 7 They can overlap each other. For example, the first capacitor electrode BMLb of the second lower metal layer BML can overlap with the main body portion BDP of the first lower metal layer UBML. The first capacitor electrode BMLb and the main body portion BDP can form a second-1 capacitor C2-1. The second-1 capacitor C2-1 can form Figure 2 This is part of the second capacitor C2. In this respect, the first lower metal layer UBML and the second lower metal layer BML can each receive different voltages, resulting in a voltage difference between the first lower metal layer UBML and the second lower metal layer BML. Charge can be stored in the second capacitor C2-1 in proportion to this voltage difference.

[0109] In one or more embodiments, the shapes of the first lower metal layer UBML and the second lower metal layer BML can be modified in various ways. In one or more embodiments, the first lower metal layer UBML and the second lower metal layer BML may not be provided.

[0110] refer to Figure 9 and Figure 10 The first active layer ACT1 can be disposed on the second lower metal layer BML. The first active layer ACT1 may include low-temperature polycrystalline silicon (LTPS).

[0111] The first active layer ACT1 may include a first active pattern AP1 disposed in a first sub-pixel region SPA1 and a second sub-pixel region SPA2. The first active pattern AP1 is connected between the first sub-pixel region SPA1 and the second sub-pixel region SPA2 and can be integrally formed. The first active pattern AP1 can be formed... Figure 2The first transistor T1. Because the first transistor T1 is a P-type transistor, the first active pattern AP1 may include a doped region doped with P-type (type) dopant.

[0112] refer to Figure 11 and Figure 12 The first gate layer GAT1 can be arranged in the first active layer ACT1 (see Figure 9 The first gate layer GAT1 may include a metal, alloy, conductive metal oxide, and / or transparent conductive material. For example, in one or more embodiments, the first gate layer GAT1 may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

[0113] The first gate layer GAT1 may include a gate electrode GT1a disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The gate electrode GT1a may be arranged in an island shape. The gate electrode GT1a may overlap with the first active pattern AP1. The overlapping gate electrode GT1a and the first active pattern AP1 may form a first transistor T1.

[0114] refer to Figure 13 and Figure 14 The second gate layer GAT2 can be disposed on the first gate layer GAT1. The second gate layer GAT2 may include metals, alloys, conductive metal oxides, and / or transparent conductive materials. For example, in one or more embodiments, the second gate layer GAT2 may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

[0115] The second gate layer GAT2 may include a second capacitor electrode GT2a disposed in the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and a first connection electrode GT2b disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0116] The second capacitor electrode GT2a can be connected between the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and can extend to other adjacent sub-pixel regions in the first direction DR1. The second capacitor electrode GT2a is connected to the first power supply wiring SD1b (see...). Figure 24 (This will be described in more detail later), and the initialization voltage can be received via the first power supply line SD1b. In this regard, the initialization voltage can be referred to via... Figure 2 The initial voltage transmitted by the VINTN node is the initial voltage.

[0117] The second capacitor electrode GT2a can overlap with the gate electrode GT1a. The overlapping gate electrode GT1a and the second capacitor electrode GT2a can form a first-I capacitor C1-1. The first-I capacitor C1-1 can form Figure 2 This is a portion of the first capacitor C1. In this respect, the gate electrode GT1a and the second capacitor electrode GT2a can each receive different voltages, resulting in a voltage difference between the gate electrode GT1a and the second capacitor electrode GT2a. Charge can be stored in the first capacitor C1-1 in proportion to this voltage difference.

[0118] The first connecting electrode GT2b may be spaced apart from and / or separated from the second capacitor electrode GT2a (e.g., spaced apart or separated), and may be arranged in an island shape. The first connecting electrode GT2b may be connected to the second lower metal layer BML through the second-1 contact hole CNT2-1 (see...). Figure 7 The first capacitor electrode BMLb.

[0119] refer to Figure 15 and Figure 16 The lower conductive layer BSD can be arranged in the second gate layer GAT2 (see...). Figure 13 The lower conductive layer BSD can include metals, alloys, conductive metal oxides, and / or transparent conductive materials. For example, in one or more embodiments, the lower conductive layer BSD can include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

[0120] The lower conductive layer BSD may include a second connecting electrode BSDa disposed in the first sub-pixel region SPA1 and the second sub-pixel region SPA2, a first lower electrode BSDb disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and a second lower electrode BSDc disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0121] The second connection electrode BSDa can be arranged across the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The second connection electrode BSDa can be connected to the first active pattern AP1 through the first-1 contact hole CNT1-1 (see...). Figure 9 ).

[0122] The first lower electrode BSDb may be spaced and / or separated from the second connection electrode BSDa (e.g., spaced apart or separate). The first lower electrode BSDb may be arranged in the first transistor T1 (see...). Figure 12 It can be placed on top of the first transistor T1 and can overlap with it. Additionally, the first lower electrode BSDb can be formed... Figure 2 The second transistor T2.

[0123] The first lower electrode BSDb can partially overlap with the second capacitor electrode GT2a included in the second gate layer GAT2. The overlapping second capacitor electrode GT2a and the first lower electrode BSDb can form a first-2 capacitor C1-2. The first-2 capacitor C1-2 can form Figure 2 This is part of the first capacitor C1. In this respect, the second capacitor electrode GT2a and the first lower electrode BSDb can receive different voltages, resulting in a voltage difference between the second capacitor electrode GT2a and the first lower electrode BSDb. Charge can be stored in the first capacitor C1-2 in proportion to this voltage difference.

[0124] Additionally, the first lower electrode BSDb can be connected to the gate electrode GT1a via the contact hole BSDCH. For example, the first lower electrode BSDb can have the same voltage as the gate electrode GT1a. Therefore, the first -1 capacitor C1-1 (see...) Figure 14 The first capacitor (C1-2) and the second capacitor (C1-2) can be connected in parallel to form a single first capacitor. In this respect, the first capacitor can be provided as... Figure 2 The first capacitor C1. Because the first-1 capacitor C1-1 and the first-2 capacitor C1-2 are connected in parallel, the first capacitor C1 can have a capacitance equal to the sum of the capacitances of the first-1 capacitor C1-1 and the first-2 capacitor C1-2.

[0125] The second lower electrode BSDc can be spaced apart and / or separated from the second connecting electrode BSDa and the first lower electrode BSDb (e.g., spaced apart or separated). Additionally, the second lower electrode BSDc can form... Figure 2 The third transistor T3.

[0126] The second lower electrode BSDc can be connected to the first active pattern AP1 through the first-1 contact hole CNT1-1. Therefore, the lower conductive layer BSD and the first active layer ACT1 (see...) Figure 9 They can be connected to each other through at least one first-1 contact hole CNT1-1. For example, since the second connecting electrode BSDa is connected to the first active pattern AP1 through the first-1 contact hole CNT1-1, and the second lower electrode BSDc is also connected to the first active pattern AP1 through the first-1 contact hole CNT1-1, the lower conductive layer BSD and the first active layer ACT1 included in the first sub-pixel region SPA1 and the second sub-pixel region SPA2 in a pixel can be connected to each other through a total of three first-1 contact holes CNT1-1.

[0127] refer to Figure 17 and Figure 18 The upper conductive layer TSD can be placed on the lower conductive layer BSD (see Figure 15The upper conductive layer TSD may include metals, alloys, conductive metal oxides, and / or transparent conductive materials. For example, in one or more embodiments, the upper conductive layer TSD may include a transparent conductive material such as indium zinc oxide.

[0128] The upper conductive layer TSD may include an upper electrode TSDa disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The upper electrode TSDa may have a shape extending in the second direction DR2.

[0129] The upper electrode TSDa can be arranged in Figure 15 The upper electrode TSDa is located on the first lower electrode BSDb and the second lower electrode BSDc. The upper electrode TSDa can overlap with the first lower electrode BSDb and can be formed together with the first lower electrode BSDb. Figure 2 The second transistor T2. Additionally, the upper electrode TSDa can overlap with the second lower electrode BSDc, and can be formed together with the second lower electrode BSDc. Figure 2 The third transistor T3.

[0130] The upper electrode TSDa may include a first opening OP1 that overlaps with the first lower electrode BSDb and a second opening OP2 that overlaps with the second lower electrode BSDc. For example, the first lower electrode BSDb may be exposed through the first opening OP1, and the second lower electrode BSDc may be exposed through the second opening OP2.

[0131] The upper electrode TSDa can be connected via the second-2 contact hole CNT2-2 to the second gate layer GAT2 (see...). Figure 13 The first connecting electrode GT2b in ) (see Figure 13 Therefore, the upper electrode TSDa can be connected via the first connection electrode GT2b (see...). Figure 16 Electrically connected to the second lower metal layer BML (see...) Figure 7 The first capacitor electrode BMLb in ) (see Figure 7 Therefore, the upper electrode TSDa, the first connecting electrode GT2b, and the first capacitor electrode BMLb can have the same voltage.

[0132] Additionally, the second-1 contact hole CNT2-1 connected to the second gate layer GAT2 (see...) Figure 14 The second-1 contact hole CNT2-1 and the second-2 contact hole CNT2-2 can overlap in the plan view. By overlapping the second-1 contact hole CNT2-1 and the second-2 contact hole CNT2-2, the pixel integration density can be increased, thereby enabling high-resolution display devices.

[0133] refer to Figure 19 and Figure 20The second active layer ACT2 can be disposed on the upper conductive layer TSD. The second active layer ACT2 and the first active layer ACT1 can include different materials.

[0134] The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and / or magnesium (Mg). For example, in one or more embodiments, the second active layer ACT2 may include indium gallium zinc oxide. The second active layer ACT2 may include a second active pattern AP2 and a third active pattern AP3 disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The second active pattern AP2 and the third active pattern AP3 may each be arranged in an island shape. In this context, unless otherwise defined, "island shape" refers to an isolated and distinct pattern or structure resembling an island. This pattern is surrounded by different materials or spaces, making it stand out as a separate entity. For example, the active patterns AP2 and AP3 are arranged much like islands in the sea, isolated from each other and from the surrounding area.

[0135] The second active pattern AP2 can be coupled with the first lower electrode BSDb (see...). Figure 18 ) and the first opening OP1 of the upper electrode TSDa (see Figure 18 The second active pattern AP2 can be connected to the upper electrode TSDa and can also be connected to the first lower electrode BSDb through the first opening OP1. For example, the second active pattern AP2 can directly contact the upper electrode TSDa adjacent to the first opening OP1, and can also directly contact the first lower electrode BSDb through the first opening OP1.

[0136] The second active pattern AP2 can be formed Figure 2 The second transistor T2. Because the second transistor T2 is an N-type transistor, the second active pattern AP2 may include a doped region doped with an N-type (type) dopant.

[0137] The third active pattern AP3 may be spaced apart and / or separated from the second active pattern AP2 (e.g., spaced apart or separated), and may be connected to the second lower electrode BSDc (see [link to relevant documentation]). Figure 18 ) and the second opening OP2 of the upper electrode TSDa (see Figure 18 The third active pattern AP3 can be connected to the upper electrode TSDa and can also be connected to the second lower electrode BSDc through the second opening OP2. For example, the third active pattern AP3 can directly contact the upper electrode TSDa adjacent to the second opening OP2, and can also directly contact the second lower electrode BSDc through the second opening OP2.

[0138] The third active pattern AP3 can be formed Figure 2 The third transistor T3. Because the third transistor T3 is an N-type transistor, the third active pattern AP3 can include doped regions doped with N-type (type) dopants.

[0139] refer to Figure 21 and Figure 22 The third gate layer GAT3 can be arranged in the second active layer ACT2 (see Figure 19 The third gate layer GAT3 may comprise a metal, alloy, metal nitride, and / or conductive metal oxide. For example, in one or more embodiments, the third gate layer GAT3 may comprise a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti).

[0140] The third gate layer GAT3 may include a first gate wiring GT3a and a second gate wiring GT3b arranged in the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0141] The first gate wiring GT3a can be connected between the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and can extend to other adjacent sub-pixel regions in the first direction DR1. The first gate wiring GT3a can provide... Figure 2 The first sub-gate line SGL1. For example, the first gate wiring GT3a can transmit the first gate signal as a write gate signal.

[0142] The first gate wiring GT3a can be arranged on the second active pattern AP2 and can overlap with the second active pattern AP2. The overlapping first lower electrode BSDb (see...) Figure 18 ), upper electrode TSDa (see Figure 18 The second active pattern AP2 and the first gate wiring GT3a can form the second transistor T2.

[0143] Because the first lower electrode BSDb, the upper electrode TSDa, the second active pattern AP2, and the first gate wiring GT3a form the first transistor T1 (see...). Figure 12 The first active pattern AP1 (see) Figure 12 ) and gate electrode GT1a (see Figure 12 Since the transistors overlap, the second transistor T2 can overlap with the first transistor T1.

[0144] Because the first transistor T1 and the second transistor T2 are arranged in different layers and overlap in the planar diagram, the pixel integration density can be increased, thereby enabling a high-resolution display device.

[0145] The second gate wiring GT3b may be spaced apart from and / or separated from the first gate wiring GT3a on the second direction DR2 (e.g., spaced apart or separated). The second gate wiring GT3b connects between the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and may extend to other adjacent sub-pixel regions on the first direction DR1. The second gate wiring GT3b can provide... Figure 2 The second sub-gate line SGL2. For example, the second gate wiring GT3b can transmit a second gate signal as a compensation gate signal.

[0146] The second gate wiring GT3b can be arranged on the third active pattern AP3 and can overlap with the third active pattern AP3. The overlapping second lower electrode BSDc (see...) Figure 18 The upper electrode TSDa, the third active pattern AP3, and the second gate wiring GT3b can form the third transistor T3. Therefore, the third transistor T3 can be arranged in the same layer as the second transistor T2.

[0147] refer to Figure 23 and Figure 24 The first conductive layer SD1 can be disposed on the third gate layer GAT3. The first conductive layer SD1 may include metal, alloy, conductive metal oxide and / or transparent conductive material, etc.

[0148] The first conductive layer SD1 may include a first power supply wiring SD1b arranged across the boundary between sub-pixel regions of other adjacent pixels in the first direction DR1, and a data wiring SD1a arranged in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0149] The first power supply wiring SD1b can extend on the second direction DR2 and can be arranged at the boundary between the sub-pixel regions of adjacent pixels on the first direction DR1. The first power supply wiring SD1b can receive and transmit an initialization voltage. The first power supply wiring SD1b can be connected via contact hole SD1CH to the second gate layer GAT2 (see...). Figure 13 The second capacitor electrode GT2a in ) (see Figure 13 Therefore, the first power supply wiring SD1b can apply an initialization voltage to the second capacitor electrode GT2a.

[0150] The data routing SD1a is spaced apart from and / or separated from the first power routing SD1b in the first direction DR1 (e.g., spaced apart or separated), and may extend in the second direction DR2. The data routing SD1a may extend to other adjacent sub-pixel regions in the second direction DR2.

[0151] Data wiring SD1a can receive and transmit data voltage. For example, because data wiring SD1a and the first lower metal layer UBML (see...) Figure 6 Each receives its own data voltage, so they can have the same voltage.

[0152] Data routing SD1a can overlap with the upper electrode TSDa. Overlapping upper electrode TSDa (see...) Figure 17 The data wiring SD1a and the second-2 capacitor C2-2 can be formed. The second-2 capacitor C2-2 can be formed Figure 2 This is part of the second capacitor C2. In this respect, the upper electrode TSDa and the data wiring SD1a can receive different voltages, resulting in a voltage difference between the upper electrode TSDa and the data wiring SD1a. Charge can be stored in each of the plurality of second capacitors C2-2 in proportion to this voltage difference.

[0153] Additionally, the first connection electrode GT2b (see also) is included in the second gate layer GAT2. Figure 14 It can be accessed through the second-1 contact hole CNT2-1 (see...) Figure 14 ) connected to the second lower metal layer BML (see Figure 7 The first capacitor electrode BMLb in ) (see Figure 14 And it can be accessed through the second-2 contact hole CNT2-2 (see...) Figure 18 The upper electrode TSDa is connected to the upper electrode TSDa included in the upper conductive layer TSD. Therefore, the upper electrode TSDa can be electrically connected to the first capacitor electrode BMLb included in the second lower metal layer BML via the first connection electrode GT2b. Thus, the upper electrode TSDa, the first connection electrode GT2b, and the first capacitor electrode BMLb can have the same voltage.

[0154] Therefore, the second capacitor C2-1 (see...) Figure 8 The first capacitor (C1) and the second capacitor (C2-2) can be connected in parallel to form a single second capacitor. In this respect, the second capacitor can be provided as... Figure 2 The second capacitor C2. Because the second-1 capacitor C2-1 and the second-2 capacitor C2-2 are connected in parallel, the second capacitor can have a capacitance equal to the sum of the capacitances of the second-1 capacitor C2-1 and the second-2 capacitor C2-2.

[0155] In one or more embodiments, the capacitance of the second capacitor can be increased because it comprises a plurality of capacitors connected in parallel (e.g., composed of a plurality of capacitors connected in parallel). When a data voltage is applied to a sub-pixel, the data voltage can be transmitted to the first transistor T1 (see [reference]) in a ratio of (the capacitance of the second capacitor) / (the capacitance of the first capacitor + the capacitance of the second capacitor). Figure 2 The gate electrode of the second capacitor. For example, by increasing the capacitance of the second capacitor, the data voltage transmission rate can be increased. Furthermore, by increasing the capacitance of the second capacitor, variations in the data voltage transmission rate can be minimized or reduced.

[0156] refer to Figure 25 and Figure 26 The second conductive layer SD2 can be disposed in the first conductive layer SD1 (see Figure 23 The second conductive layer SD2 may include metals, alloys, conductive metal oxides, and / or transparent conductive materials.

[0157] The second conductive layer SD2 may include a second power supply wiring SD2a disposed in the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and a third connection electrode SD2b disposed in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2.

[0158] The second power supply wiring SD2a connects the first sub-pixel region SPA1 and the second sub-pixel region SPA2, and can extend to other adjacent sub-pixel regions in the first direction DR1. The second power supply wiring SD2a can be connected to the underlying conductive layer BSD (see [link to BSD]) via the first-2 contact holes CNT1-2. Figure 15 The second connecting electrode BSDa in ).

[0159] The second power supply wiring SD2a can receive and transmit the first power supply voltage. In this regard, the first power supply voltage can refer to... Figure 2 The first power supply voltage of the first power supply node VDDN is transmitted.

[0160] The third connection electrode SD2b may be spaced and / or separated from the second power supply wiring SD2a (e.g., spaced apart or separate). The third connection electrode SD2b may be arranged in an island shape. The third connection electrode SD2b may be connected to the second lower electrode BSDc of the lower conductive layer BSD through the first-2 contact holes CNT1-2. Additionally, the third connection electrode SD2b may be connected to the anode electrode through the contact hole SD2CH, which will be described in more detail later.

[0161] The second conductive layer SD2 and the lower conductive layer BSD can be connected to each other through at least one first-2 contact hole CNT1-2. For example, in one or more embodiments, the second power supply wiring SD2a is connected to the second connection electrode BSDa through the first-2 contact hole CNT1-2, and the third connection electrode SD2b is also connected to the second lower electrode BSDc through the first-2 contact hole CNT1-2. Therefore, in the first sub-pixel region SPA1 and the second sub-pixel region SPA2 included in the pixel, the second conductive layer SD2 and the lower conductive layer BSD can be connected to each other through three first-2 contact holes CNT1-2. Therefore, the lower conductive layer BSD can be connected through the first-1 contact hole CNT1-1 (see...). Figure 16 Connected to the first active layer ACT1 (see...) Figure 9 ), and is connected to the second conductive layer SD2 through the first-2 contact holes CNT1-2.

[0162] For example, the second power supply wiring SD2a is connected to the second connection electrode BSDa included in the lower conductive layer BSD through the first-2 contact hole CNT1-2, and the second connection electrode BSDa is connected to the first active pattern AP1 through the first-1 contact hole CNT1-1 (see...). Figure 9 This allows the first power supply voltage to be transmitted from the second power supply wiring SD2a to the first active layer ACT1.

[0163] Additionally, the third connecting electrode SD2b is connected to the second lower electrode BSDc included in the lower conductive layer BSD through the first-2 contact hole CNT1-2, and the second lower electrode BSDc is connected to the first active pattern AP1 through the first-1 contact hole CNT1-1. Therefore, the anode electrode ( Figure 2 The anode electrode AE), the second lower electrode BSDc, and the first active pattern AP1 can be electrically connected to each other. Therefore, including the first transistor T1 (see...) Figure 2 The light-emitting element and anode electrode of the transistor can be electrically connected, and it includes a third transistor T3 (see [link to transistor T3]). Figure 2 The light-emitting element and anode electrode can also be electrically connected.

[0164] Furthermore, the first-1 contact holes CNT1-1 and the first-2 contact holes CNT1-2, which are connected to the underlying conductive layer BSD, can overlap in a plan view. By overlapping the first-1 contact holes CNT1-1 and the first-2 contact holes CNT1-2, pixel integration density can be increased, thereby enabling high-resolution display devices. In this context, unless otherwise specified, a plan view refers to a view of an object or layout viewed from above. In technical drawings, it is an orthographic projection showing the arrangement of components as seen from above, thus providing a clear layout of how different elements are positioned relative to each other.

[0165] The anode electrode can be disposed on the second conductive layer SD2. The anode electrode may include metals, alloys, conductive metal oxides, and / or transparent conductive materials, etc.

[0166] An anode electrode can be provided in each of the first sub-pixel region SPA1 and the second sub-pixel region SPA2. The anode electrode can be provided as... Figure 2 The anode electrode AE. The anode electrode can form Figure 2 It is part of the light-emitting element.

[0167] The anode electrode can be connected to the third connection electrode SD2b through the contact hole SD2CH. Through this connection, the anode electrode can be electrically connected to the first transistor T1 and the third transistor T3.

[0168] It can be obtained from the first lower metal layer UBML (see Figure 6 At least one insulating layer is arranged between each layer of the anode electrode. Therefore, except for the contact hole portion, each layer can be insulated from each other, and overlapping electrodes with different voltages applied can form a transistor or a capacitor.

[0169] In one or more embodiments, if (e.g., when) a first transistor comprising polysilicon and a second transistor comprising oxide semiconductor overlap each other, and contact holes arranged on different layers and sharing the same electrode to electrically connect the corresponding electrodes overlap each other (e.g., first-1 contact hole CNT1-1 and first-2 contact hole CNT1-2, or second-1 contact hole CNT2-1 (see...) Figure 14 ) and second-2 contact hole CNT2-2 (see Figure 18 This can increase pixel integration density, thereby allowing for high-resolution display devices.

[0170] Furthermore, by increasing the capacitance of the second capacitor connected to the data wiring SD1a that transmits the data voltage, the transmission rate of the data voltage transmitted to the first transistor T1 can be increased, and the variation in the transmission rate of the data voltage can be minimized or reduced.

[0171] Figure 27 This is a block diagram illustrating a display system according to one or more embodiments of the present disclosure.

[0172] refer to Figure 27 The display system 1000 may include a processor 1100 and one or more display devices 1210, 1220.

[0173] Processor 1100 can perform one or more suitable tasks and calculations. In one or more embodiments, processor 1100 may include an application processor, graphics processor, microprocessor, and / or central processing unit (CPU), etc. Processor 1100 may be connected to and control other components of display system 1000 via a bus system.

[0174] exist Figure 27 In the diagram, the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 is connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0175] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can also display an image with reference to... Figure 1 The described display device DD is configured in essentially the same manner. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided respectively as... Figure 1 The input image data is IMG and the control signal is CTRL.

[0176] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be compared with a reference... Figure 1 The described display device DD is configured in essentially the same manner. In this case, the second image data IMG2 and the second control signal CTRL2 can be provided as... Figure 1 The input image data is IMG and the control signal is CTRL.

[0177] Display system 1000 may include a computing system that provides image display capabilities, such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation system, or ultra-mobile PC (UMPC). Additionally, display system 1000 may include at least one of a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0178] Figure 28 This illustrates one or more embodiments according to the present disclosure. Figure 27A perspective view of an application example of the display system.

[0179] refer to Figure 28 In one or more embodiments, Figure 27 The display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0180] The head-mounted display device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap to secure the head-mounted display device 2000 to a user's head. The horizontal strap may be configured to surround (e.g., encircle) the sides of the user's head, and the vertical strap may be configured to surround (e.g., encircle) the top of the user's head. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the headband 2100 may be implemented in the form of an eyeglass frame, a helmet, or other shapes.

[0181] The display device housing 2200 can accommodate Figure 27 The first display device 1210 and the second display device 1220. The display device housing 2200 can further accommodate... Figure 27 The processor is 1100.

[0182] Figure 29 This illustrates a user-wearable device according to one or more embodiments of the present disclosure. Figure 28 A view of a head-mounted display device.

[0183] refer to Figure 29 Inside the head-mounted display device 2000, a first display panel DP1 of the first display device 1210 is arranged (see...). Figure 27 ) and the second display panel DP2 of the second display device 1220 (see Figure 27 The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0184] Inside the display device housing 2200, the right lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Inside the display device housing 2200, the left lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0185] In one or more embodiments, an image output from the first display panel DP1 can be displayed to the user's right eye via a right lens RLNS. The right lens RLNS can refract light from the first display panel DP1 toward the user's right eye. The right lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0186] In one or more embodiments, the image output from the second display panel DP2 can be displayed to the user's left eye via a left lens LLNS. The left lens LLNS can refract light from the second display panel DP2 toward the user's left eye. The left lens LLNS can perform optical functions to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0187] In one or more embodiments, each of the right lens RLNS and the left lens LLNS may include an optical lens having a pancake-shaped cross-section. In one or more embodiments, each of the right lens RLNS and the left lens LLNS may include a multi-channel lens with sub-regions having different optical properties. In these embodiments, each display panel may output an image corresponding to each of the multiple sub-regions of the multi-channel lens, and the output image may pass through each sub-region for viewing by the user.

[0188] According to one or more embodiments of this disclosure, the display device can be applied to one or more electronic devices. The electronic devices may include one or more selected from televisions, monitors, billboards, personal computers, laptops, personal digital terminals, display devices for automobiles, game consoles, portable electronic devices, Internet of Things (IoT) devices, cameras, mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, ultra-mobile personal computers, smartwatches, watch phones, head-mounted displays, virtual reality devices, mixed reality devices, and augmented reality devices.

[0189] In the context of this application, unless otherwise specified, the term “use (use, using, and used)” may be considered synonymous with the terms “utilize (utilizing, utilizing, and utilized)”, respectively.

[0190] In view of the full contents of this disclosure, those skilled in the art will understand that, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0191] Display devices, electronic devices / apparatus, display device manufacturing apparatus, or any other related devices / apparatus or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on a single integrated circuit (IC) chip or a discrete IC chip. Furthermore, various components of the device may be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in a computing device using a standard storage device such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as, for example, CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of embodiments of the present disclosure.

[0192] Although certain technical aspects of this disclosure have been described in more detail with reference to the embodiments described above, it should be noted that these embodiments are for illustrative purposes and are not intended to limit the scope of this disclosure. Those skilled in the art will understand that one or more suitable modifications are possible within the scope of the technical concept of this disclosure.

[0193] The scope of this disclosure should not be limited to the specific embodiments described herein, but should be defined by the claims and their equivalents. All modifications or variations derived from the meaning and scope of the claims and their equivalents should be construed as including within the scope of this disclosure.

Claims

1. A display device, characterized in that, The display device includes: Base; A first transistor is located on the substrate; A second transistor, situated on and overlapping the first transistor; and The anode electrode is located on the second transistor and connected to the first transistor. The first transistor includes: A first active pattern, on the substrate; and The gate electrode is on and overlaps with the first active pattern, and The second transistor includes: The first lower electrode is on the gate electrode; An upper electrode is on the first lower electrode and includes a first opening that overlaps with the first lower electrode; A second active pattern is formed on the upper electrode and connected to the first lower electrode through the first opening; and The first gate wiring is on and overlaps with the second active pattern.

2. The display device according to claim 1, characterized in that: The first active pattern is a low-temperature polycrystalline silicon active pattern, and The second active pattern is an oxide semiconductor active pattern.

3. The display device according to claim 1, characterized in that, The display device further includes: The first active layer includes the first active pattern; A first gate layer includes the gate electrode; The second gate layer is located between the first gate layer and the first lower electrode; The lower conductive layer includes the first lower electrode; Upper conductive layer, including the upper electrode; The second active layer includes the second active pattern; The third gate layer includes the first gate wiring; and The third transistor is in the same layer as the second transistor.

4. The display device according to claim 3, characterized in that, The third transistor includes: The second lower electrode is located in the lower conductive layer and is spaced apart from the first lower electrode; The upper electrode is on the second lower electrode and includes a second opening that overlaps with the second lower electrode; A third active pattern, spaced apart from the second active pattern in the second active layer, is connected to the second lower electrode through the second opening, and includes an oxide semiconductor; and The second gate wiring is spaced from the first gate wiring in the third gate layer and overlaps with the third active pattern.

5. The display device according to claim 3, characterized in that: The second gate layer overlaps with the gate electrode; The overlapping gate electrode and the second gate layer constitute a first capacitor; The second gate layer overlaps with the first lower electrode; and The overlapping second gate layer and the first lower electrode constitute a second capacitor.

6. The display device according to claim 5, characterized in that, The first lower electrode and the gate electrode are connected to each other.

7. The display device according to claim 3, characterized in that, The display device further includes: A first conductive layer is disposed on the third gate layer and includes power supply wiring for transmitting initialization voltage and data wiring for transmitting data voltage; and A second conductive layer is located between the first conductive layer and the anode electrode.

8. The display device according to claim 7, characterized in that, The lower conductive layer is connected to the first active layer through at least one first contact hole, and to the second conductive layer through at least one second contact hole.

9. The display device according to claim 8, characterized in that, The first contact hole and the second contact hole overlap each other.

10. The display device according to claim 7, characterized in that: The data wiring overlaps with the upper electrode; and The overlapping upper electrode and the data wiring constitute a third capacitor.

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