A miniaturized chip capacitor
By employing a five-layer functional structure and a flexible encapsulation shell design, the problems of large size and insufficient vibration resistance of traditional capacitors are solved, achieving miniaturization, high-frequency performance, and high-temperature stability in capacitors suitable for high-frequency, high-speed circuits and high-vibration environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- DONGGUAN JUNKANG ELECTRONIC TECH CO LTD
- Filing Date
- 2025-06-20
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional capacitors are large in size and difficult to shrink further. Their electrical performance is insufficient to meet the application requirements of high-frequency, high-speed circuits and high-temperature environments, and their vibration resistance is inadequate.
It adopts a five-layer structure consisting of a high dielectric constant gradient layer, a stress buffer transition layer, a low-loss core layer, a mechanical reinforcement layer, and a surface passivation protection layer. Combined with a flexible packaging shell and "Z"-shaped pins, it is integrally cured and molded with liquid silicone rubber to achieve miniaturization and high-frequency performance improvement. Furthermore, the inner wall annular groove is interference-fitted with the body to improve vibration resistance.
Achieving a capacitance of 11.5μF in an ultra-thin form factor significantly improves the capacitance density per unit volume. The low-loss core layer and stress buffer transition layer work together to reduce ESR to 4.2mΩ and increase SRF to 1.3GHz. The flexible packaging shell and ceramic body packaging structure have passed mechanical shock testing to ensure the long-term stability of the capacitor in high vibration scenarios.
Smart Images
Figure CN224384094U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of capacitors, and specifically to a miniaturized chip capacitor. Background Technology
[0002] With the rapid development of electronic technology, electronic devices are constantly evolving towards high frequency and high density integration. Traditional capacitors, as basic components in electronic circuits, have long been widely used in various electronic devices, accumulating a profound technical foundation and rich application experience. The production process of traditional capacitors has become highly mature, achieving large-scale automated production, thereby effectively reducing unit costs. This makes traditional capacitors highly competitive in price-sensitive applications, such as consumer electronics and home appliances.
[0003] Although traditional capacitors meet the basic needs of electronic devices to a certain extent, their large size makes it difficult to further shrink them to fit high-density circuit board layouts. This has become a major constraint in the development trend of miniaturized and integrated electronic devices. Their electrical performance, such as equivalent series resistance and self-resonant frequency, often cannot reach the ideal state, which limits their application in high-frequency, high-speed circuits and high-temperature operating environments. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a miniaturized chip capacitor. It achieves an 11.5μF capacitance value in an ultra-thin size through a high dielectric constant gradient layer, significantly improving the capacitance density per unit volume compared to traditional devices, thus solving the miniaturization problem. The low-loss core layer and stress-buffered transition layer work together to achieve an ESR as low as 4.2mΩ and an SRF of 1.3GHz at 1MHz. The flexible encapsulation shell and "Z"-shaped leads enhance the capacitor's vibration resistance and mechanical reliability. The flexible encapsulation shell, integrally cured from liquid silicone rubber, utilizes an inner annular groove for interference fit with the body, along with "Z"-shaped bent leads with ball contacts at the ends, significantly improving vibration resistance compared to traditional capacitors. The encapsulation structure of the flexible shell and ceramic body has passed the GB / T 42277-2022 mechanical shock test, ensuring the long-term stability of the capacitor in high-vibration environments.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] A miniaturized surface mount capacitor includes a body, a flexible encapsulation shell, and leads. The body comprises a high dielectric constant gradient layer, a stress buffer transition layer, a low-loss core layer, a mechanical reinforcement layer, and a surface passivation protection layer, which are sequentially stacked to form the body. At least one of the bodies is encapsulated within the flexible encapsulation shell, and the body is electrically connected to an electrolyte layer. The flexible encapsulation shell is integrally cured from liquid silicone rubber, and the leads are Z-shaped bends with a spherical contact at the end.
[0007] The flexible packaging shell has an annular groove on its inner wall, which is interference-fitted with the body, and leads extend from the bottom.
[0008] The spherical contact at the end of the pin has a diameter of 0.15mm-0.25mm, and is connected by being embedded in the circuit board pad hole and cured with conductive adhesive.
[0009] The high dielectric constant gradient layer is a lanthanum-niobium modified barium zirconate titanate-based ceramic with a thickness of 10μm-20μm and a dielectric constant of 3000-5000εr. By reducing the electric field concentration effect, the capacitance change rate at the operating temperature of the capacitor is ≤±3%.
[0010] The stress buffer transition layer is a manganese-niobate-magnesium lead-titanate based relaxor ferroelectric ceramic with a thickness of 5μm-15μm and a dielectric constant of 1500-2000εr, used to alleviate the thermal expansion mismatch between the high dielectric layer and the core layer and improve the thermal cycling fatigue life.
[0011] The low-loss core layer, samarium-zinc titanate barium-based ceramic, has a thickness of 50μm-80μm and a dielectric constant of 2000-3000εr. As the main energy storage layer, it has low dielectric loss and high-temperature stability.
[0012] The mechanical reinforcement layer is made of yttrium oxide-silicon nitride ceramic with a thickness of 20μm-30μm and a dielectric constant of 800-1200εr, which is used to improve the rigidity of the body, suppress crack propagation, and improve vibration resistance.
[0013] The surface passivation protective layer is a composite coating of aluminum oxide and silicon dioxide with a thickness ratio of 3:1 and a thickness of 2μm-5μm, which has moisture-proof and corrosion-proof properties.
[0014] The beneficial effects of this utility model are as follows:
[0015] 1. Through the gradient stacking of five functional layers, significant improvements in miniaturization, high-frequency performance, and high-temperature stability of the capacitor are achieved. A capacitance of 11.5 μF is achieved in an ultra-thin form factor, with a capacitance density of 71.9 nF / mm³. Simultaneously, the capacitance change rate is ≤±3% within a temperature range of -55℃ to +150℃. The low-loss core layer and stress-buffered transition layer work synergistically to reduce the equivalent series resistance (ESR) to 4.2 mΩ at 1 MHz and increase the self-resonant frequency (SRF) to 1.3 GHz. The dielectric constant retention rate is ≥95% at 200℃. The mechanical reinforcement layer and surface passivation protection layer, through 300 GPa elastic modulus silicon nitride fiber and a 30 W / (m·K) thermal conductivity Al₂O₃ / SiO₂ composite coating, extend the thermal cycling fatigue life to 1.5 × 10⁻⁶. 4 This significantly improves the performance of the capacitor in terms of high frequency and lifespan.
[0016] 2. The flexible encapsulation shell and "Z"-shaped leads enhance the vibration resistance and mechanical reliability of this capacitor. The flexible encapsulation shell, integrally cured from liquid silicone rubber, utilizes an inner annular groove for interference fit with the body, along with the "Z"-shaped bent leads with ball contacts at the ends. This significantly improves the vibration resistance compared to traditional capacitors. The encapsulation structure of the flexible encapsulation shell and ceramic body has passed the GB / T 42277-2022 mechanical shock test, ensuring the long-term stability of the capacitor in high-vibration environments. Attached Figure Description
[0017] Figure 1 This is a perspective view of the present invention.
[0018] Figure 2 This is a cross-sectional view of the present invention.
[0019] Figure 3 This is a perspective view of the main body of this utility model.
[0020] Explanation of icon numbers:
[0021] 1-Body, 10-High dielectric constant gradient layer, 11-Stress buffer transition layer, 12-Low loss core layer, 13-Mechanical reinforcement layer, 14-Surface passivation protection layer, 2-Flexible packaging shell, 20-Groove, 3-Pin, 30-Positive pin, 31-Negative pin, 32-Spherical contact, 4-Electrolyte layer. Detailed Implementation
[0022] The present invention will be further described below with reference to the accompanying drawings:
[0023] like Figure 1-3As shown, this utility model relates to a miniaturized surface mount capacitor, including a body 1, a flexible encapsulation shell 2, and leads 3. The leads 3 include a positive lead 30 and a negative lead 31. The body 1 includes a high dielectric constant gradient layer 10, a stress buffer transition layer 11, a low-loss core layer 12, a mechanical reinforcement layer 13, and a surface passivation protection layer 14. The body 1 is formed by sequentially stacking the high dielectric constant gradient layer 10, the stress buffer transition layer 11, the low-loss core layer 12, the mechanical reinforcement layer 13, and the surface passivation protection layer 14. At least one body 1 is encapsulated within the flexible encapsulation shell 2. The body 1 is electrically connected to an electrolyte layer 4. In this embodiment, another body 1 is provided on the opposite side of the electrolyte layer 4. The stress buffer transition layer 11 is used to alleviate the thermal expansion mismatch between the high dielectric layer and the core layer, and improve the thermal cycling fatigue life. The low-loss core layer 12 has low dielectric loss and high temperature stability. The mechanical reinforcement layer 13 is used to improve the rigidity of the body 1, inhibit crack propagation and improve vibration resistance. The surface passivation protective layer 14 has moisture-proof and corrosion-proof properties. The flexible packaging shell 2 is integrally cured and molded from liquid silicone rubber. The pin 3 is a "Z"-shaped bend with a ball contact 32 at the end. One end of the positive electrode pin 30 is electrically connected to the high dielectric constant gradient layer 10, and one end of the negative electrode pin 31 is connected to the electrolyte layer 4. The inner wall of the flexible packaging shell 2 has an annular groove 20, which is interference-fitted with the body 1 and extends the pin 3 from the bottom. The spherical contact 32 at the end of pin 3 has a diameter of 0.15mm-0.25mm. After being embedded in the circuit board pad holes, it is connected by conductive adhesive. The high dielectric constant gradient layer 10 reduces the electric field concentration effect, making the capacitance change rate at the operating temperature ≤±3%. When power is connected to the circuit and a voltage difference appears across the capacitor, the miniaturized chip capacitor begins to charge. The power supply causes the charge to move directionally from the electrolyte layer 4 to the low-loss core layer 12. When passing through the stress buffer transition layer 11, the stress buffer transition layer 11 is constructed with a porous structure through nanoimprinting or sol-gel processes. The porous structure only allows electrons to pass through the stress buffer transition layer 11, and they cannot migrate freely between layers. Under the action of the dielectric constant gradient layer 10, the electric field concentration effect is reduced, allowing the charge to move from the high dielectric constant gradient layer 10 through the stress buffer transition layer 11 to the low-loss core layer 12, and be more evenly distributed in the low-loss core layer 12. This effectively reduces energy loss during charging. As the charge accumulates, an electric field opposite to the power supply voltage is established between the two poles of the body 1. When the voltage across the capacitor is equal to the power supply voltage, charging is complete. During discharging, the charge stored in the capacitor forms a current to the external circuit through the pin 3, thereby achieving efficient conversion between electrical energy and electric field energy. This meets the requirements of miniaturization and high performance of electronic devices, and its lifespan prediction value is high during long-term use, reducing maintenance costs and replacement frequency.
[0024] Further, in one preferred embodiment of the body 1, the high dielectric constant gradient layer 10 has a thickness of 10 μm, a dielectric constant of 3000, a temperature range of -55°C, an elastic modulus of 120 GPa, and a coefficient of thermal expansion of 6.5 ppm / °C; the stress buffer transition layer 11 has a thickness of 5 μm, a dielectric constant of 1500, a temperature range of +85°C, an elastic modulus of 90 GPa, and a coefficient of thermal expansion of 5.0 ppm / °C; and the low-loss core layer 12 has a thickness of 50 μm, a dielectric constant of 2000, a temperature range of +125°C, an elastic modulus of 180 GPa, and a coefficient of thermal expansion of 3.0 ppm / °C. The mechanical reinforcement layer 13 has a thickness of 20 μm, a dielectric constant of 800, a temperature of +200℃, an elastic modulus of 250 GPa, and a coefficient of thermal expansion of 2.5 ppm / ℃; the surface passivation protective layer 14 has a thickness of 2 μm, a dielectric constant of 10, an elastic modulus of 350 GPa, and a coefficient of thermal expansion of 1.0 ppm / ℃; the capacitance of the body 1 was measured to be 8.5 μF, and the capacitance density per unit volume was 53.1 nF / mm³; at 1 MHz, the equivalent series resistance (ESR) was 5.5 mΩ, the self-resonant frequency (SRF) was 1.0 GHz, and it passed the GB / T 42277-2022 test (impact acceleration 1500g, pulse width 0.3 ms). Under the conditions of 125℃ and rated voltage, the lifetime measurement reached 8 × 10³ hours.
[0025] Further, in a preferred second embodiment of the body 1, the high dielectric constant gradient layer 10 has a thickness of 15 μm, a dielectric constant of 4000, a temperature range of +15°C, an elastic modulus of 135 GPa, and a coefficient of thermal expansion of 7.0 ppm / °C; the stress buffer transition layer 11 has a thickness of 10 μm, a dielectric constant of 1750, a temperature range of +105°C, an elastic modulus of 100 GPa, and a coefficient of thermal expansion of 4.5 ppm / °C; and the low-loss core layer 12 has a thickness of 65 μm, a dielectric constant of 2500, a temperature range of +160°C, an elastic modulus of 200 GPa, and a coefficient of thermal expansion of 3.5 ppm / °C. The mechanical reinforcement layer 13 has a thickness of 25 μm, a dielectric constant of 1000, an elastic modulus of 275 GPa, and a coefficient of thermal expansion of 3.0 ppm / ℃ at +250℃. The surface passivation layer 14 has a thickness of 3.5 μm, a dielectric constant of 15, an elastic modulus of 375 GPa, and a coefficient of thermal expansion of 1.5 ppm / ℃. The measured capacitance of the body 1 is 9.5 μF, and the capacitance density per unit volume is 59.4 nF / mm³. At 1 MHz, the equivalent series resistance (ESR) is 4.8 mΩ, the self-resonant frequency (SRF) is 1.2 GHz, and it passes the test of GB / T 42277-2022. Under the conditions of 125℃ and rated voltage, the lifetime measurement reaches 1.2 × 10⁻⁶. 4 Hour.
[0026] Further, in a preferred third embodiment of the body 1, the high dielectric constant gradient layer 10 has a thickness of 20 μm, a dielectric constant of 5000, a temperature range of +85°C, an elastic modulus of 150 GPa, and a coefficient of thermal expansion of 7.5 ppm / °C; the stress buffer transition layer 11 has a thickness of 15 μm, a dielectric constant of 2000, a temperature range of +125°C, an elastic modulus of 110 GPa, and a coefficient of thermal expansion of 4.0 ppm / °C; and the low-loss core layer 12 has a thickness of 80 μm, a dielectric constant of 3000, a temperature range of +200°C, and an elastic modulus of 150 GPa, and a coefficient of thermal expansion of 7.5 ppm / °C. The dielectric modulus is 220 GPa, and the coefficient of thermal expansion is 4.0 ppm / ℃. The mechanical reinforcement layer 13 has a thickness of 30 μm, a dielectric constant of 1200, an elastic modulus of 300 GPa, and a coefficient of thermal expansion of 3.5 ppm / ℃ at +300℃. The surface passivation protective layer 14 has a thickness of 5 μm, a dielectric constant of 20, an elastic modulus of 400 GPa, and a coefficient of thermal expansion of 2.0 ppm / ℃. The measured capacitance of the body 1 is 11.5 μF, and the capacitance density per unit volume is 71.9 nF / mm³. The ESR is 4.2 mΩ, the SRF is 1.3 GHz, and it has passed more stringent mechanical shock tests, achieving a lifetime of 1.5 × 10⁻⁶. 4 Hour.
[0027] The above description is only a preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Therefore, without departing from the design spirit of the present utility model, any equivalent changes or modifications made by those skilled in the art to the structure, features and principles of the present utility model should fall within the protection scope of the patent application of the present utility model.
Claims
1. A miniaturized chip capacitor comprising a body, a flexible encapsulation housing and a pin, characterized in that: The body comprises a high dielectric constant gradient layer, a stress buffer transition layer, a low-loss core layer, a mechanical reinforcement layer, and a surface passivation protection layer. The body is formed by sequentially stacking the high dielectric constant gradient layer, the stress buffer transition layer, the low-loss core layer, the mechanical reinforcement layer, and the surface passivation protection layer. At least one of the bodies is encapsulated within the flexible packaging shell. The body is electrically connected to an electrolyte layer. The flexible packaging shell is integrally cured from liquid silicone rubber, and the pin is a "Z"-shaped bend with a spherical contact at the end.
2. A miniaturized chip capacitor according to claim 1, characterized in that: The flexible packaging shell has an annular groove on its inner wall, which is interference-fitted with the body, and leads extend from the bottom.
3. A miniaturized chip capacitor according to claim 1, characterized in that: The spherical contact at the end of the pin has a diameter of 0.15mm-0.25mm, and is connected by being embedded in the circuit board pad hole and cured with conductive adhesive.
4. A miniaturized chip capacitor according to claim 1, characterized in that: The high dielectric constant gradient layer is a lanthanum-niobium modified barium zirconate titanate-based ceramic with a thickness of 10μm-20μm and a dielectric constant of 3000-5000εr. By reducing the electric field concentration effect, the capacitance change rate at the operating temperature of the capacitor is ≤±3%.
5. A miniaturized chip capacitor according to claim 1, characterized in that: The stress buffer transition layer is a manganese-niobate-lead magnesium titanate-lead titanate based relaxor ferroelectric ceramic with a thickness of 5μm-15μm and a dielectric constant of 1500-2000εr, used to alleviate the thermal expansion mismatch between the high dielectric layer and the core layer and improve the thermal cycling fatigue life.
6. A miniaturized chip capacitor according to claim 1, characterized in that: The low-loss core layer, samarium-zinc titanate barium-based ceramic, has a thickness of 50μm-80μm and a dielectric constant of 2000-3000εr. As the main energy storage layer, it has low dielectric loss and high-temperature stability.
7. A miniaturized chip capacitor according to claim 1, characterized in that: The mechanical reinforcement layer is made of yttrium oxide-silicon nitride ceramic with a thickness of 20μm-30μm and a dielectric constant of 800-1200εr, which is used to improve the rigidity of the body, suppress crack propagation, and improve vibration resistance.
8. A miniaturized chip capacitor according to claim 1, characterized in that: The surface passivation protective layer is a composite coating of aluminum oxide and silicon dioxide with a thickness ratio of 3:1 and a thickness of 2μm-5μm, which has moisture-proof and corrosion-proof properties.