Time sequence circuit for acoustic logging instrument

Abstract

The utility model discloses a time sequence circuit for acoustic logging instrument, including quartz crystal oscillator and frequency divider unit, quartz crystal oscillator includes quartz crystal Y1 and NAND gate circuit U1, and frequency divider unit includes three 74LS74 digital frequency divider, is 74LS74 digital frequency divider U2, 74LS74 digital frequency divider U3, 74LS74 digital frequency divider U4 respectively. The utility model discloses quartz crystal oscillator, high precision, good stability, long life, utilize 74LS74 double D flip-flop and constitute digital frequency divider, and the CLK is divided into several time sequence signals, and the power loss and distortion, flexibility and high accuracy are reduced.

Description

Technical Field

[0001] This utility model belongs to the field of acoustic logging tool technology, specifically relating to a timing circuit for an acoustic logging tool. Background Technology

[0002] like Figure 1 The acoustic logging tool shown often encounters the following problems during high-resolution acoustic repair:

[0003] 1) One of the four channels of received acoustic time difference signals is malfunctioning;

[0004] 2) In actual circuit testing and repair, timing waveforms are disordered;

[0005] 3) The selection channel is malfunctioning.

[0006] Based on practical repair experience and principle deduction, the three common faults mentioned above can be located in the four-in-one unit circuit of synchronization signal, squelch gate, sound wave gating, and insertion circuit. Among them, sound wave signal gating is the core of this unit circuit. That is to say, the received sound wave signals do not enter these processing circuits at the same time. Instead, the time difference for entering the processing circuit is set according to the distance between the sources, so that the four received sound wave signals enter in sequence, control the field effect transistor to conduct, and thus complete the segmented processing of the time difference signal by the hardware circuit.

[0007] When the timing circuit malfunctions, the controlled signals of the circuits controlling the four receiving signals cannot sequentially complete their opening and closing states according to the pre-designed time. This results in the incoming acoustic signals not being acquired in strict chronological order, leading to disordered acoustic and electrical signals within the specified time. If a receiving unit malfunctions, the waveform of that receiving unit will exhibit abnormalities. Existing technical solutions use RC delay and gating to select the initial CLK signal. This traditional RC circuit is simple in structure and readily available in raw materials. However, under temperature changes, the resistance R fluctuates significantly, easily causing frequency shifts. This results in a certain degree of deviation between the signal gating and delay and the theoretical design value, leading to deviations in the time difference signal.

[0008] Chinese utility model patent (authorization announcement number CN 202132037 U) discloses an acoustic logic circuit for an acoustic logging tool, including a CPL programmable circuit. The input terminal of the CPL programmable circuit is connected to a control command circuit, a clock circuit, and a synchronization signal circuit. The output terminal of the CPL programmable circuit is connected to a transmit pulse drive circuit and a receive line.

[0009] Chinese utility model patent (authorization announcement number CN214035639U) discloses a detection device for a sonic logging tool based on a USB acquisition card, including a PC, a USB acquisition card, a microcontroller, a synchronization signal detection circuit, and a signal separation and filtering circuit. The PC is connected to the USB acquisition card, which is connected to the microcontroller, the synchronization signal detection circuit, and the signal separation and filtering circuit. The microcontroller is connected to the synchronization signal detection circuit and the signal separation and filtering circuit, which are connected to the sonic logging tool to be detected.

[0010] Both of the aforementioned patents have technical defects that cause the signal gating and delay to deviate to a certain extent from the theoretical design value, thus resulting in time difference signal deviation. Summary of the Invention

[0011] The purpose of this invention is to solve the above-mentioned technical problems and provide a timing circuit for an acoustic logging tool that has good stability and reduces power loss and distortion.

[0012] To achieve the above objectives, this utility model provides a timing circuit for an acoustic logging tool, including a quartz crystal oscillator and a frequency divider unit. The quartz crystal oscillator includes a quartz crystal Y1 and a NAND gate circuit U1. The frequency divider unit includes three 74LS74 digital frequency dividers, namely 74LS74 digital frequency divider U2, 74LS74 digital frequency divider U3, and 74LS74 digital frequency divider U4.

[0013] Furthermore, each of the 74LS74 digital frequency dividers is a dual D flip-flop. The 74LS74 digital frequency divider U2 includes U2A and U2B, the 74LS74 digital frequency divider U3 includes U3A and U3B, and the 74LS74 digital frequency divider U4 includes U4A and U4B.

[0014] Furthermore, the data input terminal D and the data output terminal Q of the U2A are connected, and the quartz crystal oscillator is connected to the clock signal input terminal CLK of the U2A; the inverting data output terminal of the U2A... Connect the clock signal input terminal CLK of U2B, connect the data input terminal D and the data output terminal Q of U2B, and connect the inverting data output terminal of U2B. Connect to the clock signal input terminal CLK of U3A.

[0015] Furthermore, the data input terminal D of the U3A is connected to the data output terminal Q of the U3A, and the inverting data output terminal of the U3A is connected. Connect the clock signal input terminal CLK of U3B, connect the data input terminal D and the data output terminal Q of U3B, and connect the inverting data output terminal of U3B. Connect to the clock signal input terminal CLK of U4A.

[0016] Furthermore, the data input terminal D and the data output terminal Q of the U4A are connected, and the inverting data output terminal of the U4A is... Connect the clock signal input terminal CLK of U4B, and connect the data input terminal D and the data output terminal Q of U4B.

[0017] Furthermore, the quartz crystal Y1 is connected in parallel with a resistor R1.

[0018] Furthermore, the two ends of the quartz crystal Y1 are grounded via capacitor C1 and capacitor C2, respectively.

[0019] Furthermore, the NAND gate circuit U1 uses a 74LS37 chip.

[0020] Compared with the prior art, the beneficial effects of this utility model are as follows: This utility model adopts a quartz crystal oscillator, which has high precision, good stability and long life; it uses a 74LS74 dual D flip-flop to form a digital frequency divider, which divides CLK into several timing signals, reducing power loss and distortion, and providing high flexibility and accuracy. Attached Figure Description

[0021] Figure 1 The background diagram shows the circuit diagram of an acoustic logging tool.

[0022] Figure 2 This is the timing circuit diagram for the wave logging tool of this utility model. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 2 The timing circuit for the acoustic logging tool shown includes a quartz crystal oscillator and a frequency divider unit. The quartz crystal oscillator consists of a quartz crystal Y1 and a NAND gate circuit U1, providing a stable and accurate clock signal. The quartz crystal Y1 is connected in parallel with a resistor R1, and its two ends are grounded via capacitors C1 and C2 respectively. The resistor R1 and capacitors C1 and C2 form a temperature compensation circuit, which can effectively suppress frequency shift caused by changes in ambient temperature. The NAND gate circuit U1 uses a 74LS37 chip.

[0025] The frequency divider unit includes three 74LS74 digital frequency dividers: 74LS74 digital frequency divider U2, 74LS74 digital frequency divider U3, and 74LS74 digital frequency divider U4. Each 74LS74 digital frequency divider is a dual D flip-flop and consists of two modules with the same function. Specifically, 74LS74 digital frequency divider U2 includes U2A and U2B, 74LS74 digital frequency divider U3 includes U3A and U3B, and 74LS74 digital frequency divider U4 includes U4A and U4B.

[0026] The data input terminal D and the data output terminal Q of U2A are connected. The quartz crystal oscillator is connected to the clock signal input terminal CLK of U2A to complete the second frequency division of the input signal; the inverting data output terminal of U2A... Connect the clock signal input terminal CLK of U2B, connect the data input terminal D and the data output terminal Q of U2B, and connect the inverting data output terminal of U2B. Connect the clock signal input terminal CLK of U3A; similarly, connect the data input terminal D and the data output terminal Q of U3A, and connect the inverting data output terminal of U3A. Connect the clock signal input terminal CLK of U3B, connect the data input terminal D and the data output terminal Q of U3B, and connect the inverting data output terminal of U3B. Connect the clock signal input terminal CLK of U4A; connect the data input terminal D and the data output terminal Q of U4A; and connect the inverting data output terminal of U4A. Connect the clock signal input terminal CLK of U4B, and connect the data input terminal D and the data output terminal Q of U4B.

[0027] The clock signal input terminal CLK of U2A is connected to a quartz crystal oscillator to complete the first secondary frequency division of the input signal, which is then output through the inverting data terminal of U2A. Half of the original signal frequency is output to the clock signal input terminal CLK of U2B to complete the second frequency division, which is the inverted data output terminal of U2B. Output one-quarter of the original signal frequency; and so on:

[0028] U3A's inverting data output terminal The output frequency is one-eighth of the original signal frequency.

[0029] U3B's inverted data output terminal The output frequency is one-sixteenth of the original signal frequency.

[0030] U4A's inverting data output terminal The output frequency is one thirty-second of the original signal frequency.

[0031] U4B's inverted data output terminal The output frequency is one-sixtieth of the original signal frequency.

[0032] This invention uses a quartz crystal oscillator, which has high precision, good stability and long life; it uses a 74LS74 dual D flip-flop to form a digital frequency divider, which divides CLK into several timing signals, reducing power loss and distortion, and providing high flexibility and accuracy.

[0033] This invention relates to a timing circuit for a sonic logging tool. It abandons the traditional analog RC circuit for signal selection and delay, instead employing a quartz crystal oscillator circuit and digital frequency division technology. This improves design flexibility and expands detection performance. Before actual manufacturing and debugging, the circuit was tested using two common circuit simulation software programs, Multisim 14.0 and Proteus. The results showed that the digital frequency division signal generated by the improved circuit unit has advantages such as low background noise, accurate frequency division, controllable oscillation frequency, and high precision. Furthermore, even under high-temperature conditions at the bottom of the well, after changes in the instrument's internal temperature and software simulation of temperature drift, the device's parameter performance, stability, and temperature compensation all reached the expected ideal state. This achieves modular design and targeted replacement. After multiple tests and comparisons following the prototype's release, the design demonstrated stable and reliable performance and successfully replaced some downhole sonic logging tools.

Claims

1. A timing circuit for an acoustic logging tool, characterized in that: It includes a quartz crystal oscillator and a frequency divider unit. The quartz crystal oscillator includes a quartz crystal Y1 and a NAND gate circuit U1. The frequency divider unit includes three 74LS74 digital frequency dividers, namely 74LS74 digital frequency divider U2, 74LS74 digital frequency divider U3 and 74LS74 digital frequency divider U4. Each of the 74LS74 digital frequency dividers is a dual D flip-flop. The 74LS74 digital frequency divider U2 includes U2A and U2B, the 74LS74 digital frequency divider U3 includes U3A and U3B, and the 74LS74 digital frequency divider U4 includes U4A and U4B. The data input terminal D and the data output terminal Q of the U2A are connected, and the quartz crystal oscillator is connected to the clock signal input terminal CLK of the U2A; the inverted data output terminal of the U2A... Connect the clock signal input terminal CLK of U2B, connect the data input terminal D and the data output terminal Q of U2B, and connect the inverting data output terminal of U2B. Connect to the clock signal input terminal CLK of U3A.

2. The timing circuit for the acoustic logging tool according to claim 1, characterized in that: The data input terminal D and the data output terminal Q of the U3A are connected, and the inverting data output terminal of the U3A is connected. Connect the clock signal input terminal CLK of U3B, connect the data input terminal D and the data output terminal Q of U3B, and connect the inverting data output terminal of U3B. Connect to the clock signal input terminal CLK of U4A.

3. The timing circuit for the acoustic logging tool according to claim 1, characterized in that: The data input terminal D and the data output terminal Q of the U4A are connected, and the inverting data output terminal of the U4A is connected. Connect the clock signal input terminal CLK of U4B, and connect the data input terminal D and the data output terminal Q of U4B.

4. The timing circuit for the acoustic logging tool according to claim 1, characterized in that: The quartz crystal Y1 is connected in parallel with resistor R1.

5. The timing circuit for the acoustic logging tool according to claim 1, characterized in that: The two ends of the quartz crystal Y1 are grounded through capacitors C1 and C2, respectively.

6. The timing circuit for the acoustic logging tool according to claim 1, characterized in that: The NAND gate circuit U1 uses a 74LS37 chip.

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