An image processing circuit for autonomous vehicles

Abstract

This invention discloses an image processing circuit for autonomous vehicles, belonging to the field of image processing technology. It solves the problems of unexpected refraction and scattering of light due to physical defects in optical microlenses and color filters, and charge coupling caused by parasitic capacitance in pixel units, leading to leakage of optical / electrical signals from a single pixel to adjacent pixels, resulting in color aliasing and blurred image edges. The circuit includes a main image sensor module, a reference image sensor module, and an analog signal preprocessing and multiplexing module. This invention coordinates the synchronous signal acquisition of the main and reference image sensors through a low-jitter clock distribution module. After integration by the analog signal preprocessing module, a dynamic crosstalk compensation module generates an inverse compensation signal based on the reference signal. A high-precision differential correlation dual sampling module then performs noise suppression and crosstalk elimination on the main signal. Finally, a programmable gain amplifier module outputs the purified differential signal.

Description

Technical Field

[0001] This utility model relates to the field of image processing technology, and in particular to an image processing circuit for unmanned vehicles. Background Technology

[0002] The conventional image processing circuit of an autonomous vehicle is a complex system that integrates photoelectric conversion, analog signal processing, digital conversion and high-speed transmission to convert optical images into digital signals with high fidelity.

[0003] The image processing circuit of a conventional autonomous vehicle begins with the CMOS image sensor module, where pixel units generate voltage signals through photoelectric conversion and output them; the analog front-end processing circuit uses correlated double sampling noise suppression and programmable gain amplifier amplitude modulation; the analog-to-digital conversion module adopts a parallel architecture, equipped with a single-slope or successive approximation ADC; the clock management module relies on a phase-locked loop to provide a low-jitter master clock to ensure timing synchronization; the power management module has multiple power supplies and uses LDOs, switching power supplies, and filter networks for noise suppression; signal transmission is achieved through LVDS differential signals and impedance matching; it also includes a temperature sensor and a bias voltage generation circuit to acquire high-quality image data in complex electromagnetic environments.

[0004] However, in the actual operation of the image processing circuit of autonomous vehicles, due to physical defects in the optical microlenses and color filters, the incident light is refracted and scattered unexpectedly. At the same time, due to the inherent parasitic capacitance between pixel units, the charge signal is coupled through the semiconductor substrate. These reasons cause the light or electrical signal that should be sensed by a single pixel to leak to adjacent pixels, resulting in problems such as color mixing and blurred image edges. Specifically, abnormal color spots appear in pure color areas and the object outline is diffused and distorted.

[0005] This directly reduces the color reproduction accuracy and spatial resolution of image sensors, severely interfering with the autonomous driving system's ability to accurately identify traffic light colors, perceive the shape features of vehicles ahead, and the clear edges of lane lines, thus significantly increasing the risk of misjudgment in environmental perception.

[0006] Therefore, an image processing circuit for autonomous vehicles is proposed to solve or alleviate the above problems. Utility Model Content

[0007] The purpose of this invention is to address the shortcomings of existing technologies by proposing an image processing circuit for autonomous vehicles.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] An image processing circuit for an autonomous vehicle includes a main image sensor module, a reference image sensor module, an analog signal preprocessing and multiplexing module, a dynamic crosstalk compensation analog calculation module, a high-precision differential correlation dual sampling module, a programmable gain amplifier and driver module, an ultra-low noise precision reference voltage source module, and a low-jitter clock distribution and synchronization module. The eight analog signal outputs of the main image sensor module are respectively connected to the eight main signal inputs of the analog signal preprocessing and multiplexing module. The eight analog signal outputs of the reference image sensor module are respectively connected to the eight reference signal inputs of the analog signal preprocessing and multiplexing module. The first analog signal output of the reference image sensor module is directly connected to the reference signal input of the dynamic crosstalk compensation analog calculation module. The main clock output of the low-jitter clock distribution and synchronization module is simultaneously connected to the clock signal inputs of both the main image sensor module and the reference image sensor module. The three address signal outputs of the low-jitter clock distribution and synchronization module are connected to the analog signal preprocessing and multiplexing module. The three address signal input terminals are connected to the main signal input terminal of the dynamic crosstalk compensation analog calculation module, the compensation signal output terminal of the dynamic crosstalk compensation analog calculation module is connected to the compensation signal input terminal of the high-precision differential correlation dual sampling module, the positive and negative input terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module are respectively connected to the positive and negative input terminals of the differential signal input terminal of the high-precision differential correlation dual sampling module, the sampling clock output terminal of the low jitter clock distribution and synchronization module is connected to the sampling clock input terminal of the high-precision differential correlation dual sampling module, the positive and negative input terminals of the differential signal output terminal of the high-precision differential correlation dual sampling module are connected to the positive and negative input terminals of the differential signal input terminal of the programmable gain amplifier module, the reference voltage output terminal of the ultra-low noise precision reference voltage source module is connected to the reference voltage input terminal of the high-precision differential correlation dual sampling module, and the positive and negative input terminals of the differential signal output terminal of the programmable gain amplifier module serve as the signal output terminals of the entire image processing circuit.

[0010] Preferably, the main image sensor module includes a first CMOS image sensor chip. The positive terminal of the analog power supply of the first CMOS image sensor chip is connected to analog ground through a first decoupling capacitor. The positive terminal of the digital power supply of the first CMOS image sensor chip is connected to digital ground through a second decoupling capacitor. The analog ground terminal of the first CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the first CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the first CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module. The eight analog signal output terminals of the first CMOS image sensor chip are respectively connected to the eight main signal input terminals of the analog signal preprocessing and multiplexing module through eight series matching resistors.

[0011] Preferably, the reference image sensor module includes a second CMOS image sensor chip. The positive terminal of the analog power supply of the second CMOS image sensor chip is connected to analog ground through a third decoupling capacitor. The positive terminal of the digital power supply of the second CMOS image sensor chip is connected to digital ground through a fourth decoupling capacitor. The analog ground terminal of the second CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the second CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the second CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module. The surface of the optical photosensitive area of ​​the second CMOS image sensor chip is covered with a gray filter. The first analog signal output terminal of the second CMOS image sensor chip is connected to the reference signal input terminal of the dynamic crosstalk compensation analog calculation module through a matching resistor.

[0012] Preferably, the analog signal preprocessing and multiplexing module includes a first analog switch chip ADG1206, a second analog switch chip ADG1206, an RC low-pass filter, a first operational amplifier ADA4817, and a differential amplifier THS4551. The eight signal input terminals of the first analog switch chip ADG1206 are configured as the eight main signal input terminals of the analog signal preprocessing and multiplexing module. The eight signal input terminals of the second analog switch chip ADG1206 are configured as the eight reference signal input terminals of the analog signal preprocessing and multiplexing module. The three address signal input terminals of the two analog switch chips ADG1206 are connected in parallel and configured as the three address signal input terminals of the analog signal preprocessing and multiplexing module. The signal output terminal of the switching chip ADG1206 is connected to the non-inverting input terminal of the first operational amplifier ADA4817 after passing through an RC low-pass filter. The signal output terminal of the first operational amplifier ADA4817 is set as the multiplexed signal output terminal of the analog signal preprocessing and multiplexing module. The feedback terminal of the first operational amplifier ADA4817 is connected to its inverting input terminal through a feedback resistor. The other signal output terminals of the first analog switching chip ADG1206 and the second analog switching chip ADG1206 are converted into differential signals by the differential amplifier THS4551. The non-inverting output terminal and the inverting output terminal of the differential amplifier THS4551 are set as the non-inverting and inverting terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module.

[0013] Preferably, the dynamic crosstalk compensation analog calculation module includes a second operational amplifier ADA4817, a digital potentiometer, and an analog multiplier AD633. The non-inverting input of the second operational amplifier ADA4817 is set as the main signal input of the dynamic crosstalk compensation analog calculation module, and the signal output of the second operational amplifier ADA4817 is connected to the inverting input through a feedback resistor. The serial data terminal and serial clock terminal of the digital potentiometer are set as the control interface of the dynamic crosstalk compensation analog calculation module. The first signal input of the analog multiplier AD633 is connected to the signal output of the second operational amplifier ADA4817, the second signal input of the analog multiplier AD633 is set as the reference signal input of the dynamic crosstalk compensation analog calculation module, and the signal output of the analog multiplier AD633 is set as the compensation signal output of the dynamic crosstalk compensation analog calculation module after being amplified by an adjustable gain amplifier.

[0014] Preferably, the high-precision differential correlation dual sampling module includes a fully differential operational amplifier THS4531, a sample-and-hold capacitor network, and a compensation signal injection circuit. The non-inverting and inverting input terminals of the fully differential operational amplifier THS4531 are configured as the non-inverting and inverting input terminals of the differential signal input terminal of the high-precision differential correlation dual sampling module. The compensation signal injection circuit includes a third operational amplifier ADA4817. The non-inverting input terminal of the third operational amplifier ADA4817 is configured as the compensation signal input terminal of the high-precision differential correlation dual sampling module. The signal output terminal of the third operational amplifier ADA4817 is connected to the inverting input terminal of the fully differential operational amplifier THS4531 through an injection resistor. The sample-and-hold capacitor network includes four... Four precision capacitors are connected between the input and output terminals of the fully differential operational amplifier THS4531, respectively. The non-inverting and inverting output terminals of the fully differential operational amplifier THS4531 are configured as the non-inverting and inverting terminals of the differential signal output terminals of the high-precision differential correlation dual sampling module. The reference voltage input terminal of the high-precision differential correlation dual sampling module provides a common-mode voltage to the fully differential operational amplifier THS4531 through a voltage divider resistor network. The voltage divider resistor network includes a first voltage divider resistor and a second voltage divider resistor connected in series. One end of the first voltage divider resistor is energized, and one end of the second voltage divider resistor is grounded. The connection node between the first voltage divider resistor and the second voltage divider resistor is connected to the fully differential operational amplifier THS4531.

[0015] Preferably, the programmable gain amplifier and driver module includes a programmable gain amplifier LTC6912 and an output driver circuit. The non-inverting and inverting input terminals of the programmable gain amplifier LTC6912 are configured as the non-inverting and inverting input terminals of the differential signal input terminal of the programmable gain amplifier module. The three gain control terminals of the programmable gain amplifier LTC6912 are used to receive external gain control signals. The output driver circuit includes a fourth operational amplifier ADA4817 and a fifth operational amplifier ADA4817. The non-inverting input terminal of the fourth operational amplifier ADA4817 is connected to the non-inverting output terminal of the programmable gain amplifier LTC6912, and the non-inverting input terminal of the fifth operational amplifier ADA4817 is connected to the inverting output terminal of the programmable gain amplifier LTC6912. The output terminals of the fourth and fifth operational amplifiers ADA4817 are configured as the non-inverting and inverting input terminals of the differential signal output terminal of the programmable gain amplifier module.

[0016] Preferably, the ultra-low noise precision reference voltage source module includes a reference voltage source ADR4540, and the voltage output terminal of the reference voltage source ADR4540 is set as the reference voltage output terminal of the ultra-low noise precision reference voltage source module after passing through a π-type filter.

[0017] Preferably, the low-jitter clock distribution and synchronization module includes a clock generator Si5332. The main clock output of the clock generator Si5332 is configured as the main clock output of the low-jitter clock distribution and synchronization module after passing through a clock buffer SiT92211. The three address outputs of the clock generator Si5332 are configured as the three address signal outputs of the low-jitter clock distribution and synchronization module after passing through a level converter Si5330. The auxiliary clock output of the clock generator Si5332 is configured as the sampling clock output of the low-jitter clock distribution and synchronization module after passing through a clock buffer SiT92211.

[0018] This utility model has the following beneficial effects:

[0019] This invention coordinates the synchronous acquisition of signals by the main image sensor module and the reference image sensor module through a low-jitter clock distribution and synchronization module. After analog signal preprocessing and integration by a multiplexing module, the dynamic crosstalk compensation analog calculation module generates an inverse compensation signal based on the reference signal. Then, the main signal is subjected to noise suppression and crosstalk elimination processing by a high-precision differential correlation dual sampling module with the reference support of an ultra-low noise precision reference voltage source module. Finally, the purified differential signal is output by a programmable gain amplifier module. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural block diagram of the present invention.

[0022] In the diagram: 1. Main image sensor module; 2. Reference image sensor module; 3. Analog signal preprocessing and multiplexing module; 4. Dynamic crosstalk compensation analog calculation module; 5. High-precision differential correlation dual sampling module; 6. Programmable gain amplifier and driver module; 7. Ultra-low noise precision reference voltage source module; 8. Low jitter clock distribution and synchronization module. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0027] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0028] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0029] An image processing circuit for an autonomous vehicle, such as Figure 1As shown, the system includes a main image sensor module 1, a reference image sensor module 2, an analog signal preprocessing and multiplexing module 3, a dynamic crosstalk compensation analog calculation module 4, a high-precision differential correlation dual sampling module 5, a programmable gain amplifier and driver module 6, an ultra-low noise precision reference voltage source module 7, and a low-jitter clock distribution and synchronization module 8. The eight analog signal outputs of the main image sensor module 1 are connected to the eight main signal inputs of the analog signal preprocessing and multiplexing module 3. The eight analog signal outputs of the reference image sensor module 2 are connected to the eight reference signal inputs of the analog signal preprocessing and multiplexing module 3. The first analog signal output of the reference image sensor module 2 is directly connected to the reference signal input of the dynamic crosstalk compensation analog calculation module 4. The main clock output of the low-jitter clock distribution and synchronization module 8 is connected to the clock signal inputs of both the main image sensor module 1 and the reference image sensor module 2. The three address signal outputs of the low-jitter clock distribution and synchronization module 8 are connected to the analog signal preprocessing and multiplexing module 3. The three address signal input terminals, the multiplexed signal output terminal of the analog signal preprocessing and multiplexing module 3 are connected to the main signal input terminal of the dynamic crosstalk compensation analog calculation module 4, the compensation signal output terminal of the dynamic crosstalk compensation analog calculation module 4 is connected to the compensation signal input terminal of the high-precision differential correlation dual sampling module 5, the positive and negative terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module 3 are respectively connected to the positive and negative terminals of the differential signal input terminal of the high-precision differential correlation dual sampling module 5, the sampling clock output terminal of the low jitter clock distribution and synchronization module 8 is connected to the sampling clock input terminal of the high-precision differential correlation dual sampling module 5, the positive and negative terminals of the differential signal output terminal of the high-precision differential correlation dual sampling module 5 are connected to the positive and negative terminals of the differential signal input terminal of the programmable gain amplifier module, the reference voltage output terminal of the ultra-low noise precision reference voltage source module 7 is connected to the reference voltage input terminal of the high-precision differential correlation dual sampling module 5, and the positive and negative terminals of the differential signal output terminal of the programmable gain amplifier module serve as the signal output terminals of the entire image processing circuit.

[0030] The main image sensor module 1 includes a first CMOS image sensor chip. The positive terminal of the analog power supply of the first CMOS image sensor chip is connected to analog ground through a first decoupling capacitor. The positive terminal of the digital power supply of the first CMOS image sensor chip is connected to digital ground through a second decoupling capacitor. The analog ground terminal of the first CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the first CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the first CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module 8. The eight analog signal output terminals of the first CMOS image sensor chip are respectively connected to the eight main signal input terminals of the analog signal preprocessing and multiplexing module 3 through eight series matching resistors.

[0031] The reference image sensor module 2 includes a second CMOS image sensor chip. The positive terminal of the analog power supply of the second CMOS image sensor chip is connected to analog ground through a third decoupling capacitor. The positive terminal of the digital power supply of the second CMOS image sensor chip is connected to digital ground through a fourth decoupling capacitor. The analog ground terminal of the second CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the second CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the second CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module 8. The surface of the optical photosensitive area of ​​the second CMOS image sensor chip is covered with a gray filter. The first analog signal output terminal of the second CMOS image sensor chip is connected to the reference signal input terminal of the dynamic crosstalk compensation analog calculation module 4 through a matching resistor.

[0032] The analog signal preprocessing and multiplexing module 3 includes a first analog switch chip ADG1206, a second analog switch chip ADG1206, an RC low-pass filter, a first operational amplifier ADA4817, and a differential amplifier THS4551. The eight signal input terminals of the first analog switch chip ADG1206 are configured as the eight main signal input terminals of the analog signal preprocessing and multiplexing module 3. The eight signal input terminals of the second analog switch chip ADG1206 are configured as the eight reference signal input terminals of the analog signal preprocessing and multiplexing module 3. The three address signal input terminals of the two analog switch chips ADG1206 are connected in parallel and configured as the three address signal input terminals of the analog signal preprocessing and multiplexing module 3. The signal output terminal of the ADG1206 chip is connected to the non-inverting input terminal of the first operational amplifier ADA4817 after passing through an RC low-pass filter. The signal output terminal of the first operational amplifier ADA4817 is set as the multiplexed signal output terminal of the analog signal preprocessing and multiplexing module 3. The feedback terminal of the first operational amplifier ADA4817 is connected to its inverting input terminal through a feedback resistor. The other signal output terminals of the first analog switch chip ADG1206 and the second analog switch chip ADG1206 are converted into differential signals by the differential amplifier THS4551. The non-inverting output terminal and the inverting output terminal of the differential amplifier THS4551 are set as the non-inverting and inverting terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module 3.

[0033] The dynamic crosstalk compensation analog calculation module 4 includes a second operational amplifier ADA4817, a digital potentiometer, and an analog multiplier AD633. The non-inverting input of the second operational amplifier ADA4817 is set as the main signal input of the dynamic crosstalk compensation analog calculation module 4. The signal output of the second operational amplifier ADA4817 is connected to the inverting input through a feedback resistor. The serial data terminal and serial clock terminal of the digital potentiometer are set as the control interface of the dynamic crosstalk compensation analog calculation module 4. The first signal input of the analog multiplier AD633 is connected to the signal output of the second operational amplifier ADA4817. The second signal input of the analog multiplier AD633 is set as the reference signal input of the dynamic crosstalk compensation analog calculation module 4. The signal output of the analog multiplier AD633 is set as the compensation signal output of the dynamic crosstalk compensation analog calculation module 4 after passing through an adjustable gain amplifier.

[0034] The high-precision differential correlation dual sampling module 5 includes a fully differential operational amplifier THS4531, a sample-and-hold capacitor network, and a compensation signal injection circuit. The non-inverting and inverting inputs of the fully differential operational amplifier THS4531 are set as the non-inverting and inverting inputs of the differential signal of the high-precision differential correlation dual sampling module 5. The compensation signal injection circuit includes a third operational amplifier ADA4817. The non-inverting input of the third operational amplifier ADA4817 is set as the compensation signal input of the high-precision differential correlation dual sampling module 5. The signal output of the third operational amplifier ADA4817 is connected to the inverting input of the fully differential operational amplifier THS4531 through an injection resistor. The sample-and-hold capacitor network includes four... Four precision capacitors are connected between the input and output terminals of the fully differential operational amplifier THS4531. The non-inverting and inverting output terminals of the fully differential operational amplifier THS4531 are set as the non-inverting and inverting terminals of the differential signal output terminals of the high-precision differential correlation dual sampling module 5. The reference voltage input terminal of the high-precision differential correlation dual sampling module 5 provides a common-mode voltage to the fully differential operational amplifier THS4531 through a voltage divider resistor network. The voltage divider resistor network includes a first voltage divider resistor and a second voltage divider resistor connected in series. One end of the first voltage divider resistor is energized, and one end of the second voltage divider resistor is grounded. The connection node between the first voltage divider resistor and the second voltage divider resistor is connected to the fully differential operational amplifier THS4531.

[0035] The programmable gain amplifier and driver module 6 includes a programmable gain amplifier LTC6912 and an output driver circuit. The non-inverting and inverting input terminals of the programmable gain amplifier LTC6912 are set as the non-inverting and inverting input terminals of the differential signal input terminal of the programmable gain amplifier module. The three gain control terminals of the programmable gain amplifier LTC6912 are used to receive external gain control signals. The output driver circuit includes a fourth operational amplifier ADA4817 and a fifth operational amplifier ADA4817. The non-inverting input terminal of the fourth operational amplifier ADA4817 is connected to the non-inverting output terminal of the programmable gain amplifier LTC6912, and the non-inverting input terminal of the fifth operational amplifier ADA4817 is connected to the inverting output terminal of the programmable gain amplifier LTC6912. The output terminals of the fourth and fifth operational amplifiers ADA4817 are set as the non-inverting and inverting input terminals of the differential signal output terminal of the programmable gain amplifier module.

[0036] The ultra-low noise precision reference voltage source module 7 includes a reference voltage source ADR4540. The voltage output terminal of the reference voltage source ADR4540 is set as the reference voltage output terminal of the ultra-low noise precision reference voltage source module 7 after passing through a π-type filter.

[0037] The low-jitter clock distribution and synchronization module 8 includes a clock generator Si5332. The main clock output of the clock generator Si5332 is configured as the main clock output of the low-jitter clock distribution and synchronization module 8 after passing through a clock buffer SiT92211. The three address outputs of the clock generator Si5332 are configured as the three address signal outputs of the low-jitter clock distribution and synchronization module 8 after passing through a level converter Si5330. The auxiliary clock output of the clock generator Si5332 is configured as the sampling clock output of the low-jitter clock distribution and synchronization module 8 after passing through a clock buffer SiT92211.

[0038] When the image processing circuit of the autonomous vehicle is working

[0039] Driven by the precise synchronization clock signal provided by the low jitter clock distribution and synchronization module 8, the main image sensor module 1 and the reference image sensor module 2 simultaneously acquire images of the scene in front of the vehicle's driving direction. The main image sensor module 1 captures a composite signal containing real scene information and crosstalk noise, while the reference image sensor module 2, due to its surface being covered with a uniform gray filter, only senses changes in ambient light and pure electrical crosstalk signals.

[0040] Subsequently, the eight parallel analog output signals of the main image sensor module 1 and the reference image sensor module 2 are transmitted to the corresponding input terminals of the analog signal preprocessing and multiplexing module 3, respectively. This module controls the internal multiplexer array to perform timing switching on the sixteen input signals through the address signal. The selected single signal is output to the main signal input terminal of the dynamic crosstalk compensation analog calculation module 4 after preliminary conditioning by the internal low-pass filter and operational amplifier. At the same time, the first output signal of the reference sensor is directly fed into the reference signal input terminal of this module.

[0041] The analog multiplier of the dynamic crosstalk compensation simulation calculation module 4 performs a multiplication operation between the reference signal and the adjustable gain coefficient to generate an inverse compensation signal that is proportional to the amplitude of the measured crosstalk signal and opposite in phase. This compensation signal is injected into the signal processing link through the compensation signal input terminal of the high-precision differential correlation dual sampling module 5.

[0042] Meanwhile, another differential output signal of the analog signal preprocessing and multiplexing module 3 is sent to the differential input of the high-precision differential correlation dual sampling module 5. This module first samples and holds the pixel reset level and signal level twice, and performs correlation dual sampling operation through a fully differential operational amplifier to suppress fixed pattern noise and reset noise. At the same time, it performs analog addition and subtraction operations on the received compensation signal and the main signal to cancel crosstalk components in real time.

[0043] The purified differential signal is then transmitted to the programmable gain amplifier module, where the amplification factor is adjusted according to the ambient light intensity via an external gain control signal to ensure that the output signal amplitude always matches the input range of the subsequent analog-to-digital converter.

[0044] Throughout the entire processing, the ultra-low noise precision reference voltage source module 7 provides a stable and clean voltage reference for the differential correlation dual sampling module, ensuring the consistency of signal processing accuracy.

[0045] Finally, the high-quality differential analog signal, after crosstalk compensation, noise suppression, and gain adjustment, is sent to an external analog-to-digital converter through the output of the programmable gain amplifier module, providing accurate and reliable road environment image information for autonomous vehicles. The entire process is completed entirely in the analog domain, effectively suppressing optical and electrical crosstalk.

[0046] In one possible embodiment, the main image sensor module 1 and the reference image sensor module 2 are placed side-by-side or adjacent to each other to ensure that the images they acquire have consistent context. The main image sensor module 1 and the reference image sensor module 2 are located in the front area of ​​the vehicle, such as near the bumper, vehicle logo, grille, or headlights. The main image sensor module 1 and the reference image sensor module 2 are mounted on a photoelectric sensor bracket, and the photoelectric sensor bracket is firmly fixed to a certain position in the front area of ​​the vehicle using screws, nuts, and anti-loosening washers, or high-strength cable ties. Exposed to the external environment, they sense changes in real ambient light and can capture images of the road, traffic signs, obstacles, etc. ahead without obstruction.

[0047] In one possible embodiment, the gray filter may be an NExxB series neutral density filter, an EdmundOptics coated neutral density filter, or an ND series neutral density filter.

[0048] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An image processing circuit for an unmanned vehicle, characterized in that, The system includes a main image sensor module (1), a reference image sensor module (2), an analog signal preprocessing and multiplexing module (3), a dynamic crosstalk compensation analog calculation module (4), a high-precision differential correlation dual sampling module (5), a programmable gain amplifier and driver module (6), an ultra-low noise precision reference voltage source module (7), and a low-jitter clock distribution and synchronization module (8). The eight analog signal output terminals of the main image sensor module (1) are respectively connected to the eight main signal input terminals of the analog signal preprocessing and multiplexing module (3), and the eight analog signal output terminals of the reference image sensor module (2) are respectively connected to the eight main signal input terminals of the analog signal preprocessing and multiplexing module (3). The analog signal output terminals of the two modules are respectively connected to the eight reference signal input terminals of the analog signal preprocessing and multiplexing module (3), and the first analog signal output terminal of the reference image sensor module (2) is directly connected to the reference signal input terminal of the dynamic crosstalk compensation analog calculation module (4). The main clock output terminal of the low jitter clock distribution and synchronization module (8) is simultaneously connected to the clock signal input terminals of the main image sensor module (1) and the reference image sensor module (2). The three address signal output terminals of the low jitter clock distribution and synchronization module (8) are connected to the analog signal preprocessing and multiplexing module (4). The three address signal input terminals of block (3), the multiplexing signal output terminal of the analog signal preprocessing and multiplexing module (3) is connected to the main signal input terminal of the dynamic crosstalk compensation analog calculation module (4), the compensation signal output terminal of the dynamic crosstalk compensation analog calculation module (4) is connected to the compensation signal input terminal of the high-precision differential correlation double sampling module (5), the positive and negative terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module (3) are respectively connected to the positive and negative terminals of the differential signal input terminal of the high-precision differential correlation double sampling module (5), and the low jitter clock allocation The sampling clock output of the synchronization module (8) is connected to the sampling clock input of the high-precision differential correlation dual sampling module (5). The inverting and non-inverting terminals of the differential signal output of the high-precision differential correlation dual sampling module (5) are connected to the inverting and non-inverting terminals of the differential signal input of the programmable gain amplifier module. The reference voltage output of the ultra-low noise precision reference voltage source module (7) is connected to the reference voltage input of the high-precision differential correlation dual sampling module (5). The inverting and non-inverting terminals of the differential signal output of the programmable gain amplifier module serve as the signal output terminals of the entire image processing circuit.

2. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The main image sensor module (1) includes a first CMOS image sensor chip. The positive terminal of the analog power supply of the first CMOS image sensor chip is connected to the analog ground through a first decoupling capacitor. The positive terminal of the digital power supply of the first CMOS image sensor chip is connected to the digital ground through a second decoupling capacitor. The analog ground terminal of the first CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the first CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the first CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module (8). The eight analog signal output terminals of the first CMOS image sensor chip are respectively connected to the eight main signal input terminals of the analog signal preprocessing and multiplexing module (3) through eight series matching resistors.

3. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The reference image sensor module (2) includes a second CMOS image sensor chip. The positive terminal of the analog power supply of the second CMOS image sensor chip is connected to the analog ground through a third decoupling capacitor. The positive terminal of the digital power supply of the second CMOS image sensor chip is connected to the digital ground through a fourth decoupling capacitor. The analog ground terminal of the second CMOS image sensor chip is connected to the analog ground plane. The digital ground terminal of the second CMOS image sensor chip is connected to the digital ground plane. The clock signal input terminal of the second CMOS image sensor chip is connected to the main clock output terminal of the low jitter clock distribution and synchronization module (8). The surface of the optical photosensitive area of ​​the second CMOS image sensor chip is covered with a gray filter. The first analog signal output terminal of the second CMOS image sensor chip is connected to the reference signal input terminal of the dynamic crosstalk compensation analog calculation module (4) through a matching resistor.

4. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The analog signal preprocessing and multiplexing module (3) includes a first analog switch chip ADG1206, a second analog switch chip ADG1206, an RC low-pass filter, a first operational amplifier ADA4817, and a differential amplifier THS4551. The eight signal input terminals of the first analog switch chip ADG1206 are set as the eight main signal input terminals of the analog signal preprocessing and multiplexing module (3). The eight signal input terminals of the second analog switch chip ADG1206 are set as the eight reference signal input terminals of the analog signal preprocessing and multiplexing module (3). The three address signal input terminals of the two analog switch chips ADG1206 are connected in parallel and set as the three address signal input terminals of the analog signal preprocessing and multiplexing module (3). The signal output terminal of the analog switch chip ADG1206 is connected to the non-inverting input terminal of the first operational amplifier ADA4817 after passing through an RC low-pass filter. The signal output terminal of the first operational amplifier ADA4817 is set as the multiplexed signal output terminal of the analog signal preprocessing and multiplexing module (3). The feedback terminal of the first operational amplifier ADA4817 is connected to its inverting input terminal through a feedback resistor. The other signal output terminal of the first analog switch chip ADG1206 and the second analog switch chip ADG1206 is converted into a differential signal through the differential amplifier THS4551. The non-inverting output terminal and the inverting output terminal of the differential amplifier THS4551 are set as the non-inverting and inverting terminals of the differential signal output terminal of the analog signal preprocessing and multiplexing module (3).

5. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The dynamic crosstalk compensation simulation calculation module (4) includes a second operational amplifier ADA4817, a digital potentiometer, and an analog multiplier AD633. The non-inverting input terminal of the second operational amplifier ADA4817 is set as the main signal input terminal of the dynamic crosstalk compensation simulation calculation module (4). The signal output terminal of the second operational amplifier ADA4817 is connected to the inverting input terminal through a feedback resistor. The serial data terminal and serial clock terminal of the digital potentiometer are set as the control interface of the dynamic crosstalk compensation simulation calculation module (4). The first signal input terminal of the analog multiplier AD633 is connected to the signal output terminal of the second operational amplifier ADA4817. The second signal input terminal of the analog multiplier AD633 is set as the reference signal input terminal of the dynamic crosstalk compensation simulation calculation module (4). The signal output terminal of the analog multiplier AD633 is set as the compensation signal output terminal of the dynamic crosstalk compensation simulation calculation module (4) after passing through an adjustable gain amplifier.

6. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The high-precision differential correlation dual sampling module (5) includes a fully differential operational amplifier THS4531, a sample-and-hold capacitor network, and a compensation signal injection circuit. The non-inverting and inverting input terminals of the fully differential operational amplifier THS4531 are set as the non-inverting and inverting input terminals of the differential signal input terminal of the high-precision differential correlation dual sampling module (5). The compensation signal injection circuit includes a third operational amplifier ADA4817. The non-inverting input terminal of the third operational amplifier ADA4817 is set as the compensation signal input terminal of the high-precision differential correlation dual sampling module (5). The signal output terminal of the third operational amplifier ADA4817 is connected to the inverting input terminal of the fully differential operational amplifier THS4531 through an injection resistor. The sample-and-hold capacitor network includes four... Four precision capacitors are connected between the input and output terminals of the fully differential operational amplifier THS4531. The non-inverting and inverting output terminals of the fully differential operational amplifier THS4531 are set as the non-inverting and inverting terminals of the differential signal output terminals of the high-precision differential correlation dual sampling module (5). The reference voltage input terminal of the high-precision differential correlation dual sampling module (5) provides a common-mode voltage to the fully differential operational amplifier THS4531 through a voltage divider resistor network. The voltage divider resistor network includes a first voltage divider resistor and a second voltage divider resistor connected in series. One end of the first voltage divider resistor is connected to power, and one end of the second voltage divider resistor is grounded. The connection node between the first voltage divider resistor and the second voltage divider resistor is connected to the fully differential operational amplifier THS4531.

7. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The programmable gain amplifier and driver module (6) includes a programmable gain amplifier LTC6912 and an output driver circuit. The differential signal input terminals of the programmable gain amplifier LTC6912 are configured as the differential signal input terminals of the programmable gain amplifier module. The three-way gain control terminals of the programmable gain amplifier LTC6912 are used to receive external gain control signals. The output driver circuit includes a fourth operational amplifier ADA4817 and a fifth operational amplifier ADA4817. The non-inverting input terminal of the fourth operational amplifier ADA4817 is connected to the non-inverting output terminal of the programmable gain amplifier LTC6912. The non-inverting input terminal of the fifth operational amplifier ADA4817 is connected to the inverting output terminal of the programmable gain amplifier LTC6912. The output terminals of the fourth and fifth operational amplifiers ADA4817 are configured as the differential signal output terminals of the programmable gain amplifier module.

8. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The ultra-low noise precision reference voltage source module (7) includes a reference voltage source ADR4540. The voltage output terminal of the reference voltage source ADR4540 is set as the reference voltage output terminal of the ultra-low noise precision reference voltage source module (7) after passing through a π-type filter.

9. The image processing circuit for an unmanned vehicle according to claim 1, characterized in that, The low jitter clock distribution and synchronization module (8) includes a clock generator Si5332. The main clock output of the clock generator Si5332 is set as the main clock output of the low jitter clock distribution and synchronization module (8) after passing through a clock buffer SiT92211. The three address outputs of the clock generator Si5332 are set as the three address signal outputs of the low jitter clock distribution and synchronization module (8) after passing through a level converter Si5330. The auxiliary clock output of the clock generator Si5332 is set as the sampling clock output of the low jitter clock distribution and synchronization module (8) after passing through a clock buffer SiT92211.

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