A low dropout linear regulator for an ultra-low voltage power supply system

Abstract

The utility model provides a low voltage difference linear voltage regulator for super low voltage power supply system, including enable control circuit (B1), error amplifier (B2), common source and bias current source (B3), power transistor and feedback circuit (B4) and load circuit (B5), through enable signal control linear voltage regulator's open and close, adopt super low voltage power supply system to power supply for it, wherein, the reference voltage of error amplifier is low reference voltage, forms low voltage difference with output voltage, adjusts output voltage through feedback circuit, so that can output stable output voltage. The utility model can make super low voltage power supply system output stable voltage under low voltage difference scene.

Description

Technical Field

[0001] This utility model relates to the field of power supply voltage regulation, and more specifically, to a low-dropout linear regulator for ultra-low voltage power supply systems. Background Technology

[0002] In recent years, with the continuous evolution of integrated circuit technology and the gradual popularization of low-power technologies, more and more electronic devices have begun to adopt ultra-low voltage power supply systems, such as wearable devices, the Internet of Things, wireless sensor networks, and energy harvesting. In these application scenarios, the systems generally have high requirements for power supply capabilities. For example, the common supply voltage has gradually decreased from the traditional 1.8V and 1.2V to 0.8V, 0.7V, or even lower. When using batteries or energy harvesting as power sources, the power supply voltage fluctuates greatly. At the same time, in order to maximize battery life, these systems often rely on batteries or DC power supplies with voltages only slightly higher than the target output voltage. High requirements are also placed on static power consumption and voltage drop transient response.

[0003] Low dropout regulators (LDOs) are widely used for voltage regulation in power supply systems due to their advantages such as simple structure, low noise, and fast response. These applications place more stringent design requirements on the voltage regulator circuits, especially the need to achieve stable, reliable, and low-noise output under ultra-low input voltage conditions.

[0004] Therefore, there is an urgent need for a new linear regulator structure with ultra-low dropout voltage, low reference voltage, high output stability, and low quiescent power consumption, suitable for systems with low operating voltage and ultra-low dropout voltage requirements, in order to meet the power management needs of next-generation low-power terminal devices. Summary of the Invention

[0005] This utility model addresses the technical problems existing in the prior art by providing a low-dropout linear regulator for ultra-low voltage power supply systems. It is suitable for ultra-low voltage power supply systems and scenarios requiring ultra-low voltage drop, and the regulator also has controllable enable logic.

[0006] This invention provides a low-dropout linear regulator for ultra-low voltage power supply systems, comprising an enable control circuit B1, an error amplifier B2, a common-source and bias current source B3, a power transistor and feedback circuit B4, and a load circuit B5. The enable signal V... EN Connect the input terminal of the enable control circuit B1, when the enable signal V EN When the voltage level is low, the low-dropout linear regulator does not operate; when the enable signal V... ENWhen the voltage level is high, the low-dropout linear regulator starts working. The power supply terminal of the enable control circuit B1 is connected to the supply voltage VDD, and the output terminal of the enable control circuit B1 is connected to the power supply terminal of the error amplifier B2. The positive input terminal of the error amplifier B2 is connected to the reference voltage V. REF The ground terminal of the error amplifier B2 is grounded. The output terminal of the error amplifier B2 is connected to the input terminal of the common-source and bias current source B3. The power supply terminal of the common-source and bias current source B3 is connected to the power supply terminal of the error amplifier B2. The ground terminal of the common-source and bias current source B3 is grounded. The output terminal of the common-source and bias current source B3 is connected to the input terminal of the power transistor and feedback circuit B4. The power transistor and feedback circuit B4 includes a power transistor and a feedback circuit. The common node of the power transistor and the feedback circuit is the output voltage node. The output voltage node is connected to the load circuit B5. The feedback circuit controls the output voltage V. OUT After voltage division, the input is fed to the negative input terminal of the error amplifier B2;

[0007] Wherein, the supply voltage VDD is provided by an ultra-low voltage power supply system, and the reference voltage V REF It is a low reference voltage.

[0008] This invention provides a low-dropout linear regulator for ultra-low voltage power supply systems. It enables regulated output in ultra-low voltage power supply systems and, by employing a low reference voltage, reduces the voltage division ratio in the feedback circuit, decreases the bias current in the error amplifier, and improves overall static power efficiency and regulation accuracy. Therefore, the low-dropout regulator proposed in this invention is suitable for next-generation ultra-low power digital systems. Attached Figure Description

[0009] Figure 1 A schematic diagram of a low-dropout linear regulator for an ultra-low voltage power supply system is provided as an embodiment of this utility model;

[0010] Figure 2 This is a circuit diagram of a low-dropout linear regulator for an ultra-low voltage power supply system, provided as an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model. In addition, the technical features of the various embodiments or individual embodiments provided by this utility model can be arbitrarily combined to form feasible technical solutions. Such combinations are not bound by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0012] Modern applications such as battery-powered devices, low-voltage SoCs, wearable devices, and IoT nodes require continuous operation even when battery voltage drops. Therefore, it is crucial to design a low-dropout regulator that can maintain a stable output under low-voltage supply conditions.

[0013] Traditional low-dropout linear regulators typically have a minimum dropout voltage of around 0.3V or higher. Therefore, when the input voltage approaches the output voltage—for example, when a battery-powered system approaches low voltage or a low-voltage power supply in an advanced SoC—the control circuitry within these regulators, such as error amplifiers or pass transistors, requires sufficient margin to function properly. Consequently, the traditional regulator begins to lose its ability to maintain a stable output. This results in unstable output, increased ripple, or the low-dropout linear regulator shutting down completely, making these solutions unreliable in ultra-low dropout applications.

[0014] Traditional low-dropout linear regulators typically use relatively high reference voltages, often exceeding 0.6V. When the target output voltage is low, this leads to increased design complexity in the feedback loop, reduced regulation accuracy, and increased quiescent current consumption. Furthermore, the high reference voltage limits the integration of voltage divider networks within the chip. This inefficiency becomes a bottleneck for low-power applications such as wearable devices or IoT sensors, where energy budgets are very limited.

[0015] Furthermore, many low-dropout linear regulators lack integrated enable / disable control logic, posing challenges to power management. The need to coordinate power sequencing, common in modern SoCs and embedded applications, necessitates the use of external switches or additional logic to manage the regulator, increasing complexity and cost. The lack of enable control also limits the system's ability to respond quickly to changing performance or power-saving requirements.

[0016] To address these shortcomings, this invention aims to provide a low-dropout linear regulator capable of operating under ultra-low dropout conditions. Its reference voltage is sufficiently low to enable precise regulation at low output voltages, and it integrates enable control functionality to facilitate enable management. The proposed design addresses space and energy efficiency applications, providing a solution through optimized electrical architecture and system-level flexibility, overcoming the limitations of existing low-dropout linear regulator technology.

[0017] This invention provides a low-dropout linear regulator for ultra-low voltage power supply systems, such as... Figure 1 As shown, the linear regulator includes an enable control circuit B1, an error amplifier B2, a common-source and bias current source B3, a power transistor and feedback circuit B4, and a load circuit B5. The enable signal V... EN Connect the input terminal of the enable control circuit B1, when the enable signal V EN When the voltage level is low, the low-dropout linear regulator does not operate; when the enable signal V... EN When the voltage level is high, the low-dropout linear regulator starts working. The power supply terminal of the enable control circuit B1 is connected to the supply voltage VDD, and the output terminal of the enable control circuit B1 is connected to the power supply terminal of the error amplifier B2. The positive input terminal of the error amplifier B2 is connected to the reference voltage V. REF The ground terminal of the error amplifier B2 is grounded. The output terminal of the error amplifier B2 is connected to the input terminal of the common-source and bias current source B3. The power supply terminal of the common-source and bias current source B3 is connected to the power supply terminal of the error amplifier B2. The ground terminal of the common-source and bias current source B3 is grounded. The output terminal of the common-source and bias current source B3 is connected to the input terminal of the power transistor and feedback circuit B4. The power transistor and feedback circuit B4 includes a power transistor and a feedback circuit. The common node of the power transistor and the feedback circuit is the output voltage node. The output voltage node is connected to the load circuit B5. The feedback circuit controls the output voltage V. OUT After voltage division, the input is fed to the negative input terminal of the error amplifier B2.

[0018] The supply voltage VDD is provided by an ultra-low voltage power supply system, for example, a supply voltage of 0.8V or 0.7V or even lower, and a reference voltage V. REF This is a low reference voltage that is slightly lower than the supply voltage VDD, for example, a reference voltage of 0.5V.

[0019] in, Figure 1 The working principle of a medium-low differential voltage linear regulator is as follows:

[0020] V DD The supply voltage for the low dropout linear regulator, V EN To enable the signal, when VEN When V is low, the low-dropout linear regulator does not work; when V... EN When the voltage level is high, the low-dropout linear regulator (LDL-LEF) starts operating. After the LDL-LEF starts operating, when its output voltage increases, the feedback circuit detects the change in the output signal, causing the feedback voltage to also increase. This increased voltage signal is transmitted to the inverting terminal of the error amplifier, compared with the reference voltage input terminal of the error amplifier, and the voltage difference is obtained. The error amplifier then amplifies this voltage difference, thereby increasing the gate voltage of the power transistor and decreasing the output current. This lowers the output voltage of the LDL-LEF, suppressing its upward trend. When the output voltage of the LDL-LEF decreases, the negative feedback loop lowers the gate voltage of the power transistor, increases the output current, and causes the output voltage of the LDL-LEF to rise, suppressing its downward trend. The common-source circuit and bias current source B3 are more conducive to driving the power transistor to turn on or off.

[0021] The low-dropout linear regulator provided by this invention can achieve the stability of the output voltage of ultra-low power supply systems, and the use of a low reference voltage can improve the precision of voltage regulation.

[0022] In one embodiment of this invention, the enable control circuit B1 includes inverters D1 and D2 connected in series, with the input terminal of inverter D1 connected to a reference voltage V. EN The output terminal of inverter D1 is connected to the input terminal of inverter D2, and the output terminal of inverter D2 is connected to the power supply terminal of error amplifier B2. The power supply terminals of inverter D1 and inverter D2 are both connected to the supply voltage VDD.

[0023] See Figure 2 The inverter D1 includes field-effect transistor M1 and field-effect transistor M2, and the inverter D2 includes field-effect transistor M3 and field-effect transistor M4.

[0024] The supply voltage VDD is connected to the sources of field-effect transistors M1 and M3, respectively, and the gates of field-effect transistors M1 and M2 are both connected to the enable signal V. EN The drains of field-effect transistors M1 and M2 are connected to form a first node. The gates of field-effect transistors M3 and M4 are connected to form a second node. The first node and the second node are connected. The sources of field-effect transistors M2 and M4 are both grounded. The drains of field-effect transistors M3 and M4 are connected to form a third node. The third node is connected to the error amplifier B2.

[0025] Understandably, the enable control circuit B1 consists of four field-effect transistors, M1 to M4. M1 and M2 form an inverter, and M3 and M4 form another inverter.

[0026] In order to introduce the enable signal V EN This is to achieve the switching on and off of the entire circuit, that is, when V EN When V is low, the circuit is de-energized; when V... EN When the voltage is high, the circuit adjusts the output voltage. In this enable control circuit, two inverters are used for signal conversion and switching functions. Field-effect transistors M1 and M3 are P-channel field-effect transistors, and field-effect transistors M2 and M4 are N-channel field-effect transistors. When the P-channel field-effect transistor pulls up the signal transmission in the inverter, it generates on-resistance. Since the input resistance of the subsequent operational amplifier is too small, the voltage division is insufficient to support V. DD Power supply. Therefore, when setting the transistor size, the channel width of the P-channel field-effect transistor should be large enough.

[0027] In one embodiment of this utility model, the error amplifier B2 includes field-effect transistors M5, M6, M7, and M8. The source of field-effect transistor M5 is connected to the source of field-effect transistor M6 and is connected to the third node. The gate of field-effect transistor M5 is connected to the gate of field-effect transistor M6 to form a fourth node. The drain of field-effect transistor M5 is connected to the drain of field-effect transistor M7 to form a fifth node. The fourth node and the fifth node are connected. The drain of field-effect transistor M6 is connected to the drain of field-effect transistor M8 to form a sixth node. The sixth node is connected to the common source and the bias current source B3. The gate of field-effect transistor M8 is connected to the feedback circuit. The source of field-effect transistor M7 is connected to the source of field-effect transistor M8 to form a seventh node. The seventh node is connected to a current mirror, which provides bias current to the error amplifier B3.

[0028] Understandably, error amplifier B2 is composed of four field-effect transistors (FETs) M5 through M8. FETs M5 and M6 form an active load, while FETs M7 and M8 form a differential pair. An active load uses transistors or other active devices to replace traditional resistors as the amplifier's load, providing a significantly higher output impedance than ordinary resistors. Higher output impedance means the amplifier can achieve greater gain under the same transconductance conditions. Compared to resistors, which occupy a large area and have limited accuracy, active loads are more suitable for integrated circuit design, improving linearity and power efficiency while saving area. In the differential pair, transistors M7 and M8 receive the reference voltage V. REFThe differential pair output signal is compared with the reference voltage (obtained by voltage division at the output through resistors R2 and R3) to accurately amplify the voltage difference between the two input terminals. It has excellent common-mode rejection capability, effectively filtering out common-mode interference in the input signal and improving the circuit's noise immunity.

[0029] In one embodiment of this utility model, the current mirror includes a field-effect transistor M9 and a field-effect transistor M10. The gates of the field-effect transistor M9 and the field-effect transistor M10 are connected to form an eighth node. The eighth node is connected to the supply voltage VDD and the common source and bias current source B3. The drain of the field-effect transistor M9 is connected to the supply voltage VDD, and the source of the field-effect transistor M9 is grounded. The drain of the field-effect transistor M10 is connected to the seventh node, and the source of the field-effect transistor M10 is grounded.

[0030] Understandably, the field-effect transistors M9 and M10 form a current mirror to provide current bias for this stage. The current mirror provides a stable and constant current bias for the error amplifier B2, and is a key current source for maintaining the normal operation of the error amplifier. It ensures that the total current of the error amplifier remains constant, thus enabling the error amplifier to accurately reflect input voltage differences.

[0031] In one embodiment of this utility model, the common source and bias current source B3 includes a common source amplifier M11 and a bias current source M12. The source of the common source amplifier M11 is connected to the third node, the gate of the common source amplifier M11 is connected to the sixth node, and the drain of the common source amplifier M11 is connected to the drain of the bias current source M12 to form a ninth node. The ninth node is connected to the sixth node through a capacitor C1 and a resistor R1. The ninth node is also connected to the power transistor and the feedback circuit B4. The gate of the bias current source M12 is connected to the eighth node, and the source of the bias current source M12 is grounded.

[0032] Understandably, M11 is a common-source amplifier. This low-dropout linear regulator is a two-stage amplifier, consisting of a differential pair followed by a common-source amplifier. This eliminates direct coupling between the input and output, enhancing input-output isolation and reducing reverse propagation. This is also the main reason for choosing an error amplifier circuit as the core structure; this structure reduces the Miller effect, thus significantly improving bandwidth. M12 is a bias current source, providing current bias for the common-source amplifier. C1 is a compensation capacitor designed to improve circuit voltage stability; C1 must meet the following requirements:

[0033] C1≥0.22C2≥2.2pF

[0034] C2 is the capacitor in the load circuit B5.

[0035] In one embodiment of this utility model, the power transistor and feedback circuit B4 includes a power transistor M13 and a feedback circuit. The feedback circuit includes resistors R2 and R3. The gate of the power transistor M13 is connected to the ninth node, the source of the power transistor M13 is connected to the third node, and the drain of the power transistor M13 is grounded through resistors R2 and R3. The common node of the drain of the power transistor M13 and resistor R2 is the tenth node, and the common node of resistors R2 and R3 is denoted as the eleventh node. The tenth node is the output voltage node, and the output voltage is denoted as Vout. The eleventh node is connected to the gate of M8.

[0036] Understandably, M13 is a power transistor, which provides a large output current to the load circuit; therefore, power transistors are typically composed of large-size transistors. P-channel MOSFETs have lower noise parameters and lower differential voltage values ​​compared to N-channel MOSFETs; therefore, in this low-dropout linear regulator design, a P-channel MOSFET is used as the power transistor. The power transistor is designed to operate in the saturation region under differential voltage. Although the voltage gain of the power transistor is less than 1, the loop gain is not affected due to the error amplifier and the second-stage gain phase.

[0037] The output voltage V of the linear regulator out It is mainly determined by the reference voltage and two resistors, R2 and R3, and can be obtained from the following relationship:

[0038]

[0039] In one embodiment of this utility model, the load circuit B5 includes a resistor R4 and a capacitor C2, both of which are connected to the output voltage node. The load circuit B5 is used to stabilize the output voltage.

[0040] Below is a specific practical application example:

[0041] The input voltage of the low dropout linear regulator is V DD =0.9V, output voltage V OUT =0.5V, reference voltage V REF =0.5V, designed using FreePDK 45nm CMOS process.

[0042] The error amplifier will be designed using general-purpose components (N_VTG and P_VTG) available in the process, which support a supply voltage of 0.9V. The transistor dimensions are determined by calculating the current equations under its saturation region operating conditions.

[0043]

[0044] The meanings of each parameter are as follows:

[0045] I D — Drain current, in amperes (A)

[0046] u—Transistor carrier mobility, in units of...

[0047] Cox — the capacitance of the oxide layer per unit area of ​​the transistor gate insulating layer, in units of

[0048] W – Transistor channel width, in nm

[0049] L – Transistor channel length, in nm

[0050] V sat — Transistor saturation voltage, in volts (V).

[0051] Starting with the bias current flowing into the current mirror, select 20 μA for each stage and set the channel length L = 2L. min =100nm, and the width of each transistor in the error amplifier can be determined individually based on the current flowing through its circuit. Therefore:

[0052]

[0053] I M9 =I M10 =I M12

[0054] I M5 =I M6 =I M7 =I M8 =1 / 2×I M9 =1 / 2×I M11

[0055] Among them, I Mx — This represents the drain current of the transistor numbered Mx.

[0056] Table 1 below shows the dimensions of each transistor:

[0057] Table 1

[0058] NMOS_VTG W(nm) L(nm) PMOS_VTG W(nm) L(nm) M2 20,000 50 M1 20,000 50 M4 20,000 50 M3 20,000 50 M7 227.5 100 M5 540 100 M8 227.5 100 M6 540 100 M9 455 100 M11 1160 100 M10 455 100 M13 20,000 100 M12 455 100

[0059] Subscript 2 gives the values ​​of each resistor and capacitor:

[0060] Table 2

[0061] Position value R1 1kΩ R2 20kΩ R3 50kΩ R4 10kΩ C1 2.2pF C2 10pF

[0062] This invention provides a low-dropout linear regulator for ultra-low voltage power supply systems. Its key feature is the ability to achieve stable and accurate linear voltage regulation output under low voltage and low dropout conditions, and it also has enable control, offering the following advantages:

[0063] (1) Two inverters are introduced, which can effectively control the circuit's on and off states. This structure allows the linear regulator to start and stop according to the enable signal VEN, reducing system standby power consumption. In addition, the wide-channel design of the P-channel MOSFET reduces the on-resistance, ensuring reliable pull-up under low-impedance input conditions in the subsequent stage, logically ensuring the stability and compatibility of the circuit during startup.

[0064] (2) In the error amplifier (B2) and common-source amplifier stage (B3), a combination of differential pairs, active loads, and current mirrors is used. This design significantly improves gain, suppresses common-mode interference, and saves chip area. The current mirror structure provides a stable bias current, ensuring that the circuit maintains accurate bias even at extremely low voltages. This precise bias current supply, combined with the high loop gain brought by the two-stage amplification structure, significantly improves the output voltage regulation capability and transient response capability. Logically, this high-performance analog front-end design optimizes the solution to the problem of insufficient stability under low-voltage operation.

[0065] (3) The power transistor and feedback circuit (B4) uses a large-size P-channel field-effect transistor as the output component, which has better noise performance and lower Vds voltage drop requirements. The feedback loop adopts a standard voltage divider structure, which, combined with the error amplifier, forms a negative feedback control system. It can maintain stable voltage output under load fluctuations and input voltage changes, thus it can be inferred that the output voltage has high stability and good load regulation capability.

[0066] (4) The introduction of the load circuit (B5) not only optimizes the dynamic load capability of the output, but the compensation network formed by C2 and R4 further enhances the stability of the system in the frequency domain. Logically, this structure effectively suppresses high-frequency oscillations of the output voltage.

[0067] In summary, through the reasoning and combination of functions between modules, the following significant advantages of this invention can be derived:

[0068] Achieve reliable startup and stable output at extremely low voltage drop (less than 0.3V);

[0069] It features low quiescent current and is suitable for normally open circuits and low-power terminals.

[0070] The high-gain amplifier structure ensures good voltage regulation and common-mode interference rejection.

[0071] The modular structure facilitates SoC integration and size optimization, making it suitable for long-term operation in battery-powered environments.

[0072] Therefore, the present invention exhibits significant advantages over existing technologies in terms of high efficiency, low power consumption, and high integration.

[0073] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0074] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. A low-dropout linear regulator for ultra-low voltage power supply systems, characterized in that, It includes an enable control circuit (B1), an error amplifier (B2), a common-source and bias current source (B3), a power transistor and feedback circuit (B4), and a load circuit (B5), with an enable signal V. EN Connect the input terminal of the enable control circuit (B1), when the enable signal V EN When the voltage level is low, the low-dropout linear regulator does not operate; when the enable signal V... EN When the voltage level is high, the low-dropout linear regulator starts working. The power supply terminal of the enable control circuit (B1) is connected to the supply voltage VDD, and the output terminal of the enable control circuit (B1) is connected to the power supply terminal of the error amplifier (B2). The positive input terminal of the error amplifier (B2) is connected to the reference voltage V. REF The error amplifier (B2) is grounded, and its output is connected to the input of the common-source and bias current source (B3). The power supply of the common-source and bias current source (B3) is connected to the power supply of the error amplifier (B2). The ground of the common-source and bias current source (B3) is grounded, and its output is connected to the input of the power transistor and feedback circuit (B4). The power transistor and feedback circuit (B4) includes a power transistor and a feedback circuit. The common node of the power transistor and the feedback circuit is the output voltage node, which is connected to the load circuit (B5). The feedback circuit outputs voltage V. OUT After voltage division, the input is fed to the negative input terminal of the error amplifier (B2); Wherein, the supply voltage VDD is provided by an ultra-low voltage power supply system, and the reference voltage V REF It is a low reference voltage.

2. The low-dropout linear regulator according to claim 1, characterized in that, The enable control circuit (B1) includes inverters D1 and D2 connected in series, with the input terminal of inverter D1 connected to a reference voltage V. EN The output terminal of inverter D1 is connected to the input terminal of inverter D2, and the output terminal of inverter D2 is connected to the power supply terminal of the error amplifier (B2). The power supply terminals of inverter D1 and inverter D2 are both connected to the supply voltage VDD.

3. The low-dropout linear regulator according to claim 2, characterized in that, The inverter D1 includes field-effect transistors M1 and M2, and the inverter D2 includes field-effect transistors M3 and M4. The supply voltage VDD is connected to the sources of field-effect transistors M1 and M3, respectively. The gates of field-effect transistors M1 and M2 are both connected to the enable signal V. EN The drains of field-effect transistors M1 and M2 are connected to form a first node. The gates of field-effect transistors M3 and M4 are connected to form a second node. The first node and the second node are connected. The sources of field-effect transistors M2 and M4 are both grounded. The drains of field-effect transistors M3 and M4 are connected to form a third node. The third node is connected to the error amplifier (B2).

4. The low-dropout linear regulator according to claim 3, characterized in that, The field-effect transistors M1 and M3 are P-channel field-effect transistors, and the field-effect transistors M2 and M4 are N-channel field-effect transistors.

5. The low-dropout linear regulator according to claim 3, characterized in that, The error amplifier (B2) includes field-effect transistors M5, M6, M7, and M8. The sources of M5 and M6 are connected and connected to the third node. The gates of M5 and M6 are connected to form the fourth node. The drains of M5 and M7 are connected to form the fifth node. The fourth node and the fifth node are connected. The drains of M6 and M8 are connected to form the sixth node. The sixth node is connected to the common source and bias current source (B3). The gate of M8 is connected to the feedback circuit. The source of M7 and the source of M8 are connected to form the seventh node. The seventh node is connected to a current mirror, which provides bias current to the common source and bias current source (B3).

6. The low-dropout linear regulator according to claim 5, characterized in that, The current mirror includes a field-effect transistor M9 and a field-effect transistor M10. The gates of M9 and M10 are connected to form an eighth node. The eighth node is connected to the supply voltage VDD and the common source and bias current source (B3). The drain of M9 is connected to the supply voltage VDD, and the source of M9 is grounded. The drain of M10 is connected to the seventh node, and the source of M10 is grounded.

7. The low-dropout linear regulator according to claim 6, characterized in that, The common source and bias current source (B3) includes a common source amplifier M11 and a bias current source M12. The source of M11 is connected to the third node, the gate of M11 is connected to the sixth node, and the drain of M11 is connected to the drain of M12 to form a ninth node. The ninth node is connected to the sixth node through a capacitor C1 and a resistor R1. The ninth node is also connected to the power transistor and the feedback circuit (B4). The gate of M12 is connected to the eighth node, and the source of M12 is grounded.

8. The low-dropout linear regulator according to claim 7, characterized in that, The power transistor and feedback circuit (B4) includes a power transistor M13 and a feedback circuit. The feedback circuit includes resistors R2 and R3. The gate of the power transistor M13 is connected to the ninth node, the source of the power transistor M13 is connected to the third node, and the drain of the power transistor M13 is grounded through resistors R2 and R3. The common node of the drain of the power transistor M13 and resistor R2 is the tenth node, and the common node of resistors R2 and R3 is the eleventh node. The tenth node is the output voltage node, and the output voltage is denoted as Vout. The eleventh node is connected to the gate of the field-effect transistor M8.

9. The low-dropout linear regulator according to claim 1, characterized in that, The load circuit (B5) includes a resistor R4 and a capacitor C2, both of which are connected to the output voltage node.

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