Substrate wiring package carrier and substrate wiring package structure

Abstract

This invention provides a substrate wiring packaging carrier and a substrate wiring packaging structure, relating to the field of chip packaging technology. The substrate wiring packaging carrier includes a glass substrate and thermally conductive pillars. A thermally conductive metal layer is formed on one surface of the glass substrate to support an adhesive layer and a reconfigurable wiring assembly layer on the adhesive layer. The reconfigurable wiring assembly layer includes a bare die, a redistribution layer, and a molding compound layer. The bare die is connected to the redistribution layer, and the molding compound layer covers the bare die. The thermally conductive metal layer can be sputtered onto the surface of the glass substrate. The thermally conductive pillars are disposed within the glass substrate and extend to the thermally conductive metal layer for heat dissipation. Compared to existing technologies, this invention employs a thermally conductive pillar design, which enables better heat conduction during irradiation, thereby dissipating heat from the thermally conductive metal layer after it overheats, preventing excessive heat conduction to the adhesive layer and avoiding thermal effects on the reconfigurable wafer.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and more specifically, to a substrate wiring packaging carrier and a substrate wiring packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, fan-out packaging structures or 2.5D packaging structures usually adopt temporary bonding processes. Therefore, a layer of release adhesive is usually coated on the panel surface as a temporary bonding layer. This release adhesive is usually a UV adhesive layer that is separated by laser irradiation. At the same time, a metal layer is deposited on the release adhesive as a barrier layer (to prevent the redistribution layer or chip from being affected during debonding) before the wafer reconstruction and RDL wiring are carried out. The metal layer is then etched away after debonding.

[0003] However, since debonding adhesive requires direct ultraviolet laser irradiation, the temperature is high, which can easily cause thermal effects on the chip or redistribution layer, resulting in warping. Utility Model Content

[0004] The purpose of this invention is to provide a substrate wiring packaging method, a substrate wiring packaging structure, and a substrate wiring packaging carrier, which can reduce the influence of debonding temperature and reduce warping caused by thermal effects.

[0005] In a first aspect, this utility model provides a substrate wiring packaging method, comprising: A glass substrate, wherein a thermally conductive metal layer is sputtered on one side surface of the glass substrate for supporting an adhesive layer and a reconfiguration wiring assembly layer on the adhesive layer, the reconfiguration wiring assembly layer including a bare die, a redistribution layer and a molding compound layer, the bare die being connected to the redistribution layer and the molding compound layer covering the bare die; A heat-conducting pillar is disposed in the glass substrate and extends to the heat-conducting metal layer for heat dissipation of the heat-conducting metal layer; The thermally conductive metal layer is heated under white light irradiation and acts on the adhesive layer to separate the glass substrate and the adhesive layer.

[0006] Furthermore, the heat-conducting pillar extends along the thickness direction of the glass substrate and penetrates the glass substrate.

[0007] Furthermore, the thermally conductive metal layer is a TiW layer.

[0008] Furthermore, the heat-conducting pillar is a copper pillar.

[0009] Secondly, this utility model provides a substrate wiring package structure, including an adhesive layer, a reconfigurable wiring assembly layer and the aforementioned substrate wiring package carrier board. The adhesive layer is disposed on the thermally conductive metal layer, and the reconfigurable wiring assembly layer is disposed on the adhesive layer. The reconfigurable wiring assembly layer includes a bare die, a reconfigurable layer and a molding compound layer. The bare die is connected to the reconfigurable layer, and the molding compound layer covers the bare die.

[0010] Furthermore, the redistribution layer is disposed on the adhesive layer, the bare die is mounted on the redistribution layer, wherein the conductive bumps on the front side of the bare die face the redistribution layer and are connected to the redistribution layer, and the molding compound is disposed on the redistribution layer.

[0011] Furthermore, the bare die is mounted on the adhesive layer, and the conductive block on the front side of the bare die faces away from the adhesive layer. The molding compound is disposed on the adhesive layer, and the conductive block on the front side of the bare die is exposed outside the molding compound. The redistribution layer is disposed on the molding compound and is connected to the conductive block on the front side of the bare die.

[0012] Furthermore, the redistribution layer is provided with metal pads at a distance from the bare chip, and solder balls are provided on the metal pads.

[0013] Furthermore, an adhesive film layer is provided on the back side of the bare chip, and the adhesive film layer is bonded to the adhesive layer.

[0014] Furthermore, the projection of the bare chip onto the glass substrate overlaps with the heat-conducting pillar.

[0015] The beneficial effects of this utility model embodiment include: The substrate wiring packaging carrier and structure provided in this embodiment of the invention employs a novel carrier where a thermally conductive metal layer is sputtered onto the surface of a glass substrate. This thermally conductive metal layer can support the adhesive layer and the reconfigurable wiring assembly layer thereon during the packaging process. The reconfigurable wiring assembly layer includes a bare die, a redistribution layer, and a molding compound layer. The bare die is connected to the redistribution layer, and the molding compound layer covers the bare die. Simultaneously, the thermally conductive metal layer can be heated under white light irradiation and act on the adhesive layer, thereby separating the glass substrate and the adhesive layer. Thermally conductive pillars are disposed in the glass substrate, extending to the thermally conductive metal layer, which can dissipate heat from the thermally conductive metal layer. Compared to the prior art, the substrate wiring packaging carrier provided in this embodiment of the invention, with its thermally conductive pillar design, can better achieve heat conduction during irradiation, thereby dissipating heat from the thermally conductive metal layer after it overheats, and preventing excessive heat conduction to the adhesive layer and the resulting thermal effect on the reconfigurable wafer. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a process flow diagram of a substrate wiring packaging method in the prior art; Figure 2 This is a schematic diagram of the structure of the substrate wiring packaging carrier provided in the embodiment of the present utility model; Figure 3 A schematic diagram of the first substrate wiring packaging structure provided in this embodiment of the present utility model; Figures 4 to 11 A process flow diagram of the first substrate wiring and packaging method provided in this embodiment of the utility model; Figure 12 A schematic diagram of the second substrate wiring packaging structure provided in this embodiment of the present invention; Figures 13 to 15 This is a partial process flow diagram of the substrate wiring and packaging method provided in the second embodiment of the present invention.

[0018] Icons: 100 - Substrate wiring package structure; 110 - Bare chip; 111 - Conductive block; 112 - Conductive bump; 130 - Molding layer; 150 - Rewiring layer; 151 - Metal pad layer; 153 - Solder ball; 20 - Substrate wiring package carrier; 200 - Glass substrate; 210 - Thermally conductive metal layer; 230 - Thermally conductive pillar; 300 - Adhesive layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of this utility model, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the utility model product is usually placed during use, they are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0023] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0024] See Figure 1 As disclosed in the background section, the existing panel-level packaging process flow is as follows: A debonding adhesive layer is coated on a glass substrate, and then a TiCu or Al metal layer is deposited on the debonding adhesive layer. Then, a chip is attached, molded, and RDL wiring is performed (or RDL wiring, chip attachment, and molding) to complete the fabrication of the reconstructed wafer. After this process, laser debonding and peeling of the glass substrate is performed. This involves using ultraviolet laser irradiation to decompose the debonding adhesive layer at high temperature. After cleaning the residual adhesive layer, the metal layer is etched away, and finally, the wafer is cut to obtain a single product.

[0025] It can be seen that existing glass substrates usually do not have a metal layer on the surface and have poor thermal conductivity, resulting in high temperatures at the bonding adhesive layer during laser debonding, which in turn leads to the risk of warping in the reconstructed wafer.

[0026] To address the aforementioned problems, this utility model provides a novel substrate wiring packaging carrier and substrate wiring packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of this utility model can be combined with each other.

[0027] See Figure 2 The substrate wiring packaging carrier 20 provided in this embodiment of the present invention can reduce the influence of debonding temperature and reduce warping caused by thermal effects.

[0028] The substrate wiring packaging carrier 20 provided in this embodiment includes a glass substrate 200 and thermally conductive pillars 230. A thermally conductive metal layer 210 is formed on one side surface of the glass substrate 200 for supporting an adhesive layer 300 and a reconfigurable wiring assembly layer on the adhesive layer 300. The reconfigurable wiring assembly layer includes a bare die 110, a redistribution layer 150, and a molding compound 130. The bare die 110 is connected to the redistribution layer 150, and the molding compound 130 covers the bare die 110. The thermally conductive metal layer 210 can be sputtered onto the surface of the glass substrate 200. The thermally conductive pillars 230 are disposed in the glass substrate 200 and extend to the thermally conductive metal layer 210 for heat dissipation of the thermally conductive metal layer 210. The thermally conductive metal layer 210 is heated under white light irradiation and acts on the adhesive layer 300, thereby separating the glass substrate 200 and the adhesive layer 300.

[0029] Furthermore, the heat-conducting pillar 230 extends along the thickness direction of the glass substrate 200 and penetrates through the glass substrate 200. The thermally conductive metal layer 210 can be a TiW layer, and the heat-conducting pillar 230 can be a copper pillar. Specifically, the heat-conducting pillar 230 can be multiple TSV copper pillars, and the heat-conducting pillar 230 penetrates along the thickness direction of the glass substrate 200 to both sides of the glass substrate 200, thereby allowing the heat-conducting pillar 230 to contact the thermally conductive metal layer 210. This enables better heat conduction during irradiation, thus dissipating heat from the thermally conductive metal layer 210 after it overheats, preventing excessive heat conduction to the adhesive layer 300 and avoiding thermal effects on the reconstructed wafer.

[0030] The substrate wiring packaging carrier 20 provided in this embodiment of the utility model can be peeled off together with the glass substrate 200 using a process that avoids the metal layer remaining on the reconstructed wiring assembly layer. Therefore, no subsequent etching is required to remove it, and the etching process is prevented from affecting the reconstructed wiring structure. At the same time, the design of the heat-conducting pillars 230 can better achieve heat conduction during irradiation, thereby dissipating heat from the heat-conducting metal layer 210 after it overheats, and preventing excessive heat conduction to the adhesive layer 300, which would cause a thermal effect on the reconstructed wafer.

[0031] Please see Figure 3This utility model provides a substrate wiring package structure 100, including an adhesive layer 300, a reconfigurable wiring assembly layer, and the aforementioned substrate wiring package carrier 20. The substrate wiring package carrier 20 includes a glass substrate 200 and a heat-conducting pillar 230. A heat-conducting metal layer 210 is formed on one side surface of the glass substrate 200 for supporting the adhesive layer 300 and the reconfigurable wiring assembly layer on the adhesive layer 300. The reconfigurable wiring assembly layer includes a bare die 110, a reconfigurable layer 150, and a molding compound 130. The bare die 110 is connected to the reconfigurable layer 150, and the molding compound 130 covers the bare die 110. The thermally conductive metal layer 210 can be sputtered onto the surface of the glass substrate 200. Thermally conductive pillars 230 are disposed within the glass substrate 200 and extend to the thermally conductive metal layer 210 for heat dissipation. The thermally conductive metal layer 210 is heated under white light irradiation and acts on the adhesive layer 300, thereby separating the glass substrate 200 and the adhesive layer 300. The adhesive layer 300 is disposed on the thermally conductive metal layer 210, and a reconfigurable wiring assembly layer is disposed on the adhesive layer 300. The reconfigurable wiring assembly layer includes a bare die 110, a redistribution layer 150, and a molding compound layer 130. The bare die 110 is connected to the redistribution layer 150, and the molding compound layer 130 covers the bare die 110.

[0032] In some embodiments, a redistribution layer 150 is disposed on an adhesive layer 300, and a bare chip 110 is mounted on the redistribution layer 150, wherein the conductive bumps 112 on the front side of the bare chip 110 face the redistribution layer 150 and are connected to the redistribution layer 150, and a molding compound 130 is disposed on the redistribution layer 150.

[0033] In some embodiments, the projection of the bare chip 110 onto the glass substrate 200 overlaps with the heat-conducting pillar 230.

[0034] This utility model embodiment provides a substrate wiring packaging method for preparing the aforementioned substrate wiring packaging structure 100. The method includes the following steps: S1: A glass substrate 200 is provided, wherein a thermally conductive metal layer 210 is sputtered on the surface of the glass substrate 200.

[0035] Please continue reading Figure 3 Specifically, a glass substrate 200 is first provided. The glass substrate 200 is a transparent plate. Then, a thermally conductive metal layer 210 is sputtered onto the surface of the glass substrate 200. The thermally conductive metal layer 210 can be a TiW layer, which has good thermal conductivity. Furthermore, the glass substrate 200 is provided with thermally conductive pillars 230, which extend to the thermally conductive metal layer 210. The thermally conductive pillars 230 can be multiple TSV copper pillars, and they penetrate along the thickness direction of the glass substrate 200 to both sides of the glass substrate 200, thereby making the thermally conductive pillars 230 contact with the thermally conductive metal layer 210.

[0036] S2: An adhesive layer 300 is formed by spin coating on the thermally conductive metal layer 210.

[0037] See Figure 4 Specifically, an adhesive layer 300 is formed on the thermally conductive metal layer 210 by spin coating, and the adhesive layer 300 can be a pyrolytic adhesive.

[0038] S3: A reconfigurable wiring assembly layer is formed on the adhesive layer 300.

[0039] The reconfigurable routing layer includes a bare chip 110, a rerouting layer 150, and a molding compound 130. The bare chip 110 is connected to the rerouting layer 150, and the molding compound 130 covers the bare chip 110.

[0040] See Figure 5 In this embodiment, when preparing the reconfigurable wiring combination layer, the reconfigurable wiring layer 150 can be formed on the adhesive layer 300 first. That is, a dielectric layer is first coated, patterned and then electroplated to form wiring metal, and then a dielectric layer is coated. Multiple layers can be prepared to complete the preparation of the reconfigurable wiring layer 150.

[0041] See Figure 6 Then, a bare chip 110 is mounted on the redistribution layer 150, with the bare chip 110 facing downwards, so that the conductive bumps 112 on the front side of the bare chip 110 face the redistribution layer 150 and are connected to the redistribution layer 150. Specifically, the connection between the bare chip 110 and the conductive bumps 112 on the redistribution layer 150 can be achieved through the pads on the redistribution layer 150. Here, the bare chip 110 is a flip chip.

[0042] Please continue reading Figure 3 Finally, a molding compound 130 is formed on the redistribution layer 150, which covers the bare die 110. That is, a molding compound structure is formed on the redistribution layer 150 using a molding compounding process, thereby protecting the bare die 110.

[0043] Of course, before performing step S3, it is necessary to prepare and form bare chips 110. Specifically, first, a wafer is provided, which can still be a silicon-based wafer. Then, conductive blocks 111 are formed on the front side of the wafer, and the back side of the wafer is thinned, i.e., the back side of the wafer is ground. Finally, the wafer can be cut along the dicing lines to form multiple bare chips 110.

[0044] In some embodiments, after the substrate wiring package structure 100 is formed, subsequent processes can be performed to obtain the final product. Specifically, the following steps can also be performed: S4: Use white light to irradiate the thermally conductive metal layer 210 to peel off the glass substrate 200, wherein the thermally conductive metal layer 210 is heated under white light irradiation and acts on the adhesive layer 300.

[0045] See Figure 7 Specifically, white light can be used to irradiate the thermally conductive metal layer 210. When irradiated with white light, a temperature of 100-300°C can be generated. The thermally conductive metal layer 210 can transfer heat to the adhesive layer 300, causing the adhesive layer 300 to lose its adhesiveness and carbonize at the same time. Therefore, it will not produce a thermal effect on the reconfigured wiring assembly layer and reduce warping.

[0046] S5: Remove adhesive layer 300.

[0047] See Figure 8 Specifically, the adhesive layer 300 can be cleaned and removed using a cleaning solution, avoiding the problem of missing metal layer material and wiring metal caused by the etching process, thereby avoiding affecting the redistribution layer 150.

[0048] See Figure 9 After removing the adhesive layer 300, a metal pad layer 151 can be formed on the side of the redistribution layer 150 away from the chip, and then solder balls 153 can be formed on the metal pad layer 151. Specifically, the solder balls 153 are electrically connected to the redistribution layer 150 through the metal pad layer 151.

[0049] S6: Cut along the cutting path to reconstruct the wiring combination layer.

[0050] See Figure 10 and Figure 11 Specifically, the wiring assembly layer can be reconstructed using a dicing blade or laser cutting to form a single product. Figure 11 This is a top view of a single product, which may contain one bare chip 110 or multiple bare chips 110.

[0051] See Figure 12 In some other preferred embodiments, the bare chip 110 is mounted on the adhesive layer 300, and the conductive block 111 on the front side of the bare chip 110 faces away from the adhesive layer 300. The molding compound 130 is disposed on the adhesive layer 300, and the conductive block 111 on the front side of the bare chip 110 is exposed on the molding compound 130. The redistribution layer 150 is disposed on the molding compound 130 and connected to the conductive block 111 on the front side of the bare chip 110.

[0052] Furthermore, a metal pad layer 151 is provided on the redistribution layer 150 away from the bare die 110, and solder balls 153 are provided on the metal pad layer 151. An adhesive film layer is provided on the back side of the bare die 110, and the adhesive film layer is bonded to the adhesive layer 300.

[0053] This utility model embodiment also provides a substrate wiring packaging method for preparing the substrate wiring packaging structure 100 shown in the figure. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0054] The substrate wiring packaging method provided in this embodiment of the utility model includes the following steps: S1: A glass substrate 200 is provided, wherein a thermally conductive metal layer 210 is sputtered on the surface of the glass substrate 200.

[0055] S2: An adhesive layer 300 is formed by spin coating on the thermally conductive metal layer 210.

[0056] Steps S1 and S2 are the same as in the first embodiment.

[0057] S3: A reconfigurable wiring assembly layer is formed on the adhesive layer 300.

[0058] See Figure 13 In this embodiment, when preparing the reconfigurable wiring assembly layer, bare chips 110 can be first mounted on the adhesive layer 300, with the conductive blocks 111 on the front side of the bare chips 110 facing away from the adhesive layer 300. That is, the bare chips 110 are mounted facing upwards on the adhesive layer 300, and the bare chips 110 can be mounted at intervals.

[0059] See Figure 14 Then, using a molding process, a molding layer 130 is formed on the adhesive layer 300, wherein the molding layer 130 covers the bare chip 110.

[0060] See Figure 15 Then, using a grinding process, the molding compound 130 is thinned to expose the conductive block 111 on the front side of the bare chip 110.

[0061] Please see Figure 12 Finally, a redistribution layer 150 is formed on the molding compound 130. Specifically, a wiring process can be used, where a dielectric layer is first coated and patterned, then electroplated to form wiring metal, followed by coating with another dielectric layer. This process can be repeated for multiple layers to complete the fabrication of the redistribution layer 150. The redistribution layer 150 is electrically connected to the conductive blocks 111 of the bare chip 110.

[0062] After the redistribution layer 150 is formed, a metal pad layer 151 can be formed on the side of the redistribution layer 150 away from the chip; then solder balls 153 are formed on the metal pad layer 151; finally, a film layer is formed on the redistribution layer 150, wherein the film layer plays a protective role.

[0063] Of course, before performing step S3, it is necessary to prepare and form bare chips 110. Specifically, first, a wafer is provided, which can still be a silicon-based wafer. Then, conductive blocks 111 are formed on the front side of the wafer. Next, the back side of the wafer is thinned, i.e., the back side of the wafer is ground. Then, an adhesive film layer is formed on the back side of the wafer. This adhesive film layer facilitates mounting onto the adhesive layer 300. Finally, the wafer can be cut along the dicing lines to form multiple bare chips 110.

[0064] The substrate wiring packaging carrier 20, substrate wiring packaging structure 100, and method provided in this embodiment of the utility model first provide a glass substrate 200 with a thermally conductive metal layer 210 sputtered on its surface. Then, an adhesive layer 300 is formed by spin-coating on the thermally conductive metal layer 210. A reconfigurable wiring assembly layer is then formed on the adhesive layer 300. This reconfigurable wiring assembly layer consists of a bare die 110, a redistribution layer 150, and a molding compound layer 130. The bare die 110 is connected to the redistribution layer 150, and the molding compound layer 130 covers the bare die 110. After completing the redistribution and wafer reconstruction operations, the thermally conductive metal layer 210 can be irradiated with white light. Under the irradiation, the thermally conductive metal layer 210 is heated and acts on the adhesive layer 300, causing the adhesive layer 300 to lose its adhesiveness and peel off the glass substrate 200, while the thermally conductive metal layer 210 can also be peeled off. Then, the adhesive layer 300 is removed by cleaning, and finally, the reconstructed wafer is sent to the dicing position to cut the reconstructed wiring assembly layer along the dicing path to obtain a single product. A heat-conducting pillar 230 is provided in the glass substrate 200, extending to the heat-conducting metal layer 210. Compared with the prior art, the substrate wiring packaging method provided in this embodiment of the present invention first uses a glass substrate 200 with a heat-conducting metal layer 210, and uses the adhesive layer 300 as a subsequent separation layer. Simultaneously, due to the use of white light irradiation, which has low-temperature characteristics, the thermal effect on the reconstructed wafer can be reduced, thereby reducing warpage. The design of the heat-conducting pillar 230 can better achieve heat conduction during irradiation, thereby dissipating heat from the heat-conducting metal layer 210 after it overheats, preventing excessive heat conduction to the adhesive layer 300 and causing a thermal effect on the reconstructed wafer. Furthermore, since the heat-conducting metal layer 210 is peeled off together with the glass substrate 200, no subsequent etching removal is required, avoiding the etching process affecting the reconstructed wiring structure.

[0065] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A substrate wiring packaging carrier board, characterized in that, include: A glass substrate, wherein a thermally conductive metal layer is sputtered on one side surface of the glass substrate for supporting an adhesive layer and a reconfiguration wiring assembly layer on the adhesive layer, the reconfiguration wiring assembly layer including a bare die, a redistribution layer and a molding compound layer, the bare die being connected to the redistribution layer and the molding compound layer covering the bare die; A heat-conducting pillar is disposed in the glass substrate and extends to the heat-conducting metal layer for dissipating heat from the heat-conducting metal layer. The thermally conductive metal layer is heated under white light irradiation and acts on the adhesive layer to separate the glass substrate and the adhesive layer.

2. The substrate wiring packaging carrier board according to claim 1, characterized in that, The heat-conducting pillar extends along the thickness direction of the glass substrate and penetrates the glass substrate.

3. The substrate wiring packaging carrier board according to claim 2, characterized in that, The thermally conductive metal layer is a TiW layer.

4. The substrate wiring packaging carrier board according to claim 2, characterized in that, The heat-conducting pillar is a copper pillar.

5. A substrate wiring package structure, characterized in that, The package includes an adhesive layer, a reconfigurable wiring assembly layer, and a substrate wiring package carrier as described in claim 1. The adhesive layer is disposed on the thermally conductive metal layer, and the reconfigurable wiring assembly layer is disposed on the adhesive layer. The reconfigurable wiring assembly layer includes a bare die, a reconfigurable layer, and a molding compound layer. The bare die is connected to the reconfigurable layer, and the molding compound layer covers the bare die.

6. The substrate wiring packaging structure according to claim 5, characterized in that, The redistribution layer is disposed on the adhesive layer, the bare die is mounted on the redistribution layer, wherein the conductive bumps on the front side of the bare die face the redistribution layer and are connected to the redistribution layer, and the molding compound is disposed on the redistribution layer.

7. The substrate wiring packaging structure according to claim 5, characterized in that, The bare die is mounted on the adhesive layer, and the conductive block on the front side of the bare die faces away from the adhesive layer. The molding compound is disposed on the adhesive layer, and the conductive block on the front side of the bare die is exposed in the molding compound. The redistribution layer is disposed on the molding compound and is connected to the conductive block on the front side of the bare die.

8. The substrate wiring packaging structure according to claim 7, characterized in that, The redistribution layer has metal pads located away from the bare chip, and solder balls are disposed on the metal pads.

9. The substrate wiring packaging structure according to claim 7, characterized in that, An adhesive film layer is provided on the back of the bare chip, and the adhesive film layer is bonded to the adhesive layer.

10. The substrate wiring packaging structure according to claim 5, characterized in that, The projection of the bare chip onto the glass substrate overlaps with the heat-conducting pillar.

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