Pixel structure and display device

Abstract

A pixel structure (200, 300, 400, 500, 600, 700, 800), comprising: a sampling line (210, 310, 410, 510, 610, 710, 810) with a branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812); a data line (220, 320, 420, 520, 620, 720, 820); a pixel electrode (240, 340, 440, 540, 640, 740, 840); a semiconductor pattern (230, 330, 430, 530, 630, 730, 830) that intersects the scanning line (210, 310, 410, 510, 610, 710, 810) and the branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812), the semiconductor pattern includes (230, 330, 430, 530, 630, 730, 830): one of the first channel ranges (231, 331, 431, 531, 631, 731, 831) corresponding to the sampling line (210, 310, 410, 510, 610, 710, 810), which is electrically connected to the data line (220, 320, 420, 520, 620, 720, 820); a second channel area (232, 332, 432, 532, 632, 732, 832) corresponding to the branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812), which is electrically connected to the pixel electrode (240, 340, 440, 540, 640, 740, 840); and doping areas (235A, 235B, 235C) arranged on two sides of the first channel area (231, 331, 431, 531, 631, 731, 831) and on two sides of the second channel area (232, 332, 432, 532, 632, 732, 832), where the width of the second channel area (232, 332, 432, 532, 632, 732, 832) is smaller than the width of the first channel area (231, 331, 431, 531, 631, 731, 831).

Description

TECHNICAL AREA

[0001] The present disclosure relates to the technical field of crystal displays, and more particularly to a pixel structure and a display device. BACKGROUND

[0002] With the rapid development of display technology, high PPI (pixels per inch) and even excessively high PPI have become an inevitable development. Image resolution is generally expressed in PPI (number of pixels per inch), and the higher the PPI value, the higher the density of the display screen (pixels) for displaying an image. The higher the PPI of the screen, the more details a displayed image will contain and the higher the accuracy will be. However, with the improvement of the PPI of the screen, more and more pixels are arranged more closely, the size of each pixel must become smaller and smaller, which not only poses great challenges to the design of the device, but also brings many difficulties.

[0003] Among many technical problems that limit high-PPI technology, insufficient charging capacity is one of the reasons that challenge high-PPI technology. The main factors that limit high-PPI charging capacity can be: a heavy load of an LCD panel, a short pixel charging time, the presence of a pass-through voltage, and a limited pixel width-to-length ratio, etc., where pass-through is important for high-PPI technology with a small pixel storage capacity (less than 32fF), as in Fig. 1 shown.

[0004] There are several methods for reducing the pixel's throughput voltage: narrowing the pixel pattern width and the pixel pattern channel width, narrowing the capacitance of the gate oxide layer in the pixel pattern, narrowing the voltage difference of a thin-film transistor (TFT) when the liquid crystal display is turned on and off, and increasing the memory capacity of the pixel pattern. However, for a high-PPI product, it is difficult to increase the memory capacity of the pixel pattern because the distance between pixels is very small. Narrowing the pixel pattern channel width or narrowing the thin-film transistor (TFT) voltage difference when the liquid crystal display is turned on and off will further reduce the memory capacity.Reducing the capacitance of the gate oxide layer of the pixel structure means increasing the film thickness or reducing the dielectric coefficient. This leads to a reduction in the device's miniaturization and will reduce the device's on-state current. As a result, it will reduce the charging capacity. Reducing the channel width of the pixel structure can reduce the through-voltage and improve charging capability. However, it will cause other problems, such as increased gate delay and unequal charging capability on the left and right sides of the panel.

[0005] From US 2009 / 0 173 942 A1 a pixel structure is known, comprising a scanning line with a branching structure, a semiconductor structure which intersects the scanning line and the branching structure, wherein the semiconductor pattern comprises a first channel region corresponding to the scanning line and a second channel region corresponding to the branching structure.

[0006] From US 2011 / 0 198 607 A1 a pixel structure is known, comprising a scanning line with a branching structure, a semiconductor structure which intersects the scanning line and the branching structure, wherein the semiconductor pattern comprises a first channel region corresponding to the scanning line, a second channel region corresponding to the branching structure, and doping regions arranged on two sides of the first channel region and on two sides of the second channel region.

[0007] Therefore, a method and structure for reducing a through voltage are required.

[0008] The above-described information disclosed in the Background section is for the sole purpose of enhancing the understanding of the background of the invention and thus may include information that does not constitute prior art known to those skilled in the art. SUMMARY

[0009] The present disclosure provides a pixel structure that can reduce the forward voltage without increasing the gate delay. It can improve the device's charging capacity and the display performance of the display panel.

[0010] Other features and advantages of the present disclosure may be apparent from the following detailed description and may be learned in part by practicing the present disclosure.

[0011] According to one aspect of the present disclosure, a pixel structure is provided comprising a scan line having a branching structure, a data line, a pixel electrode, and a semiconductor pattern, wherein the semiconductor pattern intersects the scan line and the branching structure. The semiconductor pattern includes: a first channel region corresponding to the scan line and electrically connected to the data line; a second channel region corresponding to the branching structure and electrically connected to the pixel electrode; and impurity regions respectively disposed on two sides of the first channel region and on two sides of the second channel region, wherein a width of the second channel region is smaller than a width of the first channel region.

[0012] In an exemplary embodiment of the present disclosure, the branching structure is an L-shaped branch.

[0013] In an exemplary embodiment of the present disclosure, the semiconductor pattern includes a linear portion, the second portion of the L-shaped branch intersects with the first portion of the L-shaped branch, the second portion of the L-shaped branch intersects perpendicularly with the linear portion of the semiconductor pattern.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor pattern includes a linear portion, the second portion of the L-shaped branch and the scanning line intersect perpendicularly with the linear portion.

[0015] In an exemplary embodiment of the present disclosure, the branching structure extends perpendicularly from the scan line.

[0016] In an exemplary embodiment of the present disclosure, the semiconductor pattern includes at least a first portion and a second portion, the first portion intersects perpendicularly with the scan line and the second portion intersects perpendicularly with the branch structure.

[0017] In an exemplary embodiment of the present disclosure, the width of the second channel region is 1 / 5 to 4 / 5 of the width of the first channel region.

[0018] In an exemplary embodiment of the present disclosure, the semiconductor pattern comprises a polysilicon pattern.

[0019] In an exemplary embodiment of the present disclosure, the width of the pixel structure is less than 15µm.

[0020] In an exemplary embodiment of the present disclosure, wherein the pixel structure has a pixel storage capacitance of less than 150 fF.

[0021] According to another aspect of the present disclosure, a display device is provided having a pixel structure according to any embodiment of the above aspect.

[0022] According to the pixel structure of the present disclosure, the through-voltage can be reduced without increasing the gate delay. Furthermore, the charging capacity of the device can be improved, and the display performance of the display panel can be improved.

[0023] It is to be understood that the above general description and the following detailed description are merely illustrative rather than limiting of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present disclosure will become more apparent from exemplary embodiments described in detail with reference to the accompanying drawings. Fig. Figure 1 shows a schematic graph of how a forward voltage influences the charging capacity of a pixel. Fig. 2 is a schematic diagram of a pixel structure according to an exemplary embodiment of the present disclosure. Fig. 3 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. 4 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig.5 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. 6 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. 7 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. 8 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. 9 is a schematic cross-sectional view of a pixel structure according to an exemplary embodiment of the present disclosure. Fig. 10 is a simulation circuit diagram of a pixel structure according to an exemplary embodiment of the present disclosure. Fig.11 is a simulation circuit diagram of a pixel structure according to another exemplary embodiment of the present disclosure. Fig. Figure 12 is a graph of the positive frame charge of a simulation circuit of a pixel as shown in Fig. 6 and Fig. 7 according to an embodiment of the present disclosure. Fig. Figure 13 is a graph of the charge of a negative frame charge of a simulation circuit of a pixel as shown in the Fig. 6 and Fig. 7 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Now, the exemplary embodiments will be fully described with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in various forms and should not be construed as limited to the examples set forth herein. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The accompanying drawings are merely schematic representations of the present disclosure and may not be drawn to scale. Like reference numerals in the drawings represent the same or similar components, and their descriptions are omitted.

[0026] In addition, the features, structures, or properties described herein may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to help understand embodiments of the present disclosure. However, it will be understood by those skilled in the art that the technical solution of the present disclosure may be practiced without one or more of the specific details or may use other components, devices, etc. In other situations, structures, devices, or materials that are well known are not shown or described in detail so as not to obscure aspects of the present disclosure.

[0027] Fig. 2 is a schematic diagram of a pixel structure according to an exemplary embodiment of the present disclosure.

[0028] As in Fig.2, a pixel structure 200 according to an exemplary embodiment includes a scan line 210, a data line 220 intersecting the scan line 210, a semiconductor pattern 230, and a transparent pixel electrode 240. The pixel structure 200 may be arranged on a substrate (not shown). In Fig. 2, the semiconductor pattern 230 is arranged below the scan line 210, and the data line 220 is arranged below the scan line 210. However, the present disclosure is not limited thereto.

[0029] The semiconductor pattern 230 also includes a drain electrode contact 233 and a source electrode contact 234.

[0030] As in Fig. 2, the scan line 210 has a branching structure 211. The branching structure 211 extends vertically from the scan line 210. However, the present disclosure is not limited thereto.

[0031] The semiconductor pattern 230 intersects with the scan line 210 and the branching structure 211, respectively. The semiconductor pattern 230 includes a first channel region 231 corresponding to the scan line 210, a second channel region 232 corresponding to the branching structure 211, doping regions 235A, 235B, and 235C on both sides of the first channel region 231 and on both sides of the second channel region 232, respectively.

[0032] As in Fig. 2, the first channel region 231, the second channel region 232 and the doping regions 235A, 235B and 235C as well as the portions of the scan line 210 and the branch structure 211 that correspond to the first channel region 231, the second channel region 232 may be configured to form a multi-channel thin film transistor 230.

[0033] According to an exemplary embodiment, an asymmetric double-gate (or multi-gate) structure is provided. For example, as shown in Fig.As shown in Figure 2, the branching structure 211 intersecting the semiconductor pattern 230 has a width L2 that is smaller than a width L1 of the scan line 210. Since the first channel region 231 corresponds to the scan line 210, the first channel region 231 has a width equal to the width L1 of the scan line 210. In the present embodiment, L1 represents the width of the first channel region 231 or the width of the scan line 210. Since the second channel region 232 corresponds to the branch structure 211, the second channel region has a width equal to the width L2 of the branch structure 211. In the present embodiment, L2 represents the width of the second channel region 232 or the width of the branch structure 211. That is, the width of the second channel region 232 is smaller than the width of the first channel region 231. Therefore, the width of another channel region can be reduced without changing the width of the scan line.In this way, the stray capacitance can be reduced and the forward voltage can be lowered without increasing the gate delay.

[0034] In the embodiments of the present disclosure, the width mentioned herein is for convenience of description only, rather than limiting the present disclosure. In the embodiments of the present disclosure, the terms "length" and "width" may be used interchangeably.

[0035] In some embodiments, the width of the second channel region 232 is L2, as shown in Fig. 2, which can be 1 / 5 to 4 / 5 of L1, as in Fig.2, where L1 is the width of the first channel region 231. This can achieve a desired balance between performance and cost. It should be understood that the present disclosure is not limited thereto, and the width of the second channel region 232 can be smaller. As long as the manufacturing technology allows it and it does not cause the TFT device to fail, the width of the second channel region 232 can be even smaller.

[0036] In some embodiments, the semiconductor pattern 230 may be made of polysilicon material, for example. That is, the semiconductor pattern 230 may be a polysilicon pattern.

[0037] In an exemplary embodiment, as in Fig.As shown in Figure 2, the pixel structure 200 may also include the drain electrode contact 233 and the source electrode contact 234. The data line 220 may be electrically connected to the source electrode contact 234. The transparent pixel electrode 240 may be electrically connected to the drain electrode contact 233.

[0038] In an exemplary embodiment, as in Fig. 2, the semiconductor pattern 230 may also include a capacitor electrode 237.

[0039] In an exemplary embodiment, the width L2 of the second channel region 232 is smaller than the width L1 of the first channel region 231. This can effectively reduce the stray capacitance in the pixel structure. Therefore, the pixel structure in the exemplary embodiment can be applicable in situations where the pixel structure has a narrow width and the pixel storage capacity is low. For example, in some embodiments, the width of the pixel structure can be less than 15 µm. For another example, in some embodiments, the value of the pixel storage capacity can be less than 150 fF. This is difficult to achieve with conventional technology. Therefore, the pixel structure of the embodiment of the present disclosure is applicable to high-PPI technology that has a low pixel storage capacity.It can effectively improve the loading capacity of a high-PPI display screen, and thereby improve the overall performance of the display.

[0040] Fig. 3 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure.

[0041] As in Fig. 3, a pixel structure 300 includes a scan line 310, a data line 320, a semiconductor pattern 330, and a transparent pixel electrode 340.

[0042] The pixel structure of the exemplary embodiment as shown in Fig. 3 is essentially the same as the pixel structure shown in Fig. 2, except that the semiconductor pattern 330 and the extending directions of the scanning line 310 and the branching structure 311 are different from those in Fig.2. In this regard, the semiconductor pattern 330 includes: a first channel region 331 corresponding to the scan line 310, and a second channel region 332 corresponding to the branch structure 311.

[0043] Fig. 4 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure.

[0044] As in Fig. 4, a pixel structure 400 includes a scan line 410, a data line 420, a semiconductor pattern 430, and a transparent pixel electrode 440. Fig. 4 differs from Fig. 2 in that the branching structure 411 has an “L” shape and the semiconductor pattern 430 comprises a linear section Q. In Fig.4, a second portion L2 of the L-shaped branching structure 411 intersects a first portion L1 of the L-shaped branching structure 411, and the second portion L2 of the L-shaped branching structure 411 intersects perpendicularly with a linear portion Q of the semiconductor pattern 430. However, the present disclosure is not limited thereto. The semiconductor pattern 430 intersects with the scan line 410 and the branching structure 411, respectively. In this regard, the semiconductor pattern 430 includes a first channel region 431 corresponding to the scan line 410 and a second channel region 432 corresponding to the branching structure 411. A description of parts in Fig. 4, which are the same as in Fig. 2 will not be repeated.

[0045] Fig. 5 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. As in Fig.5, a pixel structure 500 includes a scanning line 510, a data line 520, a semiconductor pattern 530, and a transparent pixel electrode 540. A description of parts in Fig. 5, which are the same as in Fig. 2 will not be repeated.

[0046] Fig. 5 differs from Fig. 2 in that the semiconductor pattern 530 comprises an L-shaped structure. One side of the L-shaped structure included in the semiconductor pattern 530 intersects with the scan line 510, and the other side of the L-shaped structure included in the semiconductor pattern 530 intersects with the branch structure 511. In this regard, the semiconductor pattern 530 includes: a first channel region 531 corresponding to the scan line 510 and a second channel region 532 corresponding to the branch structure 511.

[0047] Fig.6 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. As in Fig. 6, a pixel structure 600 includes a scanning line 610, a data line 620, a semiconductor pattern 630, and a transparent pixel electrode 640. A description of parts in Fig. 6, which are the same as in Fig. 2 will not be repeated.

[0048] Fig. 6 differs from Fig.2 in that a second portion L2 of an L-shaped branching structure 611 intersects a first portion L1 of the branching structure 611, and the second portion L2 of the L-shaped branching structure 611 intersects the semiconductor pattern 630. The semiconductor pattern 630 intersects with the scan line 610 and the branching structure 611, respectively. In this regard, the semiconductor pattern 630 includes a first channel region 631 corresponding to the scan line 610 and a second channel region 632 corresponding to the branching structure 611. The first channel region 631 and the second channel region 632 are all under the data line 620. However, the present disclosure is not limited thereto.

[0049] Fig. 7 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. As in Fig.7, a pixel structure 700 includes a scanning line 710, a data line 720, a semiconductor pattern 730, and a transparent pixel electrode 740. A description of parts in Fig. 7, which are the same as in Fig. 2 will not be repeated.

[0050] As in Fig. As shown in Figure 7, the scan line 710 includes branching structures 711 and 712. Each of the branching structure 711 and the branching structure 712 extends perpendicularly from the scan line 710. However, the present disclosure is not limited thereto.

[0051] The semiconductor pattern 730 intersects with the scan line 710 and the branching structures 711 and 712. In this regard, the semiconductor pattern 730 includes: a first channel region 731 corresponding to the scan line 710, a second channel region 732 corresponding to the branching structure 711, and a third channel region 733 corresponding to the branching structure 712. Wherein, the width of the scan line 710 is the width L1" of the first channel region; the width of the branching structure 711 is the width L2" of the second channel region; the width of the branch structure 712 is the width L3" of the third channel region. Doping regions 735A and 735B are respectively arranged on the two sides of the first channel region 731; doping regions 735B and 735C are respectively arranged on the two sides of the second channel region 732; and doping regions 735C and 735D are respectively arranged on the two sides of the third channel region 733.

[0052] As in Fig. 7, the first channel region 731, the second channel region 732, the third channel region 733 and the doping regions 735A, 735B, 735C and 735D as well as the portions of the scan line 710, the branch structure 711 and the branch structure 712 corresponding to the first channel region 731, the second channel region 732 and the third channel region 733, respectively, may be formed to form a multi-channel (multi-gate) thin film transistor 730.

[0053] According to the embodiment, an asymmetric multi-gate structure is provided. For example, as shown in Fig.7, at least one of the branch structure 711 and the branch structure 712, each intersecting the semiconductor pattern 730, has a width less than a width L1" of the scan line 710. That is, at least one of the width L2" of the second channel region 732 and the width L3" of the third channel region 733 is less than the width of the first channel region 731. In this way, the width of at least one channel region can be reduced without changing the width of the scan line. In this way, the stray capacitance can be reduced and the forward voltage can be lowered without increasing the gate delay.

[0054] Fig. 8 is a schematic diagram of a pixel structure according to another exemplary embodiment of the present disclosure. As in Fig.8, a pixel structure 800 includes a scanning line 810, a data line 820, a semiconductor pattern 830, and a transparent pixel electrode 840. A description of parts in Fig. 8, which are the same as in Fig. 7 will not be repeated.

[0055] Fig. 8 differs from Fig.7 in that the scan line 810 includes a branching structure 811 and a branching structure 812. In the embodiment, the branching structure 812 is an L-shaped branching structure, and each of the branching structure 811 and the branching structure 812 extends perpendicularly from the scan line 810. However, the present disclosure is not limited thereto. A second portion L2 of the L-shaped branching structure 812 intersects with a first portion L1 of the branching structure 812. The second portion L2 of the L-shaped branching structure 812 intersects perpendicularly with a linear portion of the semiconductor pattern 830. The semiconductor pattern 830 intersects each of the scan line 810, the branching structure 811, and the branching structure 812.In this regard, the semiconductor pattern 830 includes: a first channel region 831 corresponding to the scan line 810, a second channel region 832 corresponding to the branch structure 811, and a third channel region 833 corresponding to the branch structure 812.

[0056] Fig. 9 is a schematic cross-sectional view of a pixel structure according to an exemplary embodiment of the present disclosure. As in Fig. 9A, the pixel in the cross-sectional view of the pixel includes a scan line layer 902, an insulating layer 904, and an active source layer 906. In an exemplary embodiment, the scan line layer may include a scan line 9021 and a scan line branching structure 9023. As shown in Fig.As shown in Figure 9B, the pixel includes a scan line layer 902', an insulating layer 904', and an active source layer 906' in the cross-sectional view of the pixel. In an exemplary embodiment, the scan line layer in the cross-sectional view may also include a scan line 9021' and a scan line branching structure 9023'.

[0057] Fig. 10 is a simulation circuit diagram of a pixel structure according to an exemplary embodiment of the present disclosure.

[0058] As shown in a circuit diagram 100 of Fig. 10, the values ​​are a negative frame voltage, C1 is a pixel storage capacitance, and TFT1 and TFT2 are equivalent circuits formed by the semiconductor circuit in the pixel structure of the present disclosure.

[0059] With reference to the example as in Fig.2, for example, it can be assumed that an on-voltage VGH of the thin-film transistor (TFT) is 10 V, an off-voltage VGL of the thin-film transistor (TFT) is -7 V, a negative frame voltage value is -5 V, and a pixel storage capacitance is 32 fF. The width of the scan line 210, i.e., the width L1 of the first channel region 231, as discussed above, is 2 µm. The width of the branch structure 211 of the scan line, i.e., the width L2 of the second channel region 232, as discussed above, is 3 µm, 2 µm, and 1 µm. The results of the simulation of the positive frame voltage in the embodiment of Fig. 6 are as shown in the following table, and as in Fig. 13 shown: Width of the second channel Voltage at full charge Voltage after through-voltage loss Charging current 3µm 5.00 V 4.789 V 95.78% 2µm 5.00 V 4.804 V 96.08% 1µm 5.00 V 4.821 V 96.42%

[0060] With reference to the example as in Fig.3, for example, it can be assumed that an on-voltage VGH of the thin-film transistor (TFT) is 10 V, an off-voltage VGL of the thin-film transistor (TFT) is -7 V, a negative frame voltage value is -5 V, and a pixel storage capacitance is 32 fF. The width of the scan line 310, i.e., the width L1' of the first channel region 331, as discussed above, is 2 µm. The width of the branch structure 311 of the scan line, i.e., the width L2' of the second channel region 332, as discussed above, is 3 µm, 2 µm, and 1 µm. Results of the positive frame voltage simulation in the embodiment of Fig. 6 are as shown in the following table, and as in Fig. 12 shown: Width of the second channel Voltage at full charge Voltage after through-voltage loss Charging current 3µm 5.00 V 4.789 V 95.78% 2µm 5.00 V 4.826 V 96.52% 1µm 5.00 V 4.856 V 97.12%

[0061] In a positive frame voltage simulation of the pixel structure, the goal is to reduce a pass voltage as much as possible, ie, to keep the voltage value after the pass voltage loss close to a standard voltage value of 5V.

[0062] From the results, it can be seen that if the branching structure of the scan line in the pixel structure has a different scan line width, it can affect the positive frame charge capacity of the entire pixel. The wider the branching structure of the scan line, the weaker the charge capacity of the entire pixel structure, and it means that the resulting voltage after the pixel structure is charged deviates more from 5V. In the present embodiment, the result of a positive frame voltage simulation of such a pixel structure, according to the embodiment in which the width of the scan line is larger than the width of the branching structure of the scan line (that is, the embodiment in which the width of the first channel region is larger than the width of the second channel region), can effectively reduce the feedthrough voltage and improve the charge capacity of the device.

[0063] Fig. 11 is a simulation circuit diagram of another pixel structure according to an exemplary embodiment of the present disclosure.

[0064] In the circuit diagram 120 as in Fig. 11, the values ​​are a negative frame voltage, C2 is a pixel storage capacitance, TFT1 and TFT2 are equivalent circuits formed by the semiconductor circuit in the pixel structure disclosed by the present disclosure.

[0065] With reference to the example as in Fig.2, for example, it can be assumed that an on-voltage VGH of the thin-film transistor (TFT) is 10 V, an off-voltage VGL of the thin-film transistor (TFT) is -7 V, a negative frame voltage value is -5 V, and a pixel storage capacitance is 32 fF. The width of the scan line 210, i.e., the width L1 of the first channel region 231, as discussed above, is 2 µm. The width of the branch structure 211 of the scan line, i.e., the width L2 of the second channel region 232, as discussed above, is 3 µm, 2 µm, and 1 µm. The results of the negative frame voltage simulation in the embodiment of the Fig. 7 are as shown in the following table, and as in Fig. 13 shown: Width of the second channel Voltage at full charge Voltage after through-voltage loss Charging current 3µm -5.00 -5.228 104.56% 2µm -5.00 -5.169 103.38% 1µm -5.00 -5.110 102.20%

[0066] With reference to the example as in Fig.3, for example, it can be assumed that an on-voltage VGH of the thin-film transistor (TFT) is 10 V, an off-voltage VGL of the thin-film transistor (TFT) is -7 V, a negative frame voltage value is -5 V, and a pixel storage capacitance is 32 fF. The width of the scan line 310, i.e., the width L1' of the first channel region 331, as discussed above, is 2 µm. The width of the branch structure 311 of the scan line, i.e., the width L2' of the second channel region 332, as discussed above, is 3 µm, 2 µm, and 1 µm. The results of the negative image voltage simulation in the embodiment of the Fig. 7 are as shown in the following table, and as in Fig. 13 shown: Width of the second channel Voltage at full charge Voltage after through-voltage loss Charging current 3µm -5.00 -5.228 104.56% 2µm -5.00 -5.142 102.84% 1µm -5.00 -5.084 101.68%

[0067] In a negative frame voltage simulation of the pixel structure, the goal is to reduce a pass voltage, that is, to keep the voltage value after the pass voltage loss close to a standard voltage value of -5 V.

[0068] From the results, it can be seen that when the pixel structure, the branching structure of the scanning line has a different scanning line width, it can affect the negative frame voltage capacity of the entire pixel. The wider the branching structure of the scanning line, the weaker the charging capability of the entire pixel structure becomes, and it means that the resulting voltage after the pixel structure is charged deviates more from -5V. In the present embodiment, the result of negative frame voltage simulation of such a pixel structure according to the embodiment in which the width of the scanning line is larger than the width of the branching structure of the scanning line (that is, the embodiment in which the width of the first channel region is larger than the width of the second channel region) can effectively lower the through-voltage and improve the charging capability of the device.

[0069] From the above detailed description, one skilled in the art should understand that the pixel structure according to embodiments of the present disclosure may have one or more of the following advantages.

[0070] According to embodiments of the present disclosure, the forward voltage can be lowered without increasing the gate delay. Furthermore, the charging capacity of the device can be improved, and the display performance of the display panel can be improved.

[0071] The embodiments of the present disclosure have been illustrated and described in detail. It should be understood that the present disclosure is not limited to the detailed structure, arrangement, and embodiment described herein. Rather, the present disclosure is intended to cover various modifications and equivalents falling within the scope of the appended claims.

Claims

[1] A pixel structure (200, 300, 400, 500, 600, 700, 800) comprising: a scan line (210, 310, 410, 510, 610, 710, 810) having a branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812); a data line (220, 320, 420, 520, 620, 720, 820); a pixel electrode (240, 340, 440, 540, 640, 740, 840); a semiconductor pattern (230, 330, 430, 530, 630, 730, 830) intersecting with the scanning line (210, 310, 410, 510, 610, 710, 810) and the branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812), wherein the semiconductor pattern (230, 330, 430, 530, 630, 730, 830) comprises: a first channel region (231, 331, 431, 531, 631, 731, 831) corresponding to the scanning line (210, 310, 410, 510, 610, 710, 810) and electrically connected to the data line (220, 320, 420, 520, 620, 720, 820); a second channel region (232, 332, 432, 532, 632, 732, 832) corresponding to the branching structure (211, 311, 411, 511, 611, 711, 712, 811, 812) and electrically connected to the pixel electrode (240, 340, 440, 540, 640, 740, 840); and doping regions (235A, 235B, 235C) arranged on two sides of the first channel region (231, 331, 431, 531, 631, 731, 831) and on two sides of the second channel region (232, 332, 432, 532, 632, 732, 832), wherein a width of the second channel region (232, 332, 432, 532, 632, 732, 832) is smaller than a width of the first channel region (231, 331, 431, 531, 631, 731, 831). [2] The pixel structure (400, 600, 800) according to claim 1, characterized by that the branching structure (411, 611, 711, 812) is an L-shaped branch. [3] The pixel structure (400, 600, 800) according to claim 2, characterized byin that the L-shaped branch comprises a first section (L1) and a second section (L2), the first section (L1) extending perpendicularly from the scanning line (410, 610, 810) and the second section (L2) intersecting perpendicularly with the semiconductor pattern (430, 630, 830). [4] The pixel structure (400, 600, 800) according to claim 2, characterized by in that the semiconductor pattern (430, 630, 830) comprises a linear part (Q), the second section (L2) of the L-shaped branch intersects with the first section (L1) of the L-shaped branch and the second section (L2) of the L-shaped branch intersects perpendicularly with the linear section of the semiconductor pattern (430, 630, 830). [5] The pixel structure (200, 300, 400, 500, 600, 700, 800) according to claim 1, characterized by that the branching structure (811, 812) extends perpendicularly from the scanning line (810). [6] The pixel structure (200, 300, 500, 600, 700, 800) according to claim 5, characterized byin that the semiconductor pattern (230, 330, 530, 630, 730, 830) has at least a first section (L1) and a second section (L2), the first section (L1) intersects perpendicularly with the scan line (210, 310, 510, 610, 710, 810), and the second section (L2) intersects perpendicularly with the branching structure (211, 311, 511, 611, 711, 712, 811, 812). [7] The pixel structure (200, 300, 400, 500, 600, 700, 800) according to claim 1, characterized by that the width of the second channel area (232, 332, 432, 532, 632, 732, 832) is 1 / 5 to 4 / 5 of the width of the first channel area (231, 331, 431, 531, 631, 731, 831). [8] The pixel structure (200, 300, 400, 500, 600, 700, 800) according to claim 1, characterized by that the semiconductor pattern (230, 330, 430, 530, 630, 730, 830) has a polysilicon pattern. [9] The pixel structure (200, 300, 400, 500, 600, 700, 800) according to claim 1, characterized bythat the width of the pixel structure (200, 300, 400, 500, 600, 700, 800) is less than 15µm. [10] The pixel structure (200, 300, 400, 500, 600, 700, 800) according to claim 1, characterized by that the pixel structure (200, 300, 400, 500, 600, 700, 800) has a pixel storage capacity of less than 150 fF. [11] A display device comprising a pixel structure (200, 300, 400, 500, 600, 700, 800) according to any one of claims 1-10.

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