EUV mask with tantalum-based absorber alloy and method for manufacturing such an EUV mask

Abstract

EUV mask (100) comprising: a substrate (102); a reflective multilayer stack (110) on the substrate (102); and a structured absorber layer (140P) on the reflective multilayer stack (110), wherein the structured absorber layer (140P) is a single layer and contains an alloy with tantalum (Ta) and at least one alloying element, wherein the at least one alloying element contains at least one transition metal element selected from: titanium (Ti), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), platinum (Pt), gold (Au) and alloys thereof.

Description

PRIORITY CLAIMS AND CROSS-REFERENCES

[0001] This application claims priority over the preliminary US patent application 63 / 108,187, filed on October 30, 2020, which is incorporated herein by reference. BACKGROUND

[0002] The semiconductor industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of integrated circuits (ICs), each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production output and reducing associated costs. List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a sectional view of an extreme ultraviolet (EUV) mask according to a first embodiment. Fig. Figure 2 shows a flowchart of a procedure for producing the EUV mask of Fig. 1 according to some embodiments. The Fig. 3A-3L show sectional views of an EUV mask at various stages of the manufacturing process. Fig. 2 according to some embodiments. Fig. Figure 4 shows a sectional view of an EUV mask according to a second embodiment. Fig. Figure 5 shows a flowchart of a process for manufacturing the EUV mask from Fig. 4 according to some embodiments. The Fig. Figures 6A-6J show sectional views of an EUV mask at various stages of the manufacturing process. Fig. 5 according to some embodiments. DETAILED DESCRIPTION

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves for simplicity and clarity and does not fundamentally prescribe a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] In the manufacture of integrated circuits (ICs), structures representing different layers of the IC are produced using a series of reusable photomasks (hereinafter also referred to as photolithography masks or masks) to transfer the design of each layer of the IC onto a semiconductor substrate during the semiconductor device manufacturing process.

[0007] Due to the miniaturization of integrated circuits (ICs), extreme ultraviolet (EUV) light with a wavelength of 13.5 nm is used, for example, in lithographic processes to transfer very small structures (e.g., nanometer-scale structures) from a mask to a semiconductor wafer. Since most materials are highly absorbing at a wavelength of 13.5 nm, EUV lithography uses a reflective EUV mask. This mask has a reflective multilayer to reflect the incident EUV light and an absorber layer on top of the reflective multilayer to absorb radiation in areas where light should not be reflected by the mask. The mask structure is defined by the absorber layer and is transferred to a semiconductor wafer by the reflection of EUV light from portions of the reflective surface of the EUV mask.

[0008] In EUV lithography, the EUV mask is illuminated with obliquely incident light, inclined at an angle of 6 degrees to the normal, to separate the reflected light from the incident light. The obliquely incident EUV light is reflected by the reflective multilayer or absorbed by the absorber layer. During EUV lithography, a shadow can form if the absorber layer is thick. These mask shadowing effects, also known as mask 3D effects, can lead to undesirable shifts in focus and structure positioning, depending on the structure element size. Mask 3D effects worsen with the advancement of the technology nodes.

[0009] In embodiments of the present disclosure, tantalum(Ta)-based alloys with a high extinction coefficient κ in the EUV wavelength range are developed. In some embodiments, the Ta-based alloy comprises Ta and an alloying element, such as a transition metal element or an element of Group 14. By using these tantalum(Ta)-based alloys as absorber materials in EUV masks or mask blanks, a thinner absorber can be used to reduce mask 3D effects and exposure energy. This improves scanner throughput. In some embodiments, the tantalum(Ta)-based alloys can be doped with an interstitial element, such as nitrogen (N), oxygen (O), carbon (C), or boron (B), to increase the density of the absorber material.

[0010] Fig. Figure 1 is a sectional view of an EUV mask 100 according to a first embodiment of the present disclosure. With reference to Fig. Figure 1 of the EUV mask 100 comprises the following: a substrate 102, a reflective multilayer stack 110 over a front face of the substrate 102, a cover layer 120 over the reflective multilayer stack 110, a structured buffer layer 130P over the cover layer 120, and a structured absorber layer 140P over the structured buffer layer 130P. The EUV mask 100 further comprises a conductive layer 104 over a back face of the substrate 102 opposite the front face.

[0011] The structured absorber layer 140P and the structured buffer layer 130P have a structure of openings 152 that correspond to the circuit structures to be fabricated on a semiconductor wafer. The structure of openings 152 is located in a feature area 100A of the EUV mask 100, which exposes a surface of the cover layer 120. Feature area 100A is enclosed by a peripheral area 100B of the EUV mask 100. The peripheral area 100B corresponds to an unstructured area of ​​the EUV mask 100 that is not used in an exposure process during IC fabrication. In some embodiments, the structural area 100A of the EUV mask 100 is located in a central region of the substrate 102, and the peripheral area 100B is located at an edge portion of the substrate 102. The structural area 100A is separated from the peripheral area 100B by grooves 154.The trenches 154 extend through the structured absorber layer 140P, the structured buffer layer 130P, the cover layer 120 and the reflective multilayer stack 110, exposing the front of the substrate 102.

[0012] Fig. Figure 2 is a flowchart of a process 200 for manufacturing an EUV mask, for example an EUV mask 100, according to some embodiments. Fig. 3A to Fig. Figures 3L are sectional views of the EUV mask 100 at various stages of the manufacturing process according to some embodiments. Method 200 is discussed in detail below with reference to the EUV mask 100. In some embodiments, additional steps are performed before, during, and / or after Method 200, or some of the described steps are replaced and / or omitted. In some embodiments, some of the structural elements described below are replaced or omitted. Although some embodiments are discussed with steps performed in a specific order, a person skilled in the art should recognize that these steps can also be performed in a different logical sequence.

[0013] With reference to the Fig. 2 and Fig. 3A comprises the method 200 a step 202 in which, according to some embodiments, a reflective multilayer stack 110 is produced over a substrate 102. Fig. Figure 3A is a sectional view of an initial structure of an EUV mask 100 after fabrication of the reflective multilayer stack 110 over the substrate 102 according to some embodiments.

[0014] With reference to Fig. 3A The initial structure of the EUV mask 100 comprises a substrate 102 made of glass, silicon, or other materials with low thermal expansion. The low thermal expansion material helps to minimize image distortion resulting from heating of the mask during use. In some embodiments, the substrate 102 contains quartz, fused silica, calcium fluoride, silicon carbide, black diamond, or titanium oxide-doped silicon dioxide (SiO2 / TiO2). In some embodiments, the substrate 102 has a thickness ranging from 1 mm to approximately 7 mm. If the thickness of the substrate 102 is too small, the risk of breakage or deformation of the EUV mask 100 increases in some instances. Conversely, if the thickness of the substrate is too large, the weight of the EUV mask 100 is unnecessarily increased in some instances.

[0015] In some embodiments, a conductive layer 104 is arranged on the back side of the substrate 102. In some embodiments, the conductive layer 104 is in direct contact with the back side of the substrate 102. The conductive layer 104 is adapted to provide electrostatic coupling of the EUV mask 100 to an electrostatic mask mounting device (not shown) during the fabrication and use of the EUV mask 100. In some embodiments, the conductive layer 104 contains chromium nitride (CrN) or tantalum boride (TaB). In some embodiments, the conductive layer 104 is produced by a deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The thickness of the conductive layer 104 is controlled such that the conductive layer 104 is optically transparent.

[0016] The reflective multilayer stack 110 is arranged over a front face of the substrate 102 opposite the back face. In some embodiments, the reflective multilayer stack 110 is in direct contact with the front face of the substrate 102. The reflective multilayer stack 110 offers high reflectivity towards EUV light. In some embodiments, the reflective multilayer stack 110 is configured to achieve a reflectivity of approximately 60% to approximately 75% at the maximum EUV illumination wavelength, e.g., EUV illumination at 13.5 nm. In particular, when the EUV light is applied to the surface of the reflective multilayer stack 110 at an angle of incidence of 6°, the maximum reflectivity of light near a wavelength of 13.5 nm is approximately 60%, 62%, 65%, 68%, 70%, 72%, or 75%.

[0017] In some embodiments, the reflective multilayer stack 110 comprises alternating stacked layers of a material with a high refractive index and a material with a low refractive index. On the one hand, a material with a high refractive index tends to scatter EUV light, and on the other hand, a material with a low refractive index tends to transmit EUV light. A pairing of these two types of materials provides resonant reflection. In some embodiments, the reflective multilayer stack 110 comprises alternating stacked layers of molybdenum (Mo) and silicon (Si). In some embodiments, the reflective multilayer stack 110 comprises alternating stacked Mo and Si layers, with Si in the topmost layer. In some embodiments, a molybdenum layer is in direct contact with the front face of the substrate 102.In some other embodiments, a silicon layer is in direct contact with the front face of the substrate 102. Alternatively, the reflective multilayer stack 110 has alternating stacked layers of Mo and beryllium (Be).

[0018] The thickness of each layer in the reflective multilayer stack 110 depends on the EUV wavelength and the angle of incidence of the EUV light. The thickness of the alternating layers in the reflective multilayer stack 110 is tuned to maximize the constructive interference of the EUV light reflected at each interface and to minimize the overall absorption of the EUV light. In some embodiments, the reflective multilayer stack 110 comprises 30 to 60 pairs of alternating Mo and Si layers. Each Mo / Si pair has a thickness in the range of approximately 2 nm to approximately 7 nm, with a total thickness in the range of approximately 100 nm to approximately 300 nm.

[0019] In some embodiments, each layer in the reflective multilayer stack 110 is deposited over the substrate 102 and an underlying layer by ion beam deposition (IBD) or direct current magnetron sputtering. The deposition method used helps to ensure that the thickness uniformity of the reflective multilayer stack 110 is better than approximately 0.85 across the substrate 102. For example, to fabricate a reflective Mo / Si multilayer stack 110, a Mo layer is deposited using a Mo target as the sputtering target and an argon (Ar) gas (with a gas pressure of 1.3 × 10⁻⁶). -2 Pa up to 2.7×10 -2 Pa) as the sputtering gas with an ion acceleration voltage of 300 V to 1,500 V at a deposition rate of 0.03 to 0.30 nm / s, and then a Si layer is deposited with a Si target as the sputtering target and an Ar gas (with a gas pressure of 1.3×10 -2 Pa up to 2.7×10-2 Pa) as the sputtering gas with an ion acceleration voltage of 300 V to 1,500 V at a deposition rate of 0.03 to 0.30 nm / s. By stacking Si and Mo layers in 40 to 50 cycles, each cycle comprising the preceding steps, the reflective Mo / Si multilayer stack is deposited.

[0020] With reference to the Fig. 2 and Fig. 3B the process 200 is continued with step 204 in which a cover layer 120 is deposited over the reflective multilayer stack 110 according to some embodiments. Fig. 3B is a sectional view of the structure of Fig. 3A after the deposition of the cover layer 120 over the reflective multilayer stack 110 according to some embodiments.

[0021] With reference to Fig. In step 3B, the top layer 120 is deposited over the top surface of the reflective multilayer stack 110. The top layer 120 helps to protect the reflective multilayer stack 110 from oxidation and chemical etchants to which the reflective multilayer stack 110 may be exposed during subsequent mask manufacturing processes.

[0022] In some embodiments, the cover layer 120 contains a material that resists oxidation and corrosion and has low chemical reactivity with common atmospheric gases, such as oxygen, nitrogen, and water vapor. In some embodiments, the cover layer 120 contains a transition metal, such as ruthenium (Ru), iridium (Ir), rhodium (Rh), platinum (Pt), palladium (Pd), osmium (Os), rhenium (Re), vanadium (V), tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), zirconium (Zr), manganese (Mn), technetium (Tc), or alloys thereof.

[0023] In some embodiments, the top layer 120 is produced using a deposition process such as ion beam deposition (IBD), CVD, PVD, or atomic layer deposition (ALD). In instances where a Ru layer is to be produced as the top layer 120 using IBD, the deposition can be carried out in an Ar atmosphere using a Ru target as the sputtering target.

[0024] With reference to the Fig. 2 and Fig. 3C the process 200 is continued with step 206 in which a buffer layer 130 is deposited over the cover layer 120 according to some embodiments. Fig. 3C is a cross-sectional view of the structure of Fig. 3B after the deposition of the buffer layer 130 over the cover layer 120 according to some embodiments.

[0025] With reference to Fig. In step 3C, the buffer layer 130 is arranged on the top layer 120. The buffer layer 130 has etching properties that differ from those of an absorber layer subsequently deposited on it and thus serves as an etch stop layer to prevent damage to the top layer 120 during the structuring of an absorber layer subsequently deposited on it. Furthermore, the buffer layer 130 can later also serve as a sacrificial layer for focused ion beam repair of defects in the absorber layer. In some embodiments, the buffer layer 130 contains ruthenium boride (RuB), ruthenium silicide (RuSi), chromium oxide (CrO), or chromium nitride (CrN). In some other embodiments, the buffer layer 130 contains a dielectric material, such as silicon oxide or silicon nitride. In some embodiments, the buffer layer 130 is deposited by CVD, PECVD, or PVD.

[0026] With reference to the Fig. 2 and Fig. In 3D, the process 200 is continued with step 208, in which an absorber layer 140 is deposited over the buffer layer 130 according to various embodiments. Fig. 3D is a cross-sectional view of the structure of Fig. 3C after the deposition of the absorber layer 140 over the buffer layer 130 according to some embodiments.

[0027] With reference to Fig. In 3D, the absorber layer 140 is arranged in direct contact with the buffer layer 130. The absorber layer 140 can be used to absorb radiation with the EUV wavelength projected onto the EUV mask 100.

[0028] The absorber layer 140 comprises an absorber material with a high extinction coefficient κ and a low refractive index n at EUV wavelengths. In some embodiments, the absorber layer 140 has an absorber material with a high extinction coefficient and a low refractive index at a wavelength of 13.5 nm. In some embodiments, the extinction coefficient κ of the absorber material of the absorber layer 140 is in the range of approximately 0.01 to 0.08. In some embodiments, the refractive index n of the absorber material of the absorber layer 140 is in the range of 0.87 to 1.

[0029] In some embodiments, the absorber layer 140 contains or is made of a Ta-based alloy comprising Ta and at least one alloying element. In some embodiments, the Ta-based alloy is a Ta-rich alloy with a Ta concentration in the range of more than 50 atomic percent up to 90 atomic percent. In other embodiments, the Ta-based alloy is an alloy rich in alloying elements with an alloying element concentration in the range of more than 50 atomic percent up to 90 atomic percent.

[0030] In some embodiments, the Ta-based alloy contains Ta and at least one transition metal element. Examples of transition metal elements include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), and gold (Au). In some embodiments, the Ta-based alloy contains tantalum chromium (TaCr), tantalum hafnium (TaHf), tantalum iridium (TaIr), tantalum nickel (TaNi), tantalum ruthenium (TaRu), tantalum cobalt (TaCo), tantalum gold (TaAu), tantalum molybdenum (TaMo), tantalum tungsten (TaW), tantalum iron (TaFe), tantalum rhodium (TaRh), tantalum vanadium (TaV), tantalum niobium (TaNb), tantalum palladium (TaPd), tantalum zirconium (TaZr), tantalum titanium (TaTi), or tantalum platinum (TaPt). In some embodiments, the Ta-based alloy contains Ta and an element from Group 14, such as silicon or germanium.For example, in some embodiments the Ta-based alloy is tantalum silicon (TaSi) or tantalum germanium (TaGe).

[0031] In some embodiments, the Ta-based alloy is further doped with one or more interstitial elements, such as boron (B), carbon (C), nitrogen (N), and oxygen (O). The dopants in the form of interstitial elements increase the material density, thereby increasing the strength of the resulting alloy. In some embodiments, the absorber layer 140 comprises Ta, the alloying element, and nitrogen. For example, in some embodiments, the absorber layer 140 contains TaCrN, TaHfN, TaIrN, TaNiN, TaRuN, TaCoN, TaAuN, TaMoN, TaWN, TaFeN, TaRhN, TaVN, TaNbN, TaPdN, TaZrN, TaTiN, TaPtN, or TaSiN. In some embodiments, the absorber layer 140 comprises Ta, the alloying element, nitrogen, and oxygen. For example, in some embodiments, the absorber layer 140 contains TaCrON, TaHfON, TaIrON, TaNiON, TaRuON, TaCoON, TaAuON, TaMoON, TaWON, TaFeON, TaRhON, TaVON, TaNbON, TaPdON, TaZrON, TaTiON, TaPtON or TaSiON.

[0032] In some embodiments, the absorber layer 140 has a single-layer structure. In other embodiments, the absorber layer 140 has a multi-layer structure. In some embodiments, the absorber layer 140 is produced by a deposition process, such as PVD, CVD, ALD, HF magnetron sputtering, DC magnetron sputtering, or IBD. In instances where the absorber layer 140 contains TaCr, the TaCr layer can be produced from a TaCr target with argon (Ar) as the inert sputtering gas. In instances where the absorber layer 140 contains TaCrN, the TaCrN layer can be produced from a TaCr target with nitrogen (N2) as the reactant gas and Ar as the inert sputtering gas. In instances where the absorber layer contains 140 TaCrON, the TaCrON layer can be produced from a TaCrO target with N2 as the reaction gas and Ar as the inert sputtering gas.In some embodiments, the N2 gas concentration can range from 3% to 80% by volume, from 5% to 30% by volume, or from 8% to 15% by volume. The gas pressure can range from 0.5 × 10⁻⁶. -1 Pa up to 10×10 -1 Pa, of 0.5×10 -1 Pa up to 5×1010 -1 Pa or of 0.5×10 -1 Pa up to 3×10 -1 Pa amount.

[0033] The absorber layer 140 is deposited as an amorphous layer. Maintaining an amorphous phase improves the overall roughness of the absorber layer 140. The thickness of the absorber layer 140 is controlled to provide between 95% and 99.5% absorption of EUV light at 13.5 nm. In some embodiments, the absorber layer 140 can have a thickness in the range of approximately 5 nm to approximately 50 nm. If the thickness of the absorber layer 140 is too small, it may not absorb sufficient EUV light to create contrast between the reflecting and non-reflecting areas. Conversely, if the thickness of the absorber layer 140 is too large, the accuracy of any structure fabricated within the absorber layer 140 will tend to be low.

[0034] In embodiments of the present disclosure, the use of Ta-based alloys with a high extinction coefficient κ as the absorber material can reduce the mask 3D effects caused by EUV phase distortion. This can reduce shifts in the best focus and structure positioning errors, while increasing the edge steepness (Normalized Image Log-Slope, NILS).

[0035] With reference to the Fig. 2 and Fig. 3E the process 200 is continued with step 210 in which a resist stack comprising a hard mask layer 160 and a photoresist layer 170 is deposited over the absorber layer 140 according to some embodiments. Fig. 3E is a sectional view of the structure of Fig. 3D after sequential deposition of the hard mask layer 160 and the photoresist layer 170 over the absorber layer 140 according to some embodiments.

[0036] With reference to Fig. In 3E, the hard mask layer 160 is deposited over the absorber layer 140. In some embodiments, the hard mask layer 160 is in direct contact with the absorber layer 140. In some embodiments, the hard mask layer 160 contains a dielectric oxide, such as silicon dioxide, or a dielectric nitride, such as silicon nitride. In some embodiments, the hard mask layer 160 is produced using a deposition process, such as CVD, PECVD, or PVD.

[0037] The photoresist layer 170 is deposited over the hard mask layer 160. The photoresist layer 170 comprises a photosensitive material that can be structured by radiation. In some embodiments, the photoresist layer 170 comprises a positive photoresist material and a negative photoresist material or a hybrid photoresist material. In some embodiments, the photoresist layer 170 is applied to the surface of the hard mask layer 160, for example, by spin coating.

[0038] With reference to the Fig. 2 and Fig. 3F the process 200 is continued with step 212 in which the photoresist layer 170 is lithographically structured to produce a structured photoresist layer 170P according to some embodiments. Fig. 3F is a sectional view of the structure of Fig. 3E after lithographic structuring of the photoresist layer 170 to produce the structured photoresist layer 170P according to some embodiments.

[0039] With reference to Fig. In step 3F, the photoresist layer 170 is structured by first projecting an exposure structure onto the photoresist layer 170. Then, depending on whether a positive or negative resist is used in the photoresist layer 170, the exposed or unexposed parts of the photoresist layer 170 are removed with a resist developer, producing the structured photoresist layer 170P, which has a structure of openings 172 formed within it. The openings 172 expose parts of the hard mask layer 160. The openings 172 are located in the structure area 100A and correspond to locations where the structure of openings 152 in the EUV mask 100 ( Fig. 1) is present.

[0040] Referring to the characters Fig. 2 and Fig. 3G the process 200 is continued with step 214 in which the hard mask layer 160 is etched using the structured photoresist layer 170P as an etching mask to produce a structured hard mask layer 160P according to some embodiments. Fig. 3G is a cross-sectional view of the structure of Fig. 3F after etching the hard mask layer 160 to produce the structured hard mask layer 160P according to some embodiments.

[0041] With reference to Fig. In 3G, portions of the hard mask layer 160 exposed by the openings 172 are etched to form openings 162 extending through the hard mask layer 160. The openings 162 expose portions of the underlying absorber layer 140. In some embodiments, the hard mask layer 160 is etched using anisotropic etching. In some embodiments, the anisotropic etching is a dry etching, such as reactive ion etching (RIE), a wet etching, or a combination thereof. The etching selectively etches the material providing the hard mask layer 160 relative to the material providing the absorber layer 140. The remaining portions of the hard mask layer 160 form the structured hard mask layer 160P.After etching the hard mask layer 160, the structured photoresist layer 170P is removed from the surfaces of the structured hard mask layer 160P, for example by wet peeling or plasma peeling, unless it has been completely consumed during the etching of the hard mask layer 160.

[0042] With reference to the Fig. 2 and Fig. 3H the process 200 is continued with step 216 in which the absorber layer 140 is etched using the structured hard mask layer 160P as an etching mask to produce a structured absorber layer 140P according to some embodiments. Fig. 3H is a sectional view of the structure of Fig. 3G after etching the absorber layer 140 to produce the structured absorber layer 140P according to some embodiments.

[0043] With reference to Fig. In 3H, portions of the absorber layer 140 exposed by the openings 162 are etched to form openings 142 extending through the absorber layer 140. The openings 142 expose portions of the underlying buffer layer 130. In some embodiments, the absorber layer 140 is etched using an anisotropic etching process. In some embodiments, the anisotropic etching is a dry etching, such as RIE, a wet etching, or a combination thereof, selectively removing the material providing the absorber layer 140 from the material providing the underlying buffer layer 130. For example, in some embodiments, the absorber layer 140 is dry-etched with a chlorine-containing gas, such as Cl₂ or BCl₃, or with a fluorine-containing gas, such as NF₃. Ar can be used as a carrier gas.In some embodiments, oxygen (O2) can also be used as the carrier gas. The etch rate and etch selectivity depend on the etchant gas, the etchant flow rate, the power, the pressure, and the substrate temperature. After etching, the remaining portions of the absorber layer 140 form the structured absorber layer 140P.

[0044] With reference to the Fig. 2 and Fig. 3I the process 200 is continued with step 218 in which the buffer layer 130 is etched using the structured hard mask layer 160P as an etching mask to produce a structured buffer layer 130P according to some embodiments. Fig. 3I is a sectional view of the structure of Fig. 3H after etching the buffer layer 130 to produce the structured buffer layer 130P according to some embodiments.

[0045] With reference to Fig. 3I Portions of the buffer layer 130 exposed through openings 162 and 142 are etched to form openings 132 extending through the buffer layer 130. The openings 132 expose portions of the underlying cover layer 120. In some embodiments, the buffer layer 130 is etched using an anisotropic etching process. In some embodiments, the anisotropic etching is a dry etching, such as RIE, a wet etching, or a combination thereof, selectively etching the material providing the buffer layer 130 relative to the material providing the cover layer 120. The remaining portions of the buffer layer 130 form the structured buffer layer 130P. After etching the buffer layer 130, the structured hard mask layer 160P will be removed from the surfaces of the structured absorber layer 140P, for example, using an oxygen plasma or wet etching.

[0046] The openings 142 in the structured absorber layer 140P and the respective openings 132 located below it in the structured buffer layer 130P together define the structure of openings 152 in the EUV mask 100.

[0047] With reference to the Fig. 2 and Fig. In step 3J, the process 200 is continued with step 220 in which a structured photoresist layer 180P comprising a structure of openings 182 is produced over the structured absorber layer 140P and the structured buffer layer 130P according to some embodiments. Fig. 2J is a cross-sectional view of the structure of Fig. 3I after the fabrication of the structured photoresist layer 180P, which has openings 182 above the structured absorber layer 140P and the structured buffer layer 130P according to some embodiments.

[0048] With reference to Fig. 3J exposes the openings 182 parts of the structured absorber layer 140P at the periphery of the structured absorber layer 140P. The openings 182, which correspond to the trenches 154 in the peripheral area 100B of the EUV mask 100, are to be formed. To produce the structured photoresist layer 180P, a photoresist layer (not shown) is applied over the structured buffer layer 130P and the structured absorber layer 140P. The photoresist layer fills the openings 132 and 142 in the structured buffer layer 130P and the structured absorber layer 140P, respectively. In some embodiments, the photoresist layer comprises a positive photoresist material, a negative photoresist material, or a hybrid photoresist material. In some embodiments, the photoresist layer has the same material as the photoresist layer 170 described above in Fig. 7. In some embodiments, the photoresist layer has a different material than the photoresist layer 170. In some embodiments, the photoresist layer is produced, for example, by spin coating. The photoresist layer 170 is subsequently structured by projecting an exposure pattern onto the photoresist layer and removing the exposed or unexposed parts of the photoresist layer using a resist developer, depending on whether a positive or negative resist is used. The remaining parts of the photoresist layer form the structured photoresist layer 170P.

[0049] With reference to the Fig. 2 and Fig. In 3K, the process 200 is continued with step 222 in which the structured absorber layer 140P, the possibly present structured buffer layer 130P, the cover layer 120 and the reflective multilayer stack 110 are etched using the structured photoresist layer 180P as an etching mask to produce trenches 154 in the peripheral area 100B of the substrate 102 according to some embodiments. Fig. 3K is a cross-sectional view of the structure of Fig. 3J after etching the structured absorber layer 140P, the possibly present structured buffer layer 130P, the cover layer 120 and the reflective multilayer stack 110 to produce the trenches 154 in the peripheral area 100B of the substrate 102 according to some embodiments.

[0050] With reference to Fig. The trenches 154 extend through the structured absorber layer 140P, the possibly present structured buffer layer 130P, the cover layer 120, and the reflective multilayer stack 110 to expose the surface of the substrate 102. The trenches 154 enclose the structural area 100A of the EUV mask 100 and separate the structural area 100A from the peripheral area 100B.

[0051] In some embodiments, the structured absorber layer 140P, the structured buffer layer 130P, the top layer 120, and the reflective multilayer stack 110 are etched using a single anisotropic etching process. The anisotropic etching can be a dry etching, such as RIE, a wet etching, or a combination thereof, selectively etching the materials of the respective structured absorber layer 140P, the structured buffer layer 130P, the top layer 120, and the reflective multilayer stack 110 relative to the material provided by the substrate 102. In some embodiments, the structured absorber layer 140P, the structured buffer layer 130P, the top layer 120, and the reflective multilayer stack 110 are etched using several different anisotropic etching processes.Any anisotropic etching can be a dry etching, such as RIE, a wet etching, or a combination of both.

[0052] With reference to the Fig. 2 and Fig. 3L continues the process 200 with step 224, in which the structured photoresist layer 180P is removed according to some embodiments. Fig. 3L is a cross-sectional view of the structure of Fig. 3K after removal of the structured photoresist layer 180P according to some embodiments.

[0053] With reference to Fig. In step 3L, the structured photoresist layer 180P is removed from the structural region 100A and the peripheral region 100B of the substrate 102, for example by wet peeling or plasma peeling. Removing the structured photoresist layer 180P from the openings 142 in the structured absorber layer 140P and the openings 132 in the structured buffer layer 130P exposes the surfaces of the cover layer 120 in the structural region 100A.

[0054] An EUV mask 100 is then fabricated. The EUV mask 100 comprises a substrate 102, a reflective multilayer stack 110 over a front face of the substrate 102, a cover layer 120 over the reflective multilayer stack 110, a structured buffer layer 130P over the cover layer 120, and a structured absorber layer 140P over the structured buffer layer 130P. The EUV mask 100 further comprises a conductive layer 104 over a back face of the substrate 102 opposite the front face. The structured absorber layer 140P features a Ta-based alloy with a high extinction coefficient, allowing for a thinner layer. Consequently, the mask's 3D effects caused by the thicker absorber layer can be reduced, and unnecessary EUV light can be eliminated. This allows a structure located on the EUV mask 100 to be accurately projected onto a silicon wafer.

[0055] After removing the structured photoresist layer 180P, the EUV mask 100 is cleaned to remove contaminants. In some embodiments, the EUV mask 100 is cleaned by immersing it in an ammonium hydroxide (NH4OH) solution. In other embodiments, the EUV mask 100 is cleaned by immersing it in a dilute hydrofluoric acid (HF) solution.

[0056] The EUV mask 100 is subsequently irradiated with, for example, UV light with a wavelength of 193 nm to check for defects in the structured area 100A. Foreign substances can be detected by diffusely reflected light. If defects are found, the EUV mask 100 is further cleaned using a suitable cleaning process.

[0057] Fig. Figure 4 is a sectional view of an EUV mask 400 according to a second embodiment of the present disclosure. With reference to Fig. The EUV mask 400 comprises a substrate 102, a reflective multilayer stack 110 over a front face of the substrate 102, a cover layer 120 over the reflective multilayer stack 110, and a structured absorber layer 140P over the cover layer 120. The EUV mask 400 further features a conductive layer 104 over a back face of the substrate 102 opposite the front face. In comparison with the EUV mask 100 from Fig. 1. The structured buffer layer 130P is omitted in the EUV mask 400. Accordingly, in the EUV mask 400, the structured absorber layer 140P is in direct contact with the cover layer 120.

[0058] Fig. Figure 5 is a flowchart of a process 500 for manufacturing an EUV mask, for example an EUV mask 400, according to some embodiments. Fig. 6A to Fig. Figure 6J shows sectional views of the EUV mask 400 at various stages of the manufacturing process according to some embodiments. The process 500 is discussed in detail below with reference to the EUV mask 400. In some embodiments, additional steps are performed before, during, and / or after the process 500, or some of the described steps are substituted and / or omitted. In some embodiments, some of the structural elements described below are substituted or omitted. Although some embodiments are discussed with steps performed in a specific order, a person skilled in the art should recognize that these steps can also be performed in a different logical sequence.

[0059] With reference to the Fig. 5 and Fig. 6A the method 500 comprises step 502 in which a reflective multilayer stack 110 is produced over a substrate 102 according to some embodiments. Fig. Figure 6A is a sectional view of an initial structure of an EUV mask 400 after fabrication of the reflective multilayer stack 110 over the substrate 102 according to some embodiments. The materials and fabrication processes for the reflective multilayer stack 110 are similar to those described above in Fig. Section 3A has been described and will therefore not be described in detail here.

[0060] With reference to the Fig. 5 and Fig. 6B the process 500 is continued with step 504 in which a cover layer 120 is deposited over the reflective multilayer stack 110 according to some embodiments. Fig. 6B is a sectional view of the structure of Fig. 6A after deposition of the cover layer 120 over the reflective multilayer stack 110 according to some embodiments. The materials and manufacturing processes for the cover layer 120 are similar to those described above in Fig. Section 3B has been described and will therefore not be described in detail here.

[0061] With reference to the Fig. 5 and Fig. In 6C, the process 500 is continued with step 506, in which an absorber layer 140 is deposited over the cover layer 120 according to various embodiments. Fig. 6C is a sectional view of the structure of Fig. 6B after the deposition of the absorber layer 140 over the cover layer 120 according to some embodiments. The materials and manufacturing processes for the absorber layer 140 are similar to those described above in Fig. They have been described in 3D and will therefore not be described in detail here.

[0062] With reference to the Fig. 5 and Fig. In 6D, the process 500 is continued with step 508 in which a resist stack comprising a hard mask layer 160 and a photoresist layer 170 is deposited over the absorber layer 140 according to some embodiments. Fig. 6D is a sectional view of the structure of Fig. 6C after the sequential deposition of the hard mask layer 160 and the photoresist layer 170 over the absorber layer 140 according to some embodiments. Materials and manufacturing processes for the respective hard mask layer 160 and photoresist layer 170 are similar to those described above in Fig. 3E have been described and will therefore not be described in detail here.

[0063] With reference to the Fig. 5 and Fig. In 6E, the process 500 is continued with step 510 in which the photoresist layer 170 is lithographically structured to produce a structured photoresist layer 170P according to some embodiments. Fig. 6E is a sectional view of the structure of Fig. 6D after lithographic structuring of the photoresist layer 170 to produce the structured photoresist layer 170P according to some embodiments. Etching processes for the photoresist layer 170 are similar to those described above in Fig. 3F have been described and will therefore not be described in detail here.

[0064] With reference to the Fig. 5 and Fig. In 6F, the process 500 is continued with step 512 in which the hard mask layer 160 is etched using the structured photoresist layer 170P as an etching mask to produce a structured hard mask layer 160P according to some embodiments. Fig. 6F is a sectional view of the structure of Fig. 6E after etching the hard mask layer 160 to produce the structured hard mask layer 160P according to some embodiments. Etching processes for the hard mask layer 160 are similar to those described above in Fig. 3G has been described and will therefore not be described in detail here.

[0065] With reference to the Fig. 5 and Fig. In 6G, the process 500 is continued with step 514 in which the absorber layer 140 is etched using the structured hard mask layer 160P as an etching mask to produce a structured absorber layer 140P according to some embodiments. Fig. 6G is a cross-sectional view of the structure of Fig. 6F after etching the absorber layer 140 to produce the structured absorber layer 140P according to some embodiments. Etching processes for the absorber layer 140 are similar to those described above in Fig. 3G have been described and are therefore not described in detail here. The structured absorber layer 140P has a plurality of openings 142 that expose the underlying cover layer 120.

[0066] After etching the absorber layer 140, the structured hard mask layer 160P is removed from the surfaces of the structured absorber layer 140P, for example, using oxygen plasma or wet etching.

[0067] With reference to the Fig. 5 and Fig. In step 6H, the process 500 is continued with step 516 in which a structured photoresist layer 180P having a structure of openings 182 is produced over the structured absorber layer 140P according to some embodiments. Fig. 6H is a sectional view of the structure of Fig. 6G after fabricating the structured photoresist layer 180P, which has openings 182, over the structured absorber layer 140P according to some embodiments. Materials and fabrication processes for the structured photoresist layer 180P are similar to those described above in Fig. They have been described in detail in 3J and will therefore not be described in detail here.

[0068] With reference to the Fig. 5 and Fig. 6I the process 500 is continued with step 518 in which the structured absorber layer 140P, the cover layer 120 and the reflective multilayer stack 110 are etched using the structured photoresist layer 180P as an etching mask to produce trenches 154 in the peripheral area 100B of the substrate 102 according to some embodiments. Fig. 6I is a sectional view of the structure of Fig. 6H after etching the structured absorber layer 140P, the cover layer 120 and the reflective multilayer stack 110 to produce the trenches 154 in the peripheral area 100B of the substrate 102 according to some embodiments.

[0069] With reference to Fig. The trenches 154 extend through the structured absorber layer 140P, the cover layer 120, and the reflective multilayer stack 110 to expose the surface of the substrate 102. The trenches 154 enclose the structural area 100A of the EUV mask 100 and separate the structural area 100A from the peripheral area 100B.

[0070] In some embodiments, the structured absorber layer 140P, the cover layer 120, and the reflective multilayer stack 110 are etched using a single anisotropic etching process. The anisotropic etching can be a dry etching, such as RIE, a wet etching, or a combination thereof, selectively removing materials from the respective structured absorber layer 140P, the cover layer 120, and the reflective multilayer stack 110 relative to the material provided by the substrate 102. In other embodiments, the structured absorber layer 140P, the cover layer 120, and the reflective multilayer stack 110 are etched using several different anisotropic etching processes. Each anisotropic etching can be a dry etching, such as RIE, a wet etching, or a combination thereof.

[0071] With reference to the Fig. 5 and Fig. 6J the process 500 is continued with step 520 in which the structured photoresist layer 180P is removed according to some embodiments. Fig. 6J is a cross-sectional view of the structure of Fig. 6I after removal of the structured photoresist layer 180P according to some embodiments.

[0072] With reference to Fig. At 6J, the structured photoresist layer 180P is removed from the structural region 100A and the peripheral region 100B of the substrate 102, for example, by wet peeling or plasma peeling. Removing the structured photoresist layer 180P from the openings 142 in the structured absorber layer 140P exposes the surfaces of the cover layer 120 in the structural region 100A. The openings 142 in the structured absorber layer 140P define the structure of openings 152 in the EUV mask 400.

[0073] An EUV mask 400 is then fabricated. The EUV mask 400 comprises a substrate 102, a reflective multilayer stack 110 over a front face of the substrate 102, a cover layer 120 over the reflective multilayer stack 110, and a structured absorber layer 140P over the cover layer 120. The EUV mask 400 further comprises a conductive layer 104 over a back face of the substrate 102 opposite the front face. The structured absorber layer 140P is a Ta-based alloy with a high extinction coefficient, allowing for a thinner layer. Consequently, the mask 3D effects caused by the thicker absorber layer can be reduced, and unnecessary EUV light can be eliminated. This allows a structure located on the EUV mask 400 to be accurately projected onto a silicon wafer.

[0074] After removing the structured photoresist layer 180P, the EUV mask 400 is cleaned to remove contaminants. In some embodiments, the EUV mask 400 is cleaned by immersing it in an ammonium hydroxide (NH4OH) solution. In other embodiments, the EUV mask 400 is cleaned by immersing it in a dilute hydrofluoric acid (HF) solution.

[0075] The EUV mask 400 is subsequently irradiated with, for example, UV light with a wavelength of 193 nm to check for defects in the structured area 100A. Foreign substances can be detected by diffusely reflected light. If defects are found, the EUV mask 400 is further cleaned using a suitable cleaning process.

[0076] One aspect of this description concerns an EUV mask. The EUV mask comprises a substrate, a reflective multilayer stack on the substrate, and a structured absorber layer on the reflective multilayer stack. The structured absorber layer is an alloy containing tantalum (Ta) and at least one alloying element. This at least one alloying element is either a transition metal or a group 14 element.

[0077] Another aspect of this description concerns a method for fabricating an EUV mask. The method comprises fabricating a reflective multilayer stack on a substrate, depositing a cover layer on the reflective multilayer stack, depositing an absorber layer on the cover layer, fabricating a structured hard mask layer on the absorber layer, and etching the absorber layer to create a plurality of openings, using the structured hard mask as the etching mask, which expose a surface of the cover layer. The absorber layer is an alloy containing tantalum (Ta) and at least one alloying element. The at least one alloying element is at least a transition metal element or at least one element of Group 14.

[0078] Another aspect of this description concerns a process for fabricating an EUV mask. The process involves fabricating a reflective multilayer stack on a substrate. A cover layer is then deposited onto the reflective multilayer stack. A buffer layer is then fabricated on the cover layer. An absorber layer is deposited on the buffer layer. The absorber layer comprises an alloy of tantalum (Ta) and at least one transition metal element selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), and gold (Au). A hard mask layer is then fabricated on the absorber layer. The hard mask layer is then etched to create a textured hard mask layer.Using the structured hard mask layer as an etching mask, the absorber layer is then etched to form a plurality of openings in it, with the plurality of openings exposing a surface of the cover layer.

[0079] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure.

Claims

[1] Showing ELTV mask: a substrate; a reflective multilayer stack on the substrate; and a structured absorber layer on the reflective multilayer stack, wherein the structured absorber layer contains an alloy with tantalum (Ta) and at least one alloying element, wherein the at least one alloying element contains at least one transition metal element or at least one element from Group 14. [2] EUV mask according to claim 1, wherein the alloy is a Ta-rich alloy with a Ta concentration of up to 90 atomic%. [3] ELTV mask according to claim 1 or 2, wherein the at least one transition metal element is selected from: titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), gold (Au) and alloys thereof. [4] EUV mask according to any of the preceding claims, wherein the structured absorber layer contains TaCr, TaHf, TaIr, TaNi, TaRu, TaCo, TaAu, TaMo, TaW, TaFe, TaRh, TaV, TaNb, TaPd, TaZr, TaTi or TaPt. [5] EUV mask according to any of the preceding claims, wherein the at least one element is silicon or germanium from Group 14. [6] ELTV mask according to one of the preceding claims, wherein the structured absorber layer contains TaSi or TaGe. [7] EUV mask according to one of the preceding claims, wherein the alloy further contains at least one interstitial element. [8] EUV mask according to claim 7, wherein the at least one interstitial element contains nitrogen (N), oxygen (O), boron (B), carbon (C) or combinations thereof. [9] ELTV mask according to any of the preceding claims, wherein the structured absorber layer contains TaCrN, TaHfN, TaIrN, TaNiN, TaRuN, TaCoN, TaAuN, TaMoN, TaWN, TaFeN, TaRhN, TaSiN, TaVN, TaNbN, TaPdN, TaZrN, TaTiN or TaPtN. [10] ELTV mask according to any one of claims 1 to 8, wherein the structured absorber layer comprises TaCrON, TaHfON, TaIrON, TaNiON, TaNi2ON, TaRuON, TaCoON, TaAuON, TaMoON, TaWON, TaFeON, TaRhON, TaSiON, TaVON, TaNbON, TaPdON, TaZrON, TaTiON or TaPtON. [11] ELTV mask according to one of the preceding claims, further comprising: a cover layer on the reflective multilayer stack, wherein the structured absorber layer is in contact with the cover layer. [12] EUV mask according to any one of claims 1 to 10, further comprising: a top layer on the reflective multilayer stack; and a structured buffer layer on the top layer, wherein the structured absorber layer is in contact with the structured buffer layer. [13] Method for manufacturing an EUV mask, comprising: Forming a reflective multilayer stack on a substrate; Deposition of a top layer on the reflective multilayer stack; Deposition of an absorber layer on the top layer, wherein the absorber layer comprises an alloy with tantalum (Ta) and at least one alloying element, wherein the at least one alloying element contains at least one transition metal element or at least one element from group 14; Forming a structured hard mask layer on the absorber layer; and Etching the absorber layer to create multiple openings in it using the structured hard mask layer as an etching mask, the multiple openings exposing a surface of the cover layer. [14] The method of claim 13, further comprising: Etching of the absorber layer, the cover layer and the reflective multilayer stack to form multiple trenches in a peripheral area of ​​the substrate surrounding the multiple openings. [15] Method according to claim 13 or 14, wherein the deposition of the absorber layer comprises: Sputtering a target containing the alloy in an argon atmosphere. [16] Method according to any one of claims 13 to 15, wherein the absorber layer contains TaCr, TaHf, TaIr, TaNi, TaRu, TaCo, TaAu, TaMo, TaW, TaFe, TaRh, TaV, TaNb, TaPd, TaZr, TaTi, TaPt, a nitride thereof or an oxide nitride thereof. [17] Method for manufacturing an EUV mask, comprising: Forming a reflective multilayer stack on a substrate; Deposition of a top layer on the reflective multilayer stack; Creating a buffer layer on the top layer; Deposition of an absorber layer on the buffer layer, wherein the absorber layer contains an alloy with tantalum (Ta) and at least one transition metal element selected from: titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt) and gold (Au); Forming a hard mask layer on the absorber layer; Etching the hard mask layer to form a structured hard mask layer; and Etching the absorber layer to create multiple openings in it using the structured hard mask layer as an etching mask, the multiple openings exposing a surface of the cover layer. [18] Method according to claim 17, wherein the buffer layer contains ruthenium boride, ruthenium silicide, chromium oxide, chromium nitride, silicon oxide or silicon oxide nitride. [19] Method according to claim 17 or 18, wherein the cover layer contains ruthenium (Ru), iridium (Ir), rhodium (Rh), platinum (Pt), palladium (Pd), osmium (Os), rhenium (Re), vanadium (V), tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), zirconium (Zr), manganese (Mn), technetium (Tc) or alloys thereof. [20] Method according to claim 17, 18 or 19 wherein the deposition of the buffer layer forms an amorphous layer.