WIRELESS TRANSMISSION ERROR RATE PREDICTION

Abstract

Devices, systems, and techniques for predicting wireless transmission error rates. In at least one embodiment, a processor includes one or more circuits for predicting one or more wireless transmission error rates, based at least partially on one or more signal-to-noise ratio (SNR) measurements.

Description

FIELD OF THE INVENTION

[0001] At least one embodiment relates to processing resources used to perform wireless packet transmission scheduling. For example, at least one embodiment relates to processors and / or computing systems used to predict a block error rate (BLER) and generate a packet transmission order metric of ultra-reliable, low-latency communication packets (URLLC packets) based at least in part on predicted BLER according to various novel techniques described herein. BACKGROUND

[0002] Wireless packet scheduling and transmission can consume significant computational resources and time. Approaches for wireless packet scheduling and transmission can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a system according to at least one embodiment; Fig. 2 illustrates a flowchart of a technique for selecting a modulation and coding scheme and a number of resource blocks to be used, according to at least one embodiment; Fig. 3 illustrates a flowchart of a technique for scheduling and transmitting packets according to at least one embodiment; Fig. 4 is a block diagram illustrating an example of a processor according to at least one embodiment; Fig. 5 is a block diagram illustrating a driver and / or runtime environment according to at least one embodiment; Fig. 6 illustrates an exemplary data center system according to at least one embodiment; Fig. 7A illustrates an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 7B illustrates an example of camera positions and fields of view for the autonomous vehicle from Fig. 7A according to at least one embodiment; Fig. Figure 7C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 7A according to at least one embodiment; Fig. Figure 7D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle. Fig. 7A according to at least one embodiment; Fig. 8 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 9 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 10 illustrates a computer system according to at least one embodiment; Fig. 11 illustrates a computer system according to at least one embodiment; Fig. 12A illustrates a computer system according to at least one embodiment; Fig. 12B illustrates a computer system according to at least one embodiment; Fig. 12C illustrates a computer system according to at least one embodiment; Fig. 12D illustrates a computer system according to at least one embodiment; Fig. 12E and Fig. 12F illustrate a shared programming model according to at least one embodiment; Fig. 13 illustrates example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 14A and Fig. 14B illustrate example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 15A and Fig. 15B illustrate additional example graphics processor logic according to at least one embodiment; Fig. 16 illustrates a computer system according to at least one embodiment; Fig. 17A illustrates a parallel processor according to at least one embodiment; Fig. 17B illustrates a partition unit according to at least one embodiment; Fig. 17C illustrates a processing cluster according to at least one embodiment; Fig. 17D illustrates a graphics multiprocessor according to at least one embodiment; Fig. 18 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment; Fig. 19 illustrates a graphics processor according to at least one embodiment; Fig. 20 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 21 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 22 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 23 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 24 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 25 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 26A and Fig. 26B illustrate thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment; Fig. 27 illustrates a parallel processing unit ("PPU") according to at least one embodiment; Fig. 28 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. 29 illustrates a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment; Fig. 30 illustrates a streaming multiprocessor according to at least one embodiment; Fig. 31 illustrates a network for communicating data within a 5G wireless communication network according to at least one embodiment; Fig. 32 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment; Fig. 33 is a diagram illustrating basic functionality of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment; Fig. 34 illustrates a radio access network that may be part of a 5G network architecture, according to at least one embodiment; Fig. 35 provides an example illustration of a 5G mobile communication system in which a plurality of different types of devices are used, according to at least one embodiment; Fig. 36 illustrates an exemplary high-level system according to at least one embodiment; Fig. 37 illustrates an architecture of a system of a network according to at least one embodiment; Fig. 38 illustrates exemplary components of a device according to at least one embodiment; Fig. 39 illustrates exemplary interfaces of a baseband circuit according to at least one embodiment; Fig. 40 illustrates an example of an uplink channel according to at least one embodiment; Fig. 41 illustrates an architecture of a system of a network according to at least one embodiment; Fig. 42 illustrates a control plane protocol stack according to at least one embodiment; Fig. 43 illustrates a user-plane protocol stack according to at least one embodiment; Fig. 44 illustrates components of a core network according to at least one embodiment; and Fig. 45 illustrates components of a system for supporting network function virtualization (NFV) according to at least one embodiment. DETAILED DESCRIPTION

[0003] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details.

[0004] Fig. 1 is a block diagram illustrating a system 100 according to at least one embodiment. In at least one embodiment, the system 100 includes a base station 102 in wireless radio signal communication with a set of user equipment (UE) devices 104. In at least one embodiment, the UEs are mobile communication devices (e.g., smartphones, cellular phones, cellular-enabled tablet devices, and / or any other suitable wireless mobile communication devices). In at least one embodiment, the base station 102 is a gNodeB (gNB). In at least one embodiment, the base station 102 and the UEs in the set of UEs 104 communicate according to one or more Third Generation Partnership Project (3GPP) protocols (e.g., Fifth Generation (5G) New Radio (NR), 6G, and / or another suitable protocol and / or standard).In at least one embodiment, base station 102 predicts a block error rate (BLER) of packets to be transmitted to UEs in the set of UEs 104 using one or more signal-to-noise (SNR) measurements and selects a modulation and coding scheme (MCS) and a number of resource blocks (RBs) to be used to transmit those packets based on the predicted BLER. In at least one embodiment, base station 102 generates one or more transmission priority metrics based at least in part on the selected number of resource blocks and schedules packets to be transmitted based at least in part on the generated transmission priority metrics.

[0005] In at least one embodiment, the UE 104 includes a first UE 106 and a second UE 108. In at least one embodiment, the base station 102 includes an antenna 110 for receiving signals from UEs in the set of UEs 104. In at least one embodiment, the antenna 110 is also used to transmit signals to UEs in the set of UEs 104. In at least one embodiment, the antenna 110 is a multi-element antenna. In at least one embodiment, the antenna 110 includes a set of antenna elements 112. In at least one embodiment, antenna elements in the set of antenna elements 112 are referred to as antennas. In at least one embodiment, the set of antenna elements 112 includes a first antenna 114 and a second antenna 116. In at least one embodiment, the set of antenna elements 112 includes a number of antennas that is a power of two (e.g.,two, four, eight, or sixteen antennas) or another suitable number of antennas. In at least one embodiment, signals transmitted from UEs in the set of UEs 104 are to be received using multiple antennas in the set of antenna elements 112. In at least one embodiment, signals transmitted to UEs in the set of UEs 104 are transmitted using multiple antennas in the set of antenna elements 112. In at least one embodiment, the base station 102 includes a beamformer 152. In at least one embodiment, the base station 102 is to use beamforming (e.g., using the beamformer 152) to transmit and / or receive signals using antennas in the set of antenna elements 112.

[0006] In at least one embodiment, base station 102 includes a processor 118. In at least one embodiment, base station 102 includes memory 120. In at least one embodiment, base station 102 includes an accelerator 122. In at least one embodiment, accelerator 122 includes one or more graphics processing units (GPUs). In at least one embodiment, accelerator 122 includes one or more parallel processing devices (PPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or another suitable accelerator. In at least one embodiment, base station 102 includes a different number of processors (e.g., more than one processor 118), a different number of memories (e.g., more than one memory 120), and / or a different number of accelerators (e.g., more than one accelerator 122).In at least one embodiment, processor 118 is a central processing unit (CPU). In at least one embodiment, at least one component of base station 102 is included in a virtual radio access network (vRAN). In at least one embodiment, base station 102 uses multiple input multiple output (MIMO) (e.g., digital massive MIMO) to form beams and transmit data to multiple UEs using a same set of time and frequency resources.

[0007] In at least one embodiment, the UE 106 includes a processor 124. In at least one embodiment, the UE 106 includes a memory 126. In at least one embodiment, the UE 106 includes a different number of processors (e.g., more than one processor 124), a different number of memories (e.g., more than one memory 126), one or more accelerators, and / or one or more other suitable components (e.g., one or more user interface components, one or more antennas, and / or one or more other components) that are not shown for clarity. In at least one embodiment, other UEs in the set of UEs 104 (e.g., UE 108) include components that are not shown for clarity, such as shown and / or described with respect to the UE 106.

[0008] In at least one embodiment, terms such as "module" and nominalized verbs (e.g., channel quality information generator, error rate predictor, MCS selector, channel estimator, beamformer, resource block identifier, packet transmission scheduler, BLER estimation module, MCS identification module, RB identification module, sequence metric generation module, packet transmission scheduling module, controller, and / or other terms), unless otherwise clear from the context or expressly indicated to the contrary, refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein, unless otherwise clear or expressly indicated to the contrary from the context.In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry. In at least one embodiment, modules may be embodied collectively or individually as circuitry that forms part of a larger system, for example, an integrated circuit (IC), a system on a chip (SoC), and so on.

[0009] In at least one embodiment, the UE 106 includes a channel quality information (CQI) generator 128. In at least one embodiment, the CQI generator 128 generates the CQI 130. In at least one embodiment, the CQI 130 includes information that can be used to generate an SNR. In at least one embodiment, the CQI 130 includes information indicative of the SNR. In at least one embodiment, the UE 106 transmits the CQI 130 to the base station 102. In at least one embodiment, the base station 102 generates one or more indications of the SNR 132 based at least in part on the CQI 130. In at least one embodiment where the CQI 130 includes information indicative of the SNR, the base station 102 stores one or more aspects of the CQI 130 as one or more indications of the SNR 132.

[0010] In at least one embodiment, the base station 102 includes an error rate predictor 134 to predict one or more BLERs based at least in part on one or more indications of the SNR 132. In at least one embodiment, the prediction by the error rate predictor 134 is referred to as an estimate. In at least one embodiment, the prediction by the error rate predictor 134 is referred to as generating a predicted BLER and / or generating an estimated BLER. In at least one embodiment, the error rate predictor 134 generates one or more indications of the SNR 132 based at least in part on the CQI 130 received from one or more UEs. In at least one embodiment, one or more other components of the base station 102 generate one or more indications of the SNR 132.In at least one embodiment, the error rate predictor 134 predicts the BLER of certain packets to be transmitted using the packet information 136 and one or more indications of the SNR 132. In at least one embodiment, the packet information 136 includes, for each URLLC packet to be transmitted, a BLER target (e.g., 0.001% or less, or another suitable value), a latency requirement (e.g., 1 millisecond (ms), 0.5 ms, or another suitable value), a weight, and a packet size. In at least one embodiment, the packet information 136 includes one or more other types of information instead of and / or in addition to this information. In at least one embodiment, the packet information 136 includes fewer types of information and / or information for other types of packets to be transmitted.

[0011] In at least one embodiment, base station 102 includes an MCS selector 138. In at least one embodiment, MCS selector 138 selects a modulation and coding scheme (e.g., identified using an MCS index) to be used to transmit each URLLC packet based at least in part on the BLER predicted by error rate predictor 134 to occur using that MCS. In at least one embodiment, MCS selector 138 stores the selected MCS of each packet to be transmitted as packet MCS information 140. In at least one embodiment, the MCS level determines relative portions of wireless transmission resources used to transmit bits and error correction information. In at least one embodiment, higher MCS levels have higher code rates than lower MCS levels. In at least one embodiment, a modulation order (e.g.,2, 4, 6, 8, or another suitable value) associated with each MCS level, with some MCS levels having the same modulation order. In at least one embodiment, a particular MCS level defines a number of useful bits (e.g., not used as error correction information) to be transmitted per symbol. In at least one embodiment, base station 102 includes a resource block (RB) identifier 142. In at least one embodiment, RB identifier 142 identifies a number of RBs to be used to transmit each URLLC based at least in part on the BLER predicted by error rate predictor 134 to occur using that number of RBs. In at least one embodiment, RB identifier 142 stores the identified number of RBs to be used to transmit each URLLC packet as RB information 144.In at least one embodiment, an RB includes 12 consecutive subcarriers in the frequency domain. In at least one embodiment, the error rate predictor 134 includes the MCS selector 138 and / or the RB identifier 142. In at least one embodiment, selecting the MCS is referred to as identifying the MCS and / or generating an indication of the MCS to be used. In at least one embodiment, identifying the number of RBs to be used is referred to as selecting the number of RBs to be used and / or generating an indication of the number of RBs to be used.

[0012] In at least one embodiment, base station 102 includes a packet transmission scheduler 146. In at least one embodiment, packet transmission scheduler 146 generates one or more transmission priority metrics 148. In at least one embodiment, transmission priority metrics 148 are referred to as scheduling metrics or another suitable term. In at least one embodiment, packet transmission scheduler 146 generates a transmission priority metric for each URLLC packet to be transmitted. In at least one embodiment, packet transmission scheduler 146 generates transmission priority metrics for one or more other types of packets to be transmitted. In at least one embodiment, packet transmission scheduler 146 generates transmission priority metrics 148 based at least in part on RB information 144. In at least one embodiment, packet transmission scheduler 146 is an order-based scheduler.

[0013] In at least one embodiment, one or more base stations (e.g., gNodeBs such as base station 102) in a 5G NR network use multiple antenna elements (e.g., elements of antenna 110). In at least one embodiment, one or more base stations operate at least partially in lower frequency bands (e.g., sub-6 GHz regime and / or millimeter wave (mmWave) frequency bands). In at least one embodiment, one or more base stations (e.g., base station 102) and UEs (e.g., UEs in the set of UEs 104) operate using one or more of Enhanced Mobile Broadband (eMBB), Ultra-Reliable Low Latency Communications (URLLC), and / or Massive Machine Type Communications (mMTC). In at least one embodiment, the base station (BS) performs beamforming based on channel estimation to achieve high downlink user throughput.In at least one embodiment, when downlink-uplink channel reciprocity is available, the BS obtains channel state information (CSI) by channel measurement and / or performing channel estimation using uplink signals such as probing reference signals.

[0014] In at least one embodiment, base station 102 includes a channel estimator 150 that performs channel estimation and equalization of wireless signals received at base station 102. In at least one embodiment, channel estimator 150 performs channel estimation based at least in part on reference signals (e.g., probing reference signals (SRS)) received from UEs. In at least one embodiment, beamformer 152 is to calculate and / or identify one or more beam directions to transmit one or more downlink signals based at least in part on channel estimation (e.g., performed by channel estimator 150).

[0015] In at least one embodiment, predicting BLER based at least in part on SNR, selecting MCS using predicted BLER, identifying RBs using predicted BLER, and / or scheduling packet transmission based at least in part on predicted BLER provides advantages over legacy techniques that do not select MCS, identify RBs, and / or schedule packet transmission by predicting BLER using SNR, at least because predicting and / or estimating BLER based at least in part on SNR is faster than legacy techniques for calculating BLER and allows a larger number of packets to be transmitted in a manner that meets the requirements of URLLC communication, better utilizing computation and transmission resources.

[0016] In at least one embodiment, one or more techniques use a mini-slot as a scheduling unit. In at least one embodiment, the packet transmission scheduler 146 uses mini-slots as scheduling units. In at least one embodiment, each packet (e.g., URLLC packet) has a BLER target, a latency requirement, a weight, and a packet size (e.g., stored as packet information 136). In at least one embodiment, the BLER target of a packet i is stored as BLERitar In at least one embodiment, the latency requirement of a packet i is denoted as d i In at least one embodiment, the latency requirement is referred to as a deadline. In at least one embodiment, packets that exceed the deadline are discarded. In at least one embodiment, the weight of a packet i is referred to as w iIn at least one embodiment, the weight is referred to as a priority. In at least one embodiment, the packet size of a packet i is referred to as L i In at least one embodiment, the packet size is referred to as length. In at least one embodiment, the packet is referred to as a user and / or the packets are referred to as users.

[0017] In at least one embodiment, a number of resource blocks (RBs) allocated to a packet i at mini-slot t is defined as n i (t). In at least one embodiment, a modulation and coding scheme (MCS) of packet i at mini-slot t is denoted as m i(t). In at least one embodiment, the base station 102 identifies the number of RBs assigned to the packet and / or the packet's MCS. In at least one embodiment, the packet transmission scheduler 146 maximizes a sum of weights of served packets while meeting the BLER and latency requirements of packets. In at least one embodiment, the packet transmission scheduler 146 includes one or more of the error rate predictor 134, the MCS selector 138, and / or the RB identifier 142. In at least one embodiment, the transmission scheduler 146 schedules packets at each mini-slot based on BLERitar, d i , w i and L i , which guarantees the BLER and deadline requirements.

[0018] In at least one embodiment, the base station 102 schedules packets based at least in part on performing a first stage (e.g., using the error rate predictor 134, the MCS selector 138, and the RB identifiers 142) that determines a minimum number of RBs no* and MCS mi* (e.g. optimal MCS) are identified so that ni*⋅Nsym∗Nsub∗R(mi*)≥Li and the BLER target is met, where N sym is a number of orthogonal frequency division multiplexing (OFDM) symbols per mini-slot (e.g. 2, 3, 5 or 7 depending on the system configuration), N sub is a number of sub-carriers for RB (e.g. 12 sub-carriers), R(mi*) a data rate for the MCS level mi* is and L iis the packet size. In at least one embodiment, the base station 102 schedules packets based at least in part on performing a second stage (e.g., using the packet transmission scheduler 146) that schedules packets such that a sum of weights of served packets using (ni*,wi,di) of each packet is maximized. In at least one embodiment, no*, identified in Stage 1 is used in Stage 2.

[0019] In at least one embodiment, the error rate predictor 134 performs a prediction of the BLER. In at least one embodiment, the error rate predictor 134 performs a BLER estimation for packets (e.g., URLLC packets). In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on an indication of the SNR. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on an indication of the SNR and a number of RBs per packet. In at least one embodiment, the error rate predictor 134 predicts the BLER using an assumption of an additive white Gaussian noise (AWGN) channel without frequency-selective fading (e.g., all RBs have the same SNR).

[0020] In at least one embodiment, the error rate predictor 134 predicts the BLER as follows: BLER=Q(nV(C−R−c)), where C is the channel capacity, n is the block length, V is the channel dispersion, R is the coding rate, c is a calibration term and Q(x)=12π∫x∞exp(−u22). In at least one embodiment, this is referred to as predicting the BLER using a calibrated boundary (e.g., a calibrated Polyanskiy boundary). In at least one embodiment, the error rate predictor 134 uses an assumption of the AWGN such that the channel capacity C = log2(1 + γ) and the channel dispersion V=1ln22⋅(1−1(γ+1)2), where γ is the SNR. In at least one embodiment, the calibration term c is a constant value (e.g., 0.1 or another suitable value). In at least one embodiment, the calibration term c to be used is a predetermined value (e.g., identified using the simulated decoder performance).

[0021] In at least one embodiment, the calibration term c varies with different MCS and / or the number of RBs used. In at least one embodiment, the error rate predictor 134 predicts the BLER as follows: BLER=Q(nV(C−R−cm,Nb)), Q(nv(C−R−cm,Nb)), where c m,Nb the calibration under MCS m and N b RBs is.

[0022] In at least one embodiment, the calibration terms c m,Nb predetermined values ​​(e.g. using the simulated performance with different combinations of MCS m and N b RBs identified). In at least one embodiment, the set of calibration terms c m,Nb a calibration term to be used with each combination of MCS (e.g., each MCS level) and the number of RBs that can be used. In at least one embodiment, the set of calibration terms includes c m,Nbone or more default calibration terms to be used if the set of calibration terms does not include one or more previously determined calibration terms for one or more combinations of MCS and the number of RBs. In at least one embodiment, a set of calibration terms c m,Nb stored (e.g., in memory 120) to be used by the error rate predictor 134 in predicting the BLER. In at least one embodiment, terms in the set of calibration terms c m,Nb by MCS m and N b RBs used to select a particular calibration term are indexed or otherwise associated with it. In at least one embodiment, c m,Nbfor example, 0.147 when 6 RBs are used at MCS = 0, 0.138 when 12 RBs are used at MCS = 0, and 0.139 when 24 RBs are used at MCS = 0. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on the SNR using another suitable technique and / or at least in part based on the use of another suitable formula, calibration, and / or boundary. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on the SNR using one or more neural networks (NNs). In at least one embodiment, NNs used by the error rate predictor 134 are trained NNs (e.g., trained using a supervised learning technique to generate the predicted BLER based at least in part on the SNR).In at least one embodiment, one or more of the MCS selector 138 and / or the RB identifier 142 are to select MCS and / or identify a number of RBs to be used based at least in part on another suitable technique. In at least one embodiment, one or more of the MCS selector 138 and / or the RB identifier 142 are to select MCS and / or identify a number of RBs using one or more NNs (e.g., trained using a supervised learning technique to generate an indication of the MCS and / or the number of RBs to be used based at least in part on the SNR, BLER requirement, packet size, and latency requirements as input).

[0023] In at least one embodiment, the base station 102 identifies a minimum number of RBs ni∗ and MCS mi∗ (e.g. optimal MCS) to be used to transmit each packet so that ni∗⋅Nsym∗Nsub∗R(mi∗)≥Li and BLERi=Q(nV(C−R(mi∗)−cmi∗ni∗))≤BLERitar, where BLERitar is the BLER target (e.g., the BLER assigned to the URLLC packet, such as 0.001% or less) of packet i, and other parameters are as described above. In at least one embodiment, one or more of the error rate predictor 134, the MCS selector 138, and the RB identifier 142 identify the minimum number of RBs no* and MCS mi∗ In at least one embodiment, the base station 102 identifies the minimum number of RBs ni∗ and MCS mi∗ within a certain period of time (e.g., within a mini-slot as short as 2 symbols, where, under numerology 1, 2 symbols correspond to 71 microseconds). In at least one embodiment, base station 102 identifies the minimum number of RBs ni∗ and MCS mi∗ in real time, where real time refers to within a predetermined period of time (e.g., expressed in mini-slots, symbols, or microseconds). In at least one embodiment, one or more processors (e.g., one or more GPUs and / or other suitable accelerators, such as accelerator 122) identify in parallel ni∗ and mi∗. In at least one embodiment, base station 102 identifies a number of RBs (e.g., using RB identifiers 142) to be used (e.g., a minimum number of RBs that satisfies the BLER and allows the packet size to be transmitted) based at least in part on predicting the BLER (e.g., using error rate predictor 134) at each MCS level (e.g., each MCS level that can be used to transmit packets from base stations to UEs in 5G NR) for each packet, and selects a highest MCS level (e.g., using MCS selector 138) that can be used while still satisfying the packet's BLER requirement. In at least one embodiment, the base station 102 predicts the possible BLER for each MCS level (e.g., 29 possible MCS levels (MCS 0-28) or another suitable number of MCS levels).

[0024] In at least one embodiment, base station 102 and / or another suitable mobile wireless network component uses an accelerator (e.g., a GPU) to predict the BLER of packets to be transmitted to UEs in one or more cells. In at least one embodiment, using the GPU to predict the BLER of packets in parallel to identify MCS and the number of RBs to be used for each packet can be performed to meet the URLLC BLER and latency requirements for transmitting multiple packets (e.g., the average propagation time of a single GPU is less than 40 microseconds when the number of packets is less than 4000).In at least one embodiment, the base station uses additional GPUs and / or other accelerators to scale to additional numbers of packets while still meeting the URLLC BLER and packet latency requirements.

[0025] In at least one embodiment, the packet transmission scheduler 146 generates a metric vi=f(ni*,wi,di) for each packet i. In at least one embodiment, the packet transmission scheduler 146 stores these metrics as transmission priority metrics 148. In at least one embodiment, those packets with greater v i higher priority. In at least one embodiment, the packet transmission scheduler 146 breaks connections randomly (e.g., by randomly or pseudorandomly selecting one of the packets with the same metric value). In at least one embodiment, f with w i and takes with no* and d iIn at least one embodiment, the packet transmission scheduler 146 uses order-based scheduling that assigns an order for all packets in each mini-slot. In at least one embodiment, the packet transmission scheduler 146 uses a scheduling policy that no* assigns RBs to the packet with the highest order (e.g., to transmit the packet completely), then nj* Assigns RBs to the packet with the second highest order, and so on. In at least one embodiment, if there are not enough RBs in the mini-slot to completely transmit the packet, the packet transmission scheduler 146 assigns all remaining RBs in that mini-slot to that packet. In at least one embodiment, the packet transmission scheduler 146 schedules at most one packet to be partially transmitted in each mini-slot. In at least one embodiment, partially transmitted refers to a packet that has not completed transmission in a particular mini-slot, with some bits remaining to be transmitted in a subsequent mini-slot.

[0026] In at least one embodiment, the packet transmission scheduler 146 schedules packets to be transmitted using an assumption that packets arrive in a queue to be transmitted under a Poisson-type arrival distribution at rate λ. In at least one embodiment, the packet transmission scheduler 146 schedules packets based at least in part on a technique that provides good performance (e.g., above a predetermined metric) for varying λ. In at least one embodiment, the packet transmission scheduler generates a transmission priority metric v i for each package, so that vi=wini*×(1dl)β. In at least one embodiment, w i a weight value assigned to the package, no* is the number of RBs to be used to transmit the packet, d iis an indication of the latency requirement of the packet and β is a parameter that indicates the relative contribution of the 1di−Terms compared to the wini*−Term affected when the packet transmission scheduler 146 sets the transmission priority metric v i generated. In at least one embodiment, β is greater than zero. In at least one embodiment, β is a predetermined value (e.g., identified by simulation). In at least one embodiment, the packet transmission scheduler uses a constant value of β for different packet arrival rates λ. In at least one embodiment, the packet transmission scheduler 146 uses a β value of 1. In at least one embodiment, the packet transmission scheduler 146 uses more than one β value (e.g., a higher β value when λ is small). In at least one embodiment, the packet transmission scheduler 146 sets the β value to determine a discarded ratio r=DA where D is a sum of weights of dropped packets and A is a sum of weights of arrived packets (e.g., successfully received after transmission). In at least one embodiment, using a larger β value produces metrics in a manner closer to an "earliest deadline first" (EDF) policy, where vi=1di v i ensures that all packets can meet their deadlines when λ is very small. In at least one embodiment, using a smaller β value produces metrics in a manner closer to a max-weight policy, where vi=wini* maximizes the transmitted weight per RB and works well when λ is very large. In at least one embodiment, the packet transmission scheduler 146 generates transmission priority metrics using another suitable technique and / or based at least in part on another suitable formula. In at least one embodiment, the packet transmission scheduler 146 generates transmission priority metrics using one or more neural networks (e.g., one or more neural networks trained using a supervised learning technique to generate transmission priority metrics of packets based at least in part on the use of a number of RBs to be used, a latency requirement, and a weight of each packet).

[0027] Fig. 2 is a flowchart of a technique 200 for selecting a modulation and coding scheme and a number of resource blocks to be used, according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 200 are performed by one or more aspects related to Fig. 1 (e.g., processor 118, accelerator 122, error rate predictor 134, MCS selector 138, and / or RB identifier 142) and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein.

[0028] In at least one embodiment, the technique 200 includes, in a block 202, identifying packet information and requirements. In at least one embodiment, the packet information and requirements include one or more of a BLER target of each packet, a latency requirement of each packet, a weight assigned to each packet, a packet size, and / or other suitable packet information. In at least one embodiment, packet information and requirements are stored as packet information 136. In at least one embodiment, the error rate predictor 134 of Fig. 1 Packet information stored as packet information 136 as part of retrieving information to be used to predict one or more BLERs using one or more indications of the SNR.

[0029] In at least one embodiment, the technique 200 includes, in a block 204, predicting one or more error rates. In at least one embodiment, the error rates are block error rates of packets. In at least one embodiment, the error rates are block error rates of packets to be transmitted from a base station to a user equipment (UE) device. In at least one embodiment, the error rate predictor 134 of Fig. 1 the error rates in block 204 based at least in part on one or more indications of the SNR (e.g., one or more indications of the SNR 132 of Fig. 1) and packet information (e.g., one or more aspects of the packet information 136).

[0030] In at least one embodiment, the technique 200 includes identifying a modulation and coding scheme in a block 206. In at least one embodiment, the MCS selector 138 of Fig. 1 the MCS in block 206. In at least one embodiment, identifying the MCS includes storing packet MCS information (e.g., packet MCS information 140 of Fig. 1). In at least one embodiment, identifying the MCS is based at least in part on using the identified MCS to predict the BLER that satisfies a BLER requirement (e.g., in block 204).

[0031] In at least one embodiment, the technique 200 includes, in a block 208, identifying a number of resource blocks. In at least one embodiment, the resource blocks are a number of resource blocks to be used to transmit a packet. In at least one embodiment, the RB identifier 142 of Fig. 1 the number of RBs in block 208. In at least one embodiment, identifying the number of RBs includes storing RB information (e.g., RB information 144 of Fig. 1). In at least one embodiment, identifying the RB information is based at least in part on using the identified RB information to predict the BLER that satisfies the BLER requirement (e.g., in block 204).

[0032] In at least one embodiment, the technique 200 includes, in a block 210, performing other actions. In at least one embodiment, performing other actions includes returning to block 202 to identify additional packet information and requests for further packets (e.g., that have recently entered a queue to be transmitted). In at least one embodiment, performing other actions includes scheduling and transmitting packets (e.g., using the technique 300 of Fig. 3).

[0033] Fig. 3 is a flowchart of a technique 300 for scheduling and transmitting packets, according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 300 are performed by one or more aspects related to Fig. 1 (e.g., processor 118, accelerator 122, and / or packet transfer scheduler 146) and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein.

[0034] In at least one embodiment, the technique 300 includes, in a block 302, identifying packet information and requirements. In at least one embodiment, the packet information and requirements include a number of RBs to be used to transmit each packet (e.g., using the RB information 144 of Fig. 1), a weight and / or a latency requirement (e.g., using information from the packet information 136 of Fig. 1). In at least one embodiment, the packet transmission scheduler 146 identifies packet information and requirements to be used to schedule and transmit packets.

[0035] In at least one embodiment, the technique 300 includes, in a block 304, generating one or more metrics. In at least one embodiment, one or more metrics include one or more transmission priority metrics (e.g., one or more transmission priority metrics 148 of Fig. 1). In at least one embodiment, the packet transmission scheduler 146 generates Fig. 1 one or more metrics in block 304.

[0036] In at least one embodiment, the technique 300 includes, in a block 306, scheduling packet transmission. In at least one embodiment, scheduling packet transmission is based at least in part on one or more metrics generated in block 304. In at least one embodiment, scheduling packet transmission includes scheduling packet transmission in an order-based manner according to values ​​of metrics assigned to packets. In at least one embodiment, scheduling packet transmission includes scheduling packet transmission in an out-of-order manner. In at least one embodiment, the packet transmission scheduler 146 of Fig. 1 packets in block 306. In at least one embodiment, scheduling packet transmission includes assigning particular RBs to particular packets to be transmitted based at least in part on a number of RBs determined using the RB identifiers 142 of Fig. 1 (e.g. using RB Information 144).

[0037] In at least one embodiment, the technique 300 includes transmitting packets in a block 308. In at least one embodiment, a base station (e.g., base station 102 of Fig. 1) Packets to one or more UEs (e.g., UEs in the set of UEs 104). In at least one embodiment, transmitting packets includes transmitting packets according to the scheduled order using RBs assigned to each packet. In at least one embodiment, transmitting packets includes transmitting packets using the identified MCS level of each packet to be used (e.g., the packet MCS information 140).

[0038] In at least one embodiment, technique 300 includes performing other actions at a block 310. In at least one embodiment, performing other actions includes returning to block 302 to identify packet information and requests for additional packets to be scheduled and transmitted. In at least one embodiment, performing other actions includes checking information indicating whether the packet was successfully received. In at least one embodiment, performing other actions includes retransmitting one or more packets.

[0039] In at least one embodiment, one or more aspects of the technique 200 of Fig. 2 and / or the technology 300 of Fig. 3 predicting one or more wireless transmission error rates based at least in part on one or more SNR measurements (e.g., one or more indications of the SNR 132 of Fig. 1). In at least one embodiment, one or more aspects of technique 200 and / or technique 300 further include selecting an MCS (e.g., packet MCS information 140 from Fig. 1) based at least in part on one or more predicted wireless transmission error rates. In at least one embodiment, one or more aspects of the technique 200 of Fig. 2 and / or the technology 300 of Fig. 3 selecting a number of resource blocks (e.g. RB information 144 of Fig. 1) to be used to transmit data based at least in part on one or more predicted wireless transmission error rates. In at least one embodiment, one or more aspects of the technique 200 of Fig. 2 and / or the technology 300 of Fig. 3, selecting an MCS and a number of RBs to be used to transmit data based at least in part on one or more predicted wireless transmission error rates. In at least one embodiment, the wireless transmission error rates are block error rates (BLER) of packets received from a base station (e.g., base station 102 of Fig. 1) to one or more UE devices (e.g., one or more UEs in the set of UEs 104). In at least one embodiment, the wireless transmission error rates BLER of packets and one or more aspects of the technique 200 of Fig. 2 and / or the technology 300 of Fig. 3 further includes selecting an MCS and a number of RBs to be used to transmit data based at least in part on one or more predicted wireless transmission error rates, and generating one or more scheduling metrics based at least in part on the number of RBs. In at least one embodiment, a non-transitory computer-readable medium having stored thereon a set of instructions that, when executed by one or more processors (e.g., processor 118 and / or accelerator 122 of Fig. 1 and / or the processor 402 of Fig. 4) are executed, cause one or more processors to implement at least one or more aspects of the technique 200 of Fig. 2 and / or the technology 300 of Fig. 3 to be executed.

[0040] Fig. 4 is a block diagram illustrating an example of a processor 400 according to at least one embodiment. In at least one embodiment, a processor 402 performs one or more processes as described herein to predict one or more BLERs based at least in part on the SNR and / or to identify an MCS to be used and a number of RBs to be used to transmit one or more packets based at least in part on the predicted BLER. In at least one embodiment, the processor 402 performs one or more processes as described herein to schedule one or more packets to be transmitted based at least in part on a number of RBs identified using the predicted BLER.

[0041] In at least one embodiment, the processor 402 performs one or more aspects related to the processor 118, the accelerator 122, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, one or more aspects of the technology 200 of Fig. 2, the technology 300 of Fig. 3 and / or one or more APIs 510 of Fig. 5. In at least one embodiment, the processor 402 performs one or more processes such as those described in connection with Fig. 1-3 described.

[0042] In at least one embodiment, the processor 402 includes one or more processors such as those described in connection with Fig. 1 and / or one or more figures described below. In at least one embodiment, processor 402 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof. In at least one embodiment, the processor 402 includes a block error rate (BLER) estimation module 404, a modulation and coding scheme (MCS) identification module 406, a resource block (RB) identification module 408, an order metric generation module 410, and a packet transmission scheduling module 412. In at least one embodiment, the BLER estimation module 404, the MCS identification module 406, the RB identification module 408, the order metric generation module 410, and / or the packet transmission scheduling module 412 are part of the processor 402 and / or one or more other processors.In at least one embodiment, the BLER estimation module 404, the MCS identification module 406, the RB identification module 408, the order metric generation module 410, and / or the packet transmission scheduling module 412 are distributed across multiple processors that communicate via a bus, a network, by writing to shared memory, and / or any suitable communication process as described herein. In at least one embodiment, the BLER estimation module 404 is referred to as a BLER prediction module and / or another suitable name. In at least one embodiment, the MCS identification module 406 is referred to as an MCS selection module and / or another suitable name. In at least one embodiment, the RB identification module 408 is referred to as an RB selection module and / or another suitable name.

[0043] In at least one embodiment, a module, as used in any implementation described herein, unless otherwise clear from context or expressly indicated to the contrary, refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein.In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions to be executed and / or performed by programmable circuitry. In at least one embodiment, modules may be embodied collectively or individually as circuitry that forms part of a larger system, for example, an integrated circuit (IC), a system on a chip (SoC), and so on.In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0044] In at least one embodiment, the BLER estimation module 404 is a module that estimates the BLER based at least in part on the SNR (e.g., one or more indications of the SNR 132 from Fig. 1). In at least one embodiment, the BLER estimation module 404 is a module that predicts the BLER based at least in part on the SNR. In at least one embodiment, the BLER estimation module 404 performs one or more aspects related to the error rate predictor 134 of Fig. 1 and / or the technology 200 from Fig. 2. In at least one embodiment, the MCS identification module 406 is a module that identifies one or more MCS (e.g., packet MCS information 140 of Fig. 1) identifies and / or selects packets to be used to transmit one or more packets (e.g., URLLC packets). In at least one embodiment, the MCS identification module 406 performs one or more aspects related to the MCS selector 138 of Fig. 1 and / or the technology 200 of Fig. 2. In at least one embodiment, the RB identification module 408 is a module that identifies and / or selects a number of RBs to be used to identify one or more packets (e.g., RB information 144 from Fig. 1). In at least one embodiment, the RB identification module 408 performs one or more aspects related to the RB identifier 142 of Fig. 1 and / or the technology 200 of Fig. 2 are shown or described.

[0045] In at least one embodiment, the order metric generation module 410 is a module that generates one or more order metrics (e.g., transmission priority metrics 148 of Fig. 1) based at least in part on a number of RBs to be selected by predicting the BLER based at least in part on the SNR (e.g., by the RB identification module 408). In at least one embodiment, the order metric generation module 410 performs one or more aspects related to the packet transmission scheduler 146 of Fig. 1 and / or the technology 300 of Fig. 3. In at least one embodiment, the packet transmission scheduling module 412 is a module that schedules packet transmission based at least in part on transmission order metrics generated using the order metric generation module 410. In at least one embodiment, the packet transmission scheduling module 412 includes the order metric generation module 410. In at least one embodiment, the packet transmission scheduling module performs one or more aspects related to the packet transmission scheduler 142 of Fig. 1 and / or the technology 300 of Fig. 3 are shown or described.

[0046] In at least one embodiment, a processor (e.g., processor 402 of Fig. 4 and / or the processor 118 and / or the accelerator 122 of Fig. 1) one or more circuits for predicting one or more wireless transmission error rates based at least in part on one or more SNR measurements (e.g., one or more indications of the SNR 132 of Fig. 1). In at least one embodiment, one or more circuits are to cause a modulation and coding scheme (e.g., the packet MCS information 140) to be selected based at least in part on the predicted one or more wireless transmission error rates. In at least one embodiment, one or more circuits are to cause a number of resource blocks (e.g., the RB information 144 of Fig. 1) is selected based at least in part on the predicted one or more wireless transmission error rates. In at least one embodiment, one or more circuits are to cause a modulation and coding scheme and a number of resource blocks to be selected based at least in part on the predicted one or more wireless transmission error rates. In at least one embodiment, one or more SNR measurements are based at least in part on one or more indications of channel quality (e.g., the CQI 130 of Fig. 1) between a base station and one or more UE devices. In at least one embodiment, one or more circuits are to cause an MCS to be selected based at least in part on the predicted one or more wireless transmission error rates, and to cause one or more packets to be transmitted based at least in part on the selected MCS. In at least one embodiment, one or more circuits are to cause a number of resource blocks to be selected based at least in part on the predicted one or more wireless transmission error rates, to cause one or more transmission priority metrics (e.g., the transmission priority metrics 148 of Fig. 1) based at least in part on the number of resource blocks, and causing one or more packets to be transmitted based at least in part on the generated one or more transmission priority metrics.

[0047] In at least one embodiment, a system (e.g., the system 100 of Fig. 1) one or more processors (e.g., processor 402 of Fig. 4 and / or the processor 118 and / or the accelerator 122 of Fig. 1) predicting one or more wireless transmission error rates based at least in part on one or more SNR measurements (e.g., one or more indications of the SNR 132 of Fig. 1). In at least one embodiment, one or more wireless transmission error rates are block error rates (BLER) of packets to be transmitted to one or more UE devices. In at least one embodiment, one or more processors are to cause an MCS (e.g., the packet MCS information 140 of Fig. 1) is selected based at least in part on one or more predicted wireless transmission error rates. In at least one embodiment, one or more processors are to cause a number of resource blocks (e.g., the RB information 144 of Fig. 1) is selected to transmit a particular packet based at least in part on one or more wireless transmission error rates. In at least one embodiment, one or more SNR measurements are based at least in part on one or more indications of channel quality (e.g., the CQI 130 of Fig. 1) that is sent from a gNodeB (e.g. the base station 102 of Fig. 1) from one or more UE devices (e.g., the UE 106 of Fig. 1) are received. In at least one embodiment, one or more processors are also to cause a number of resource blocks to be selected to transmit a particular packet based at least in part on the predicted one or more wireless transmission error rates, and to cause a particular packet to be scheduled to be transmitted based at least in part on the number of resource blocks.

[0048] Fig. 5 is a block diagram illustrating a driver and / or runtime environment 500 including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, a software program 502 is a software module. In at least one embodiment, a software program 502 includes one or more software modules, including, but not limited to, those described herein at least in connection with Fig. 4. In at least one embodiment, a software module is further not exclusively in Fig. 4. In at least one embodiment, one or more APIs 510 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, executing software instructions includes executing software instructions. In at least one embodiment, one or more aspects of one or more software modules associated with Fig. 4, partly in the software program 502 (e.g., instructions and / or code for calling a function when executed by a processor) and partly in one or more APIs 510 and / or functions 512 (e.g., instructions and / or code that implement the called function when executed by a processor).

[0049] In at least one embodiment, one or more APIs 510 are distributed or otherwise provided as part of one or more libraries 506, drivers and / or runtimes 504, and / or any other grouping of software, non-transitory computer-readable instructions, and / or executable code further described herein. In at least one embodiment, one or more APIs 510 perform one or more computational operations in response to being invoked by software programs 502. In at least one embodiment, a software program 502 is a collection of software code, commands, instructions, or other text sequences to instruct a computing device to perform one or more computational operations and / or to invoke one or more other sets of instructions, such as APIs 510 or API functions 512, to be executed.In at least one embodiment, the functionality provided by one or more APIs 510 includes software functions 512, such as those that can be used to accelerate one or more portions of software programs 502 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, APIs 510 and / or API functions 512 include APIs and / or functions for performing one or more aspects related to the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of FIG. Fig. 1, the technology 200 of Fig. 2 and / or the technology 300 of Fig. 3 are shown or described.

[0050] In at least one embodiment, APIs 510 are hardware interfaces to one or more circuits to perform one or more computational operations. In at least one embodiment, one or more software APIs 510 described herein are implemented as one or more circuits to perform one or more techniques described herein in connection with Fig. 1-4. In at least one embodiment, one or more software programs 502 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described herein in connection with Fig. 1-4. In at least one embodiment, one or more software programs 502 use one or more APIs 510 provided by a driver and / or a runtime 504 to manage virtual memory and / or allocate or otherwise reserve one or more memory blocks 514 to one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 502 use one or more APIs 510 provided by a driver and / or a runtime 504 to manage virtual memory and / or allocate or otherwise reserve memory blocks.

[0051] In at least one embodiment, software programs 502, such as user-implemented software programs, use one or more application programming interfaces (APIs) 510 to perform various computational operations, such as memory allocation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 510 provide a set of callable functions 512, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, a processor uses an API that includes a predictive block error rate function 516.In at least one embodiment, the predictive block error rate function 516 implements one or more aspects of the error rate predictor 134 of FIG. Fig. 1, the technology 200 of Fig. 2 and / or the BLER estimation module 404 of Fig. 4. In at least one embodiment, a processor uses an API that includes an MCS selection function 518. In at least one embodiment, the MCS selection function 518 implements one or more aspects of the MCS selector 138 of Fig. 1, the technology 200 of Fig. 2 and / or the MCS identification module 406 of Fig. 4. In at least one embodiment, a processor uses an API that includes a function 520 for identifying a number of resource blocks (RBs). In at least one embodiment, the function 520 for identifying a number of RBs implements one or more aspects of the RB identifiers 142 of Fig. 1, the technology 200 of Fig. 2 and / or the RB identification module 408 of Fig. 4. In at least one embodiment, a processor uses an API that includes a function 522 for generating an order metric. In at least one embodiment, the function 522 for generating an order metric performs one or more aspects of the packet transmission scheduler 146 of Fig. 1, the technology 300 of Fig. 3, of the order metric generation module 410 of Fig. 4 and / or the packet transmission scheduling module 412 of Fig. 4. In at least one embodiment, the set of callable functions 512 includes a different number of functions (e.g., a separate function for executing one or more aspects of the packet transmission scheduling module 412 of Fig. 4).

[0052] In at least one embodiment, one or more software programs 502 interact with or otherwise communicate with one or more APIs 510 to perform one or more computational operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations to be accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 502 interact with one or more APIs 510 to enable parallel computing using a remote or local interface.

[0053] In at least one embodiment, an interface is software instructions that, when executed, provide access to one or more functions 512 provided by one or more APIs 510. In at least one embodiment, a software program 502 uses a local interface when a software developer compiles one or more software programs 502 in conjunction with one or more libraries 506 that include or otherwise provide access to one or more APIs 510. In at least one embodiment, one or more software programs 502 are statically compiled in conjunction with precompiled libraries 506 or uncompiled source code that includes instructions to execute one or more APIs 510.In at least one embodiment, one or more software programs 502 are dynamically compiled, and the one or more software programs use a linker to link one or more precompiled libraries 506 that include one or more APIs 510.

[0054] In at least one embodiment, a software program 502 uses a remote interface when a software program uses or otherwise communicates with a library 506 comprising one or more APIs 510 over a network or other remote communication medium. In at least one embodiment, one or more libraries 506 comprising one or more APIs 510 are to be executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 506 comprising one or more APIs 510 are to be executed by any other computing host that provides the one or more APIs 510 to one or more software programs 502.

[0055] In at least one embodiment, a processor executing or using one or more software programs 502 calls, utilizes, or otherwise implements one or more APIs 510 to allocate and otherwise manage memory to be used by the software programs 502. In at least one embodiment, one or more software programs 502 use one or more APIs 510 to allocate and otherwise manage memory to be used by one or more portions of the software programs 502 to be accelerated using one or more PPUs, such as GPUs or any other accelerator or processor further described herein.

[0056] In at least one embodiment, an API of one or more APIs 510 is an API to enable parallel computing. In at least one embodiment, one or more APIs 510 include any other APIs further described herein. In at least one embodiment, one or more APIs 510 are provided by a driver and / or a runtime 504. In at least one embodiment, an API of one or more APIs 510 is provided by a CUDA user-mode driver. In at least one embodiment, an API of one or more APIs 510 is provided by a CUDA runtime. In at least one embodiment, a driver 504 is data values ​​and software instructions that, when executed, perform or otherwise enable the operation of one or more functions 512 of an API 510 during the loading and execution of one or more portions of a software program 502.In at least one embodiment, drivers and / or runtimes 504 are data values ​​and software instructions that, when executed, perform or otherwise enable the operation of one or more functions 512 of an API 510 during execution of a software program 502. In at least one embodiment, one or more software programs 502 use one or more APIs 510 implemented or otherwise provided by a driver and / or runtime 504 to perform combined arithmetic operations by one or more software programs 502 during execution by one or more PPUs, such as GPUs. DATA CENTER

[0057] Fig. 6 illustrates an example data center 600 in which at least one embodiment may be used. In at least one embodiment, the data center 600 includes a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

[0058] In at least one embodiment, as in Fig. 6, the data center infrastructure layer 610 may include a resource orchestrator 612, clustered compute resources 614, and node compute resources ("Node CRs") 616(1)-616(N), where "N" represents any whole positive integer. In at least one embodiment, the Node CRs 616(1)-616(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more Node CRs may be selected from the Node CRs 616(1)-616(N) may be a server that has one or more of the computing resources listed above.

[0059] In at least one embodiment, the grouped computing resources 614 may include separate groupings of node CRs housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped computing resources 614 may include grouped computing, networking, storage, or memory resources that may be configured or assigned to support one or more workloads. In at least one embodiment, multiple node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0060] In at least one embodiment, the resource orchestrator 612 may configure or otherwise control one or more node CRs 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, the resource orchestrator 612 may include a software design infrastructure ("SDI") management entity for the data center 600. In at least one embodiment, the resource orchestrator may include hardware, software, or a combination thereof.

[0061] In at least one embodiment, as in Fig. 6, the framework layer 620 includes a job scheduler 632, a configuration manager 634, a resource manager 636, and a distributed file system 638. In at least one embodiment, the framework layer 620 may include a framework to support software 632 of the software layer 630 and / or one or more applications 642 of the application layer 640. In at least one embodiment, the software 632 or application(s) 642 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 620 may be some type of free and open source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize the distributed file system 638 for large-scale data processing (e.g., "Big Data").In at least one embodiment, job scheduler 632 may include a Spark driver to enable scheduling of workloads supported by different layers of data center 600. In at least one embodiment, configuration manager 634 may be capable of configuring different layers, such as software layer 630 and framework layer 620, including Spark and distributed file system 638, to support large-scale computing. In at least one embodiment, resource manager 636 may be capable of managing clustered or grouped compute resources mapped to or allocated to support distributed file system 638 and job scheduler 632. In at least one embodiment, clustered or grouped compute resources may include clustered compute resource 614 in data center infrastructure layer 610.In at least one embodiment, the resource manager 636 may coordinate with the resource orchestrator 612 to manage these mapped or allocated compute resources.

[0062] In at least one embodiment, the software 632 included in the software layer 630 may include software used by at least portions of the node CRs 616(1)-616(N), the clustered computing resources 614, and / or the distributed file system 638 of the framework layer 620. In at least one embodiment, one or more types of software may include, but are not limited to, internet website search software, email virus scanning software, database software, and streaming video content software.

[0063] In at least one embodiment, the application(s) 642 included in the application layer 640 may include one or more types of applications used by at least portions of the node CRs 616(1)-616(N), the clustered compute resources 614, and / or the distributed file system 638 of the framework layer 620. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computation, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0064] In at least one embodiment, any of configuration manager 634, resource manager 636, and resource orchestrator 612 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 600 from making potentially poor configuration decisions and potentially avoid underutilized and / or poorly performing portions of a data center.

[0065] In at least one embodiment, data center 600 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 600.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 600 by using weighting parameters calculated by one or more training techniques described herein.

[0066] In at least one embodiment, the data center 600 may utilize CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0067] In at least one embodiment, at least one component related to Fig. 6 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 6, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one of the grouped computing resources 614 and the node CR 616 are used to perform a selection of packet MCS information 140, an identification of RB information 144, a generation of transmission priority metrics 148, a generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one of the grouped computing resources 614 and the node CR 616 perform at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0068] Fig. 7A illustrates an example of an autonomous vehicle 700 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 700 (alternatively referred to herein as "vehicle 700") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 700 may be a semi-trailer truck used to transport cargo. In at least one embodiment, the vehicle 700 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0069] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of this standard). In one or more embodiments, vehicle 700 may be capable of operating according to one or more of Levels 1-5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 700 may be capable of conditionally automating (Level 3), highly automating (Level 4), and / or fully automating (Level 5), depending on the embodiment.

[0070] In at least one embodiment, vehicle 700 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 700 may include, without limitation, a propulsion system 750, such as an internal combustion engine, a hybrid electric power plant, a pure electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 750 may be connected to a drivetrain of vehicle 700, which may include, without limitation, a transmission, to facilitate propulsion of vehicle 700. In at least one embodiment, propulsion system 750 may be controlled in response to receiving signals from throttle / accelerator pedal(s) 752.

[0071] In at least one embodiment, a steering system 754, which may include, without limitation, a steering wheel, is used to steer a vehicle 700 (e.g., along a desired path or route) when a propulsion system 750 is operating (e.g., when the vehicle is in motion). In at least one embodiment, a steering system 754 may receive signals from steering actuator(s) 756. In at least one embodiment, the steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 746 may be used to apply vehicle brakes in response to receiving signals from brake actuator(s) 748 and / or brake sensors.

[0072] In at least one embodiment, the controller(s) 736, which may include, without limitation, one or more system-on-chips (“SoCs”) (in Fig. 7A not shown) and / or graphics processing unit(s) ("GPU(s)"), provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 700. For example, in at least one embodiment, the controller(s) 736 may send signals to apply vehicle brakes via brake actuators 748, to apply the steering system 754 via steering actuator(s) 756, to apply the propulsion system 750 via throttle / accelerator pedal(s) 752. In at least one embodiment, the controller(s) 736 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving the vehicle 700.In at least one embodiment, the controller(s) 736 may include a first controller 736 for autonomous driving functions, a second controller 736 for functional safety functions, a third controller 736 for the artificial intelligence function (e.g., computer vision), a fourth controller 736 for infotainment functionality, a fifth controller 736 for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller 736 may handle two or more of the above functionalities, two or more controllers 736 may handle a single functionality, and / or any combination thereof.

[0073] In at least one embodiment, the controller(s) 736 provide signals to control one or more components and / or systems of the vehicle 700 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be obtained, for example and without limitation, from Global Navigation Satellite System ("GNSS") sensor(s) 758 (e.g., Global Positioning System sensor(s), RADAR sensor(s) 760, Ultrasonic sensor(s) 762, LIDAR sensor(s) 764, Inertial Measurement Unit ("IMU") sensor(s) 766 (e.g., accelerometer, gyroscope(s), magnetic compass(es), magnetometer, etc.), microphone(s) 796, stereo camera(s) 768, wide-view camera(s) 770 (e.g., fisheye cameras), infrared camera(s) 772, surround camera(s) 774 (e.g.,360-degree cameras), long-range cameras (not in . Fig. 7A), (a) medium-range camera(s) (not shown in Fig. 7A), speed sensor(s) 744 (e.g., for measuring the speed of vehicle 700), vibration sensor(s) 742, steering sensor(s) 740, brake sensor(s) (e.g., as part of brake sensor system 746), and / or other types of sensors.

[0074] In at least one embodiment, one or more of the controller(s) 736 may receive inputs (e.g., represented by input data) from an instrument cluster 732 of the vehicle 700 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 734, an audible indicator, a speaker, and / or via other components of the vehicle 700. In at least one embodiment, outputs may include information such as vehicle speed, velocity, time, map data (e.g., a high-resolution map (not shown in Fig. 7A), location data (e.g., location of vehicle 700, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 736, etc. In at least one embodiment, HMI display 734 may, for example, display information about the presence of one or more objects (e.g., a road sign, warning sign, traffic light change, etc.) and / or information about maneuvers the vehicle has undertaken, is undertaking, or is undertaking (e.g., changing lanes, entering exit 34B in two miles, etc.).

[0075] In at least one embodiment, the vehicle 700 further includes a network interface 724 that may utilize wireless antenna(s) 726 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 724 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. In at least one embodiment, the wireless antenna(s) 726 may also facilitate communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network(s) such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc. and / or low power wide area network(s) ("LPWANs") such as LoRaWAN, SigFox, etc.make possible.

[0076] In at least one embodiment, at least one component related to Fig. 7A, is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, signals from the vehicle 700 for its autonomous operation and / or may be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, perform one or more operations (e.g., predicting the BLER using the CQI from the vehicle 700 and / or scheduling packets) related to the transmission of information (e.g., transmitted in URLLC packets) to the vehicle 700. In at least one embodiment, the vehicle 700 is to perform techniques and / or functions associated with one or more UEs (e.g., UE 106) in the set of UEs 104 of Fig. 1 are described.

[0077] Fig. Figure 7B illustrates an example of camera positions and fields of view for the autonomous vehicle 700 of Fig. 7A according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at various positions on the vehicle 700.

[0078] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 700. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, camera types may be capable of achieving any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof.In at least one embodiment, the color filter array may include a red-clear-clear-clear color filter array ("RCCC"), a red-clear-clear-blue color filter array ("RCCB"), a red-blue-green-clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0079] In at least one embodiment, one or more of the camera(s) may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more of the camera(s) (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0080] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to block stray light and reflections from inside a car (e.g., dashboard reflections reflected in windshield mirrors) that may interfere with a camera's image data collection capabilities. With reference to wing mirror mounting assemblies, in at least one embodiment, wing mirror assemblies may be custom 3D printed so that the camera mounting plate conforms to the shape of the wing mirror. In at least one embodiment, camera(s) may be integrated into the wing mirror. In at least one embodiment, camera(s) for side-view cameras may also be integrated into four pillars at each corner of the car.

[0081] In at least one embodiment, cameras with a field of view that includes portions of the environment in front of the vehicle 700 (e.g., forward-facing cameras) may be used for surround vision to help identify forward paths and obstacles, as well as to help provide information critical to generating an occupancy grid and / or determining preferred vehicle paths using one or more of the controllers 736 and / or control SoCs. In at least one embodiment, forward-facing cameras may be used to perform many of the same ADAS functions as LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, but not limited to, Lane Departure Warning (“LDW”), Autonomous Cruise Control (“ACC”), and / or other features such as Traffic Sign Recognition.

[0082] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform incorporating a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, the far-view camera 770 may be used to perceive objects coming into view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 7B illustrates only one wide-view camera 770, in other embodiments, there may be any number (including zero) of wide-view camera(s) 770 on the vehicle 700. In at least one embodiment, any number of long-range camera(s) 798 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 798 may also be used for object detection and classification, as well as basic object tracking.

[0083] In at least one embodiment, any number of stereo cameras 768 may also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 768 may include an integrated control unit comprising a scalable processing unit that may provide a field-programmable gate array (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the surroundings of the vehicle 700, including a distance estimate for all points in the image.In at least one embodiment, one or more of the stereo camera(s) 768 may include, among other things, one or more compact stereo vision sensors, which may include, among other things, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance from the vehicle 700 to the target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 768 may be used in addition to or alternatively to those described herein.

[0084] In at least one embodiment, cameras with a field of view that includes portions of the environment adjacent to the vehicle 700 (e.g., side view cameras) may be used for surround vision, providing information used to create and update an occupancy grid and generate side impact collision warnings. For example, in at least one embodiment, one or more surround cameras 774 (e.g., four surround cameras 774, as in Fig. 7B) may be positioned on the vehicle 700. In at least one embodiment, the surround view camera(s) 774 may include, but are not limited to, any number and combination of wide view camera(s) 770, fisheye camera(s), 360-degree camera(s), and / or the like. For example, in at least one embodiment, four fisheye cameras may be positioned on the front, rear, and sides of the vehicle 700. In at least one embodiment, the vehicle 700 may utilize three surround view camera(s) 774 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround view camera.

[0085] In at least one embodiment, cameras with a field of view that includes portions of the environment behind the vehicle 700 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 798 and / or medium-range camera(s) 776, stereo camera(s) 768), infrared camera(s) 772, etc.), as described herein.

[0086] In at least one embodiment, at least one component related to Fig. 7B, is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, signals from the vehicle 700 for its autonomous operation and / or may be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, perform one or more operations (e.g., predicting the BLER using the CQI from the vehicle 700 and / or scheduling packets) related to the transmission of information (e.g., transmitted in URLLC packets) to the vehicle 700. In at least one embodiment, the vehicle 700 is to perform techniques and / or functions associated with one or more UEs (e.g., UE 106) in the set of UEs 104 of Fig. 1 are described.

[0087] Fig. 7C is a block diagram illustrating an example system architecture for the autonomous vehicle 700 of Fig. 7A according to at least one embodiment. In at least one embodiment, all components, features, and systems of the vehicle 700 are Fig. 7C as connected via a bus 702. In at least one embodiment, bus 702 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 700 used to assist in controlling various features and functions of vehicle 700, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 702 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 702 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPMs"), button positions, and / or other vehicle status indicators.In at least one embodiment, bus 702 may be a CAN bus that is ASIL B compliant.

[0088] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses 702, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using a different protocol. In at least one embodiment, two or more buses 702 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 702 may be used for the collision avoidance function and a second bus 702 may be used for actuation control. In at least one embodiment, each bus 702 may communicate with any of the components of the vehicle 700, and two or more buses 702 may communicate with the same components.In at least one embodiment, each of any number of system(s) on chip (“SoC(s)”) 704, each of the controller(s) 736, and / or each computer within the vehicle may have access to the same input data (e.g., inputs from sensors of the vehicle 700) and may be connected to a common bus, such as a CAN bus.

[0089] In at least one embodiment, the vehicle 700 may include one or more controllers 736, such as those described herein with respect to Fig. 7A. In at least one embodiment, the controller(s) 736 may be used for a variety of functions. In at least one embodiment, the controller(s) 736 may be coupled to any of various other components and systems of the vehicle 700 and may be used to control the vehicle 700, artificial intelligence of the vehicle 700, infotainment for the vehicle 700, and / or the like.

[0090] In at least one embodiment, the vehicle 700 may include any number of SoCs 704. Each of the SoCs 704 may include, among other things, central processing units ("CPU(s)") 706, graphics processing units ("GPU(s)") 708, processor(s) 710, cache(s) 712, accelerators 714, data storage 716, and / or other unillustrated components and features. In at least one embodiment, the SoC(s) 704 may be used to control the vehicle 700 in a variety of platforms and systems. For example, in at least one embodiment, the SoC(s) 704 may be combined in a system (e.g., system of the vehicle 700) with a high-definition ("HD") map 722 that may receive map updates and / or updates via the network interface 724 from one or more servers (not shown). Fig. 7C).

[0091] In at least one embodiment, the CPU(s) 706 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 706 may include multiple cores and / or level-two ("L2") caches. For example, in at least one embodiment, the CPU(s) 706 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 706 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 MB L2 cache). In at least one embodiment, the CPU(s) 706 (e.g., CCPLEX) may be configured to support concurrent cluster operation, allowing any combination of clusters of the CPU(s) 706 to be active at any given time.

[0092] In at least one embodiment, one or more of the CPU(s) 706 may implement power management capabilities including, without limitation, one or more of the following features: individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when the core is not actively executing due to the execution of wait-for-interrupt ("WFI") / wait-for-event ("WFE") instructions; each core may be independently clocked; each core cluster may be independently clocked when all cores are clocked or unclocked; and / or each core cluster may be independently clocked when all cores are clocked.In at least one embodiment, CPU(s) 706 may further implement an advanced performance state management algorithm, where allowed performance states and expected wake-up times are specified, and hardware / microcode determines the best performance state to enter for the core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified performance state entry sequences in software with work offloaded to microcode. In at least one embodiment, processing cores are referred to as compute units or compute units.

[0093] In at least one embodiment, the GPU(s) 708 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, the GPU(s) 708 may be programmable and may be efficient for parallel workloads. In at least one embodiment, the GPU(s) 708 may use an extended tensor instruction set. In at least one embodiment, the GPU(s) 708 may include one or more streaming microprocessors, where each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with a memory capacity of at least 96 KB) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 708 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 708 may utilize one or more computing application programming interfaces (APIs). In at least one embodiment, the GPU(s) 708 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0094] In at least one embodiment, one or more of the GPU(s) 708 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 708 may be fabricated on a fin field-effect transistor ("FinFET"). In at least one embodiment, each streaming microprocessor may include a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be assigned 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision TENSOR COREs for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0095] In at least one embodiment, one or more of the GPU(s) 708 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or alternatively to the HBM memory, a synchronous graphics random access memory ("SGRAM") may be used, such as a double data rate type five synchronous graphics random access memory ("GDDR5").

[0096] In at least one embodiment, the GPU(s) 708 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to enable the GPU(s) 708 to directly access the page tables of the CPU(s) 706. In at least one embodiment, when the memory management unit ("MMU") of the GPU(s) 708 experiences a fault, an address translation request may be transmitted to the CPU(s) 706. In response, in at least one embodiment, the CPU(s) 706 may look up a virtual-to-physical mapping by address in their page tables and transmit the translation back to the GPU(s) 708.In at least one embodiment, the unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 706 and the GPU(s) 708, thereby simplifying programming the GPU(s) 708 and porting applications to the GPU(s) 708.

[0097] In at least one embodiment, the GPU(s) 708 may include any number of access counters that can track the frequency of access by the GPU(s) 708 to the memory of other processors. In at least one embodiment, the access counter(s) can help ensure that memory pages are moved to the physical memory of the processor that accesses pages most frequently, thereby improving efficiency for memory shared between processors.

[0098] In at least one embodiment, one or more of the SoC(s) 704 may include any number of cache(s) 712, including those described herein. For example, in at least one embodiment, the cache(s) 712 may include a level-three ("L3") cache available to both the CPU(s) 706 and the GPU(s) 708 (e.g., connected to both the CPU(s) 706 and the GPU(s) 708). In at least one embodiment, the cache(s) 712 may include a write-back cache that can track states of lines, such as using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0099] In at least one embodiment, one or more of the SoC(s) 704 may include one or more accelerators 714 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 704 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement the GPU(s) 708 and offload some tasks from the GPU(s) 708 (e.g., to free up more cycles of the GPU(s) 708 to perform other tasks). In at least one embodiment, the accelerator(s) 714 could be configured for targeted workloads (e.g.,Perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are robust enough to be amenable to acceleration may be used. In at least one embodiment, a CNN may include a region-based or regional convolutional neural network ("RCNNs") and fast RCNNs (e.g., as used for object detection) or another type of CNN.

[0100] In at least one embodiment, the accelerator(s) 714 (e.g., the hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). The DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). The DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as inference. In at least one embodiment, the design of the DLA(s) may provide more performance per millimeter than a typical general-purpose GPU and typically significantly exceeds the performance of a CPU.In at least one embodiment, the TPU(s) may perform multiple functions, including a single-instance convolution function supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, the DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification using data from microphones 796; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety and / or security-related events.

[0101] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 708, and by using an inference accelerator, for example, a designer may target either the DLA(s) or the GPU(s) 708 for any function. For example, in at least one embodiment, the designer may focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 708 and / or the other accelerator(s) 714.

[0102] In at least one embodiment, the accelerator(s) 714 (e.g., the hardware acceleration cluster) may include one or more programmable vision accelerators ("PVAs"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA(s) may be designed and configured to accelerate computer vision algorithms for the advanced driver assistance system ("ADAS") 738, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. The PVA(s) may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA(s) may include, for example and without limitation, any number of reduced instruction set computing ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0103] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any of the cameras described herein), image signal processor(s), and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application-specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, RISC cores may include an instruction cache and / or tightly coupled RAM.

[0104] In at least one embodiment, DMA may enable components of PVA(s) to access system memory independently of CPU(s) 706. In at least one embodiment, DMA may support any number of features used to provide optimization for PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0105] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as a primary processing engine of PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

[0106] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. Consequently, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image.In at least one embodiment, vector processors included in a particular PVA may concurrently execute different computer vision algorithms on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each of the PVAs. In at least one embodiment, the PVA(s) may include additional error-correcting code ("ECC") memory to improve overall system security.

[0107] In at least one embodiment, the accelerator(s) 714 (e.g., the hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM to the accelerator(s) 714. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, consisting of, for example, and without limitation, eight field-configurable memory blocks accessible by both PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, PVA and DLA may access memory via a backbone that provides PVA and DLA with high-speed access to memory. In at least one embodiment, the backbone may include an on-chip computer vision network that connects PVA and DLA to memory (e.g., using APB).

[0108] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both PVA and DLA are ready and providing valid signals prior to transmitting any control signal / address / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communications for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0109] In at least one embodiment, one or more of the SoC(s) 704 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine positions and dimensions of objects (e.g., within a world model) to generate real-time visualization simulations for radar signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general wave propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or for other uses.

[0110] In at least one embodiment, the accelerator(s) 714 (e.g., the hardware accelerator cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA are a good match for algorithmic domains that require predictable, low-power, and low-latency processing. In other words, the PVA performs well on semi-dense or dense regular computation, even on small datasets that require predictable, low-latency, and low-performance runtimes.In at least one embodiment, autonomous vehicles, such as vehicle 700, PVAs are designed to execute classical computer vision algorithms because they are efficient at object detection and operate on integer mathematics.

[0111] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications use motion estimation / on-the-fly stereo matching (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, the PVA may perform a computer stereo vision function on inputs from two monocular cameras.

[0112] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA could process raw radar data (e.g., using a 4D fast Fourier transform) to provide processed radar data. In at least one embodiment, the PVA is used for runtime depth processing, for example, by processing raw runtime data to provide processed runtime data.

[0113] In at least one embodiment, the DLA may be used to execute any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be represented or interpreted as a probability or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence allows a system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, a system may set a confidence threshold and consider only detections that exceed the threshold as true positives.In an embodiment where an automatic emergency braking ("AEB") system is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections may be considered triggers for AEB. In at least one embodiment, the DLA may execute a neural network to reduce the confidence score. In at least one embodiment, the neural network may accept as its input at least a subset of parameters, such as bounding box dimensions, ground plane estimation obtained (e.g., from another subsystem), output from IMU sensor(s) 766 correlated with the orientation of the vehicle 700, distance, 3D position estimates of the object obtained from the neural network, and / or other sensors (e.g., LIDAR sensor(s) 764 or RADAR sensor(s) 760), among others.

[0114] In at least one embodiment, one or more of the SoC(s) 704 may include data storage 716 (e.g., memory). In at least one embodiment, the data storage(s) 716 may be on-chip memory of the SoC(s) 704 that may store neural networks to be executed on the GPU(s) 708 and / or DLA. In at least one embodiment, the data storage(s) 716 may be large enough in capacity to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data storage(s) 712 may include L2 or L3 cache(s).

[0115] In at least one embodiment, one or more of the SoC(s) 704 may include any number of processor(s) 710 (e.g., embedded processors). In at least one embodiment, the processor(s) 710 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC(s) 704 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assistance with system low-power state transitions, management of thermal and temperature sensors of the SoC(s) 704, and / or management of power states of the SoC(s) 704.In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC(s) 704 may use ring oscillators to detect temperatures of the CPU(s) 706, the GPU(s) 708, and / or the accelerator(s) 714. In at least one embodiment, if temperatures are determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place the SoC(s) 704 into a lower power state and / or place the vehicle 700 into a chauffeur-into-safe-stop mode (e.g., bring the vehicle 700 to a safe stop).

[0116] In at least one embodiment, the processor(s) 710 may further include a set of embedded processors that may serve as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0117] In at least one embodiment, the processor(s) 710 may further include an always-on processor engine that may provide necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic.

[0118] In at least one embodiment, the processor(s) 710 may further include a security cluster engine, including, without limitation, a dedicated processor subsystem to handle security management for automotive applications. In at least one embodiment, the security cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a security mode, two or more cores, in at least one embodiment, may operate in a lockstep mode, functioning as a single core with comparison logic to detect differences between their operations.In at least one embodiment, the processor(s) 710 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 710 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of the camera processing pipeline.

[0119] In at least one embodiment, the processor(s) 710 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a playback window. In at least one embodiment, the video image compositor may perform lens distortion correction on one or more wide-view cameras 770, one or more surround-view cameras 774, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensor(s) is / are preferably monitored by a neural network running on another instance of the SoC 704 configured to identify and respond to in-cabin events.In at least one embodiment, a system in the cabin may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in an autonomous mode and are otherwise disabled.

[0120] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in a video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by neighboring frames. In at least one embodiment, when an image or a portion of an image contains no motion, the temporal noise reduction performed by the video image compositor may use information from a previous frame to reduce noise in the current frame.

[0121] In at least one embodiment, the video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, the video image compositor may further be used for user interface composition when an operating system desktop is used, and one or more GPUs 708 are not required to continuously render new surfaces. In at least one embodiment, when one or more GPUs 708 are turned on and actively performing 3D rendering, the video image compositor may be used to offload one or more GPUs 708 to improve performance and responsiveness.

[0122] In at least one embodiment, one or more of the SoC(s) 704 may further include a Mobile Industrial Processor Interface ("MIPI") serial camera interface for receiving video and inputs from cameras, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoC(s) 704 may further include one or more input / output controllers that may be controlled by software and used to receive I / O signals that are not committed to a specific role.

[0123] In at least one embodiment, one or more of the SoC(s) 704 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. The SoC(s) 704 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LIDAR sensor(s) 764, RADAR sensor(s) 760, etc., which may be connected via Ethernet), data from the bus 702 (e.g., speed of the vehicle 700, steering wheel position, etc.), data from one or more GNSS sensors 758 (e.g., connected via Ethernet or CAN bus), etc.In at least one embodiment, one or more of the SoC(s) 704 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free one or more CPU(s) 706 from routine data management tasks.

[0124] In at least one embodiment, the SoC(s) 704 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS techniques for diversity and redundancy, providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 704 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 714, when combined with one or more CPU(s) 706, one or more GPU(s) 708, and one or more data memories 716, may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0125] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as the C programming language, to perform a wide variety of processing algorithms over a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet performance requirements of many computer vision applications, such as those related to, for example, execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0126] Embodiments described herein enable multiple neural networks to execute concurrently and / or sequentially and combine results to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on the DLA or discrete GPU (e.g., GPU(s) 720) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may further include a neural network capable of identifying, interpreting, and providing semantic understanding of the sign and passing that semantic understanding to path planning modules executing on the CPU complex.

[0127] In at least one embodiment, multiple neural networks may be executed simultaneously, such as during Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign consisting of "Warning: Flashing lights indicate icy conditions" along with an electrical light may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on the CPU complex) that, if flashing lights are detected, icy conditions exist.In at least one embodiment, a flashing light may be identified by running a third deployed neural network over multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be executed concurrently, such as within the DLA and / or on the GPU(s) 708.

[0128] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 700. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle when the owner approaches the driver's door and turn on the lights, and, in security mode, disable the vehicle when the owner exits the vehicle. In this way, the SoC(s) 704 provide security against theft and / or carjacking.

[0129] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 796 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 704 use CNNs to classify ambient and urban noise, as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative closing speed of the emergency vehicle (e.g., using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by the GNSS sensor(s) 758.In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in the United States, the CNN attempts to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine to slow the vehicle, pull over to the side of the road, park the vehicle, and / or idle the vehicle with assistance from the ultrasonic sensor(s) 762 until the emergency vehicle(s) pass by.

[0130] In at least one embodiment, the vehicle 700 may include CPU(s) 718 (e.g., discrete CPU(s) or dCPU(s)) that may be coupled to the SoC(s) 704 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 718 may include, for example, an x86 processor. The CPU(s) 718 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 704 and / or monitoring the status and integrity of the controller(s) 736 and / or an infotainment system on a chip ("infotainment SoC") 730.

[0131] In at least one embodiment, the vehicle 700 may include GPU(s) 720 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to the SoC(s) 704 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the GPU(s) 720 may provide additional artificial intelligence capabilities, such as by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of the vehicle 700.

[0132] In at least one embodiment, the vehicle 700 may further include a network interface 724, which may include, among other things, wireless antenna(s) 726 (e.g., one or more wireless antennas 726 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 724 may be used to enable wireless connectivity over the internet to the cloud (e.g., to a server and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct connection may be established between the vehicle 70 and another vehicle and / or an indirect connection may be established (e.g., via networks and over the internet).In at least one embodiment, direct connections may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide information to the vehicle 700 about vehicles in the vicinity of the vehicle 700 (e.g., vehicles in front of, beside, and / or behind the vehicle 700). In at least one embodiment, the above functionality may be part of a cooperative adaptive cruise control functionality of the vehicle 700.

[0133] In at least one embodiment, network interface 724 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 736 to communicate over wireless networks. In at least one embodiment, network interface 724 may include a radio frequency front-end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible manner. For example, frequency conversions could be performed by well-known processes and / or using superheterodyne processes. In at least one embodiment, the radio frequency front-end functionality may be provided by a separate chip.In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0134] In at least one embodiment, the vehicle 700 may further include data storage 728, which may include, but is not limited to, off-chip memory (e.g., off-SoC(s) 704). In at least one embodiment, the data storage(s) 728 may include, but are not limited to, one or more memory elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0135] In at least one embodiment, the vehicle 700 may further include one or more GNSS sensors 758 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, sensing, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 758 may be used, including, for example, and without limitation, a GPS using a USB connector with an Ethernet-to-serial bridge (e.g., RS-232).

[0136] In at least one embodiment, the vehicle 700 may further include one or more RADAR sensors 760. The RADAR sensor(s) 760 may be used by the vehicle 700 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. The RADAR sensor(s) 760 may use CAN and / or bus 702 (e.g., to transmit data generated by the RADAR sensor(s) 760 for control and to access object tracking data, with Ethernet being accessed to access raw data in some examples). In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, the RADAR sensor(s) 760 may be suitable for front, rear, and side RADAR use.In at least one embodiment, one or more of the RADAR sensors 760 are one or more Pulse Doppler RADAR sensors.

[0137] In at least one embodiment, the RADAR sensor(s) 760 may include various configurations, such as long-range narrow field of view, short-range wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a wide field of view realized by two or more independent scans, such as within a 250 m range. In at least one embodiment, the RADAR sensor(s) 760 may help distinguish between static and moving objects and may be used by the ADAS system 738 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 760 included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surroundings of the vehicle 700 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, other two antennas may expand the field of view, making it possible to quickly detect vehicles entering or exiting the lane of the vehicle 700.

[0138] In at least one embodiment, medium-range RADAR systems may include, for example, a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensors 760 configured to be installed at either end of the rear bumper. When installed at either end of the rear bumper, in at least one embodiment, a RADAR sensor system may generate two beams that continuously monitor the blind spot behind and to the side of the vehicle. In at least one embodiment, short-range RADAR systems may be used in the ADAS system 738 for blind spot detection and / or lane change assistance.

[0139] In at least one embodiment, the vehicle 700 may further include one or more ultrasonic sensors 762. In at least one embodiment, the ultrasonic sensor(s) 762, which may be positioned at the front, rear, and / or sides of the vehicle 700, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensors 762 may be used, and different ultrasonic sensors 762 may be used for different sensing ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 762 may operate at functional safety levels of ASIL B.

[0140] In at least one embodiment, the vehicle 700 may include one or more LIDAR sensors 764. The LIDAR sensor(s) 764 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 764 may be at the ASIL B functional safety level. In at least one embodiment, the vehicle 700 may include multiple LIDAR sensors 764 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0141] In at least one embodiment, the LIDAR sensor(s) 764 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 764 may have an advertised range of approximately 100 m with an accuracy of 2 cm-3 cm and with support for a 100 Mbps Ethernet connection. In at least one embodiment, the LIDAR sensor(s) 764 may have an advertised range of approximately 100 m. In at least one embodiment, the LIDAR sensor(s) 764 may have one or more non-standard LIDAR sensors 764 may be used. In such an embodiment, the LIDAR sensor(s) 764 may be implemented as a small device that may be embedded in the front, rear, sides, and / or corners of the vehicle 700.In at least one embodiment, the LIDAR sensor(s) 764 in such an embodiment can provide up to a 120-degree horizontal field of view and a 35-degree vertical field of view with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor(s) 764 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0142] In at least one embodiment, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a flash of a laser as a transmission source to illuminate the surroundings of the vehicle 700 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receiver that records the laser pulse travel time and reflected light at each pixel, which in turn corresponds to the range of the vehicle 700 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be employed, one on each side of the vehicle 700. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g.,a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a 5-nanosecond Class I (eye-safe) laser pulse per frame and may collect reflected laser light in the form of 3D range point clouds and co-registered intensity data. In at least one embodiment, the flash LIDAR device may use a 5-nanosecond Class I (eye-safe) laser pulse per frame and may collect reflected laser light in the form of 3D range point clouds and .

[0143] In at least one embodiment, the vehicle may further include one or more IMU sensors 766. In at least one embodiment, the IMU sensor(s) 766 may be located at a center of the rear axle of the vehicle 700. In at least one embodiment, the IMU sensor(s) 766 may include, for example, and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass(es), and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 766 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 766 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0144] In at least one embodiment, the IMU sensor(s) 766 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 766 may enable the vehicle 700 to estimate heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from the GPS to the IMU sensor(s) 766. In at least one embodiment, the IMU sensor(s) 766 and the GNSS sensor(s) 758 may be combined into a single integrated unit.

[0145] In at least one embodiment, the vehicle 700 may include one or more microphones 796 placed in and / or around the vehicle 700. In at least one embodiment, the microphone(s) 796 may be used for, among other things, emergency vehicle detection and identification.

[0146] In at least one embodiment, vehicle 700 may further include any number of camera types, including stereo camera(s) 768, wide-view camera(s) 770, infrared camera(s) 772, surround camera(s) 774, long-range camera(s) 798, medium-range camera(s) 776, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 700. In at least one embodiment, the camera types used depend on the vehicle 700. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 700. In at least one embodiment, the number of cameras may vary depending on the embodiment.For example, in at least one embodiment, vehicle 700 could include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, each of the camera(s) is previously described with respect to [ ]. Fig. 7A and Fig. 7B is described in more detail.

[0147] In at least one embodiment, the vehicle 700 may further include one or more vibration sensors 742. In at least one embodiment, the vibration sensor(s) 742 may measure vibrations of components of the vehicle 700, such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 742 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a power-driven axle and a free-spinning axle).

[0148] In at least one embodiment, vehicle 700 may include ADAS system 738. ADAS system 738 may, in some examples, include, among other things, an SoC. In at least one embodiment, ADAS system 738 may include, among other things, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward collision warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic alert (“RCTW*”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0149] In at least one embodiment, the ACC system may use one or more RADAR sensors 760, one or more LIDAR sensors 764, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately in front of the vehicle 700 and automatically adjusts the speed of the vehicle 700 to maintain a safe distance from the vehicles in front of the vehicle. In at least one embodiment, the lateral ACC system performs follow-through and notifies the vehicle 700 to change lanes if necessary. In at least one embodiment, lateral ACC relates to other ADAS applications, such as LC and CW.

[0150] In at least one embodiment, the CACC system utilizes information from other vehicles that may be received via the network interface 724 and / or one or more wireless antenna(s) 726 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided through a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided through an infrastructure-to-vehicle ("I2V") communication link. In general, the V2V communication concept provides information about immediately preceding vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 700), while the I2V communication concept provides information about traffic further ahead of the vehicle.In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, the CACC system may be more reliable given information from vehicles ahead of vehicle 700 and has the potential to improve traffic flow smoothness and reduce congestion on a road.

[0151] In at least one embodiment, the FCW system is configured to warn the driver of a hazard so the driver can take corrective action. In at least one embodiment, the FCW system utilizes a forward-facing camera and / or radar sensor(s) 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide a warning, such as a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0152] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and may automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may utilize forward-facing camera(s) and / or radar sensor(s) 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first alerts the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply braking to prevent or at least mitigate the impact of a predicted collision.In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or imminent collision braking.

[0153] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 700 crosses lane markings. In at least one embodiment, the LDW system is not activated if the driver indicates an intended lane departure by activating a turn signal. In at least one embodiment, the LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is / are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or braking to correct the vehicle 700 when the vehicle 700 begins to depart from the lane.

[0154] In at least one embodiment, the BSW system detects and warns the driver of vehicles in an automobile's blind spot. In at least one embodiment, the BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may utilize rear-facing camera(s) and / or RADAR sensor(s) 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0155] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside the range of the rear camera when the vehicle 700 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may utilize one or more rear-facing RADAR sensors 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0156] In at least one embodiment, conventional ADAS systems may be prone to false positives, which may be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether a safety condition actually exists and act accordingly. In at least one embodiment, even in the case of conflicting results, the vehicle 700 decides whether to honor the result from a primary computer or a secondary computer (e.g., the first controller 736 or the second controller 736). For example, in at least one embodiment, the ADAS system 738 may be a backup and / or secondary computer for providing perception information to a rationality module of a backup computer.In at least one embodiment, the rationality monitor of a backup computer may execute redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, outputs from the ADAS system 738 may be provided to a monitoring MCU. In at least one embodiment, if outputs from the primary computer and secondary computer conflict, the monitoring MCU determines how to reconcile the conflict to ensure safe operation.

[0157] In at least one embodiment, the primary computer may be configured to provide the monitoring MCU with a confidence score indicating the primary computer's confidence in the selected outcome. In at least one embodiment, if the confidence score exceeds a threshold, the monitoring MCU may follow the primary computer's instruction regardless of whether the secondary computer provides a conflicting or inconsistent outcome. In at least one embodiment, if the confidence score does not meet the threshold and if the primary and secondary computers indicate different outcomes (e.g., a conflict), the monitoring MCU may arbitrate between computers to determine an appropriate outcome.

[0158] In at least one embodiment, the monitoring MCU may be configured to execute neural network(s) trained and configured to determine, based at least in part on outputs from the primary computer and secondary computer, conditions under which the secondary computer provides false alarms. In at least one embodiment, neural networks in the monitoring MCU may learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, neural network(s) in the monitoring MCU may learn when the FCW system identifies metallic objects that are not actually hazards, such as a drainage grate or manhole cover, that trigger an alarm.In at least one embodiment, when the secondary computer is a camera-based LDW system, a neural network in the monitoring MCU can learn to override LDW when cyclists or pedestrians are present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU can include at least one of a DLA or a GPU capable of executing neural network(s) with associated memory. In at least one embodiment, the monitoring MCU can comprise and / or be included as a component of SoC(s) 704.

[0159] In at least one embodiment, the ADAS system 738 may include a secondary computer that performs ADAS functionality using conventional computer vision rules. In at least one embodiment, the secondary computer may use classical computer vision (if-then) rules, and the presence of a neural network(s) in the monitoring MCU may improve reliability, safety, and performance. For example, in at least one embodiment, a diverse implementation and intentional non-identity makes the overall system more fault-tolerant, particularly against errors caused by software (or software-to-hardware interface) functionality.For example, in at least one embodiment, if there is a software bug or error in the software executing on the primary computer and non-identical software code executing on the secondary computer provides the same overall result, the monitoring MCU may have greater confidence that the overall result is correct and a bug in the software or hardware on the primary computer does not cause a significant error.

[0160] In at least one embodiment, the output of the ADAS system 738 may be fed into the perception block of the primary computer and / or the dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 738 displays a forward collision warning due to an object immediately ahead, the perception block may use this information in identifying objects. In at least one embodiment, the secondary computer may have its own neural network trained, thus reducing the risk of false positives, as described herein.

[0161] In at least one embodiment, the vehicle 700 may further include an infotainment SoC 730 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, in at least one embodiment, the infotainment system 730 may not be an SoC and may include, among other things, two or more discrete components. In at least one embodiment, the infotainment SoC 730 may include, among other things, a combination of hardware and software that may be used to provide the vehicle 700 with audio (e.g., music, a personal digital assistant, navigation directions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g.,Navigation systems, backup assist, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door opening / closing information, air filter information, etc.). For example, the infotainment SoC 730 could include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car putters, in-vehicle entertainment, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 734, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 730 may be further used to provide information (e.g.,visual and / or audible), such as information from the ADAS system 738, autonomous driving information such as planned vehicle maneuvers, trajectories, information about the surrounding environment (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0162] In at least one embodiment, the infotainment SoC 730 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 730 may communicate with other devices, systems, and / or components of the vehicle 700 via the bus 702 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 730 may be coupled to a supervisory MCU so that the infotainment system's GPU can perform some self-driving functions in the event that the primary controller(s) 736 (e.g., primary and / or backup computer of the vehicle 700) fail. In at least one embodiment, the infotainment SoC 730 may place the vehicle 700 into a chauffeur-in-safe-stop mode, as described herein.

[0163] In at least one embodiment, the vehicle 700 may further include an instrument cluster 732 (e.g., a digital instrument panel, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 732 may include, among other things, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 732 may include, among other things, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, gear shift position indicators, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between the infotainment SoC 730 and the instrument cluster 732. In at least one embodiment, the instrument cluster 732 may be included as part of the infotainment SoC 730, or vice versa.

[0164] In at least one embodiment, at least one component related to Fig. 7C is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, signals from the vehicle 700 for its autonomous operation and / or may be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, techniques and / or functions associated with Fig. 1-5, perform one or more operations (e.g., predicting the BLER using the CQI from the vehicle 700 and / or scheduling packets) related to the transmission of information (e.g., transmitted in URLLC packets) to the vehicle 700. In at least one embodiment, the vehicle 700 is to perform techniques and / or functions associated with one or more UEs (e.g., UE 106) in the set of UEs 104 of Fig. 1 are described.

[0165] Fig. 7D is a diagram of a system 777 for communication between one or more cloud-based servers and the autonomous vehicle 700 of Fig. 7A according to at least one embodiment. In at least one embodiment, system 777 may include, without limitation, server(s) 778, network(s) 790, and any number and type of vehicles, including vehicle 700. Server(s) 778 may include, without limitation, a plurality of GPUs 784(A)-784(H) (collectively referred to herein as GPUs 784), PCIe switches 782(A)-782(H) (collectively referred to herein as PCIe switches 782), and / or CPUs 780(A)-780(B) (collectively referred to herein as CPUs 780). The GPUs 784, CPUs 780, and PCIe switches 782 may be interconnected using high-speed interconnects, such as, without limitation, NVLink interfaces 788 developed through NVIDIA and / or PCIe interconnects 786. In at least one embodiment, the GPUs 784 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 784 and PCIe switches 782 are connected via PCIe interconnects.Although eight GPUs 784, two CPUs 780, and four PCIe switches 782 are illustrated in at least one embodiment, this is not intended to be limiting. In at least one embodiment, each of the servers 778 may include, without limitation, any number of GPUs 784, CPUs 780, and / or PCIe switches 782 in any combination. For example, in at least one embodiment, the server(s) 778 may each include eight, sixteen, thirty-two, and / or more GPUs 784.

[0166] In at least one embodiment, the server(s) 778 may receive, via a network(s) 790 and from vehicles, image data representing images depicting unexpected or changed road conditions, such as recently commenced road construction. In at least one embodiment, the server(s) 778 may transmit, via a network(s) 790 and to vehicles, neural networks 792, updated neural networks 792, and / or map information 794, including, without limitation, information related to traffic and road conditions. In at least one embodiment, updates to the map information 794 may include, without limitation, updates to the HD map 722, such as information related to construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 792, updated neural networks 792, and / or map information 794 may result from new training and / or experience represented in data received from any number of vehicles in the area and / or may be based at least in part on training performed in a data center (e.g., using server 778 and / or other servers).

[0167] In at least one embodiment, the server(s) 778 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles and / or may be generated in a simulation (e.g., using a gaming machine). In at least one embodiment, any amount of training data is labeled (e.g., if the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g.,transmitted to vehicles via network(s) 790) and / or machine learning models may be used by server 778 to remotely monitor vehicles.

[0168] In at least one embodiment, the server(s) 778 may receive data from vehicles and apply the data to real-time neural networks for intelligent real-time inference. In at least one embodiment, the server(s) 778 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 784, such as a DGX and DGX Station machine developed by NVIDIA. However, in at least one embodiment, the server(s) 778 may include deep learning infrastructure using CPU-powered data centers.

[0169] In at least one embodiment, the deep learning infrastructure of server(s) 778 may be capable of fast, real-time inference and may use this capability to evaluate and verify the integrity of processors, software, and / or associated hardware in vehicle 700. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 700, such as a sequence of images and / or objects that vehicle 700 has been located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by the vehicle 700, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 700 is malfunctioning, then the server(s) 778 may send a signal to the vehicle 700 instructing a fail-safe computer of the vehicle 700 to take control, notify passengers, and complete a safe parking maneuver.

[0170] In at least one embodiment, the server(s) 778 may include GPU(s) 784 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, such as when performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inference. COMPUTER SYSTEMS

[0171] Fig. 8 is a block diagram illustrating an example computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof 800, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, computer system 800 may include, without limitation, a component, such as a processor 802, for employing execution units that include logic for performing algorithms on process data, according to the present disclosure, such as in the embodiment described herein.In at least one embodiment, computer system 800 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 800 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, California, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0172] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of performing one or more instructions according to at least one embodiment.

[0173] In at least one embodiment, computer system 800 may include, without limitation, a processor 802, which may include, without limitation, one or more execution units 808 to perform machine learning model training and / or inference according to techniques described herein. In at least one embodiment, system 800 is a single-processor desktop or server system, but in another embodiment, system 800 may be a multiprocessor system. In at least one embodiment, processor 802 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computer ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor.In at least one embodiment, the processor 802 may be coupled to a processor bus 810 that may transmit data signals between the processor 802 and other components in the computer system 800.

[0174] In at least one embodiment, processor 802 may include, without limitation, an internal level 1 ("L1") cache 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache may be external to processor 802. Other embodiments may also include a combination of both internal and external caches depending on a particular implementation and requirements. In at least one embodiment, register file 806 may store various types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0175] In at least one embodiment, execution unit 808, including without limitation logic for performing integer and floating-point operations, is also located in processor 802. In at least one embodiment, processor 802 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 808 may include logic to handle a packed instruction set 809. In at least one embodiment, by including packed instruction set 809 in the instruction set of a general-purpose processor 802, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in a general-purpose processor 802.In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of a processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data item at a time.

[0176] In at least one embodiment, execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 may include, among other things, a memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 820 may store instruction(s) 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0177] In at least one embodiment, the system logic chip may be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip may include, among other things, a memory control node ("MCH") 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 816 may route data signals between the processor 802, the memory 820, and other components in the computer system 800, and may bridge data signals between the processor bus 810, the memory 820, and a system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller.In at least one embodiment, the MCH 816 may be coupled to the memory 820 through a high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 through an accelerated graphics port ("AGP") connection 814.

[0178] In at least one embodiment, computer system 800 may use system I / O 822, which is a proprietary node interface bus, to couple MCH 816 to I / O control node ("ICH") 830. In at least one embodiment, ICH 830 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 820, chipset, and processor 802. Examples may include, without limitation, an audio controller 829, a firmware node (“Flash BIOS”) 828, a wireless transceiver 826, a data store 824, a legacy I / O controller 823 containing user input and keyboard interfaces, a serial expansion port 827, such as a Universal Serial Bus (“USB”), and a network controller 834.In at least one embodiment, data storage 824 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0179] In at least one embodiment, Fig. 8 a system containing interconnected hardware devices or ‘chips’, whereas Fig. 8 may, in other embodiments, illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, Fig. The devices illustrated in Figure 8 may be connected using proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using Compute Express Link (CXL) connections.

[0180] In at least one embodiment, at least one component related to Fig. 8 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 8, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, the processor 802 and / or the graphics card 812 are used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, the processor 802 and / or the graphics card 812 perform at least one aspect that is related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0181] Fig. 9 is a block diagram illustrating an electronic device 900 for using a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example and without limitation, a notebook, a master server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0182] In at least one embodiment, system 900 may include, without limitation, processor 910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as a 1°C bus, a system management bus ("SM bus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-resolution audio ("HDA") bus, a serial advanced technology port ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9 a system containing interconnected hardware devices or ‘chips’, whereas Fig. 9 may, in other embodiments, illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, Fig. 9 may be connected to proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 9 using CXL connections (CXL = Compute Express Link).

[0183] In at least one embodiment, Fig. 9 a display 924, a touchscreen 925, a touchpad 930, a near field communication unit (“NFC”) 945, a sensor node 940, a thermal sensor 939, an express chipset (“EC”) 935, a trusted platform module (“TPM”) 938, BIOS / firmware / flash memory (“BIOS, FW Flash”) 922, a DSP 960, a drive (“SSD or HDD”) 920, such as a solid state disk (“SSD”) or a hard disk drive (“HDD”), a wireless local area network unit (“WLAN”) 950, a Bluetooth unit 952, a wireless wide area network unit (“WWAN”) 956, a global positioning system (GPS) 955, a camera (“USB 3.0 camera”) 954, such as a USB 3.0 camera, or a storage unit with Low Double Data Rate ("LPDDR") 915 ("LPDDR3"), implemented, for example, in the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0184] In at least one embodiment, other components may be communicatively coupled to processor 910 through components discussed above. In at least one embodiment, an accelerometer 941, an ambient light sensor ("ALS") 942, a compass 943, and a gyroscope 944 may be communicatively coupled to sensor node 940. In at least one embodiment, thermal sensor 939, a fan 937, a keyboard 936, and a touchpad 930 may be communicatively coupled to EC 935. In at least one embodiment, speaker 963, headphones 964, and a microphone ("mic") 965 may be communicatively coupled to an audio unit ("audio codec and class-D amplifier") 964, which in turn may be communicatively coupled to DSP 960. In at least one embodiment, the audio unit 964 may include, for example and without limitation, an audio encoder / decoder (“codec”) and a Class D amplifier.In at least one embodiment, the SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952, as well as the WWAN unit 956, may be implemented in a next-generation form factor ("NGFF").

[0185] In at least one embodiment, at least one component related to Fig. 9 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 9, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, the processor 910 is used to perform a selection of packet MCS information 140, an identification of RB information 144, a generation of transmission priority metrics 148, a generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, the processor 910 performs at least one aspect that is related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0186] Fig. Figure 10 illustrates a computer system 1000 according to at least one embodiment. In at least one embodiment, the computer system 1000 is configured to implement various processes and methods described in this disclosure.

[0187] In at least one embodiment, computer system 1000 includes, without limitation, at least one central processing unit ("CPU") 1002 connected to a communications bus 1010 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), PCI-Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communications protocol(s). In at least one embodiment, computer system 1000 includes, without limitation, main memory 1004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1004, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem (“Network Interface”) 1022 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems from computer system 1000.

[0188] In at least one embodiment, computer system 1000 includes, without limitation, input devices 1008, parallel processing system 1012, and display devices 1006, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light-emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input devices 1008, such as a keyboard, mouse, touchpad, microphone, and more. In at least one embodiment, each of the foregoing modules may be arranged on a single semiconductor platform to form a processing system.

[0189] In at least one embodiment, at least one component related to Fig. 10 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 10, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one of parallel processing system 1012 and CPU 1002 are used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one of parallel processing system 1012 and CPU 1002 performs at least one aspect related to processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB identifier 142, and / or packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0190] Fig. 11 illustrates a computer system 1100 according to at least one embodiment. In at least one embodiment, the computer system 1100 includes, among other things, a computer 1110 and a USB flash drive 1120. In at least one embodiment, the computer 1110 may include, among other things, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1110 includes, among other things, a server, a cloud instance, a laptop, and a desktop computer.

[0191] In at least one embodiment, USB flash drive 1120 includes, among other things, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, processing unit 1130 may be any instruction execution system, instruction execution apparatus, or instruction execution device capable of executing instructions. In at least one embodiment, processing unit 1130 may include, among other things, any number and type of processing cores (not shown). In at least one embodiment, processing core 1130 comprises an application-specific integrated circuit ("ASIC") optimized to perform any set and type of operations associated with machine learning.For example, in at least one embodiment, processing core 1130 is a tensor processing unit ("TPC") optimized to perform inference operations for machine learning. In at least one embodiment, processing core 1130 is a vision processing unit ("VPU") optimized to perform inference operations for machine vision and machine learning.

[0192] In at least one embodiment, USB interface 1140 may be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1150 may include any amount and type of logic that enables processing unit 1130 to connect to devices (e.g., computer 1110) via USB connector 1140.

[0193] In at least one embodiment, at least one component related to Fig. 11 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 11, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, computer 1110 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, computer 1110 performs at least one aspect related to processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB identifier 142, and / or packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0194] Fig. 12A illustrates an example architecture in which a plurality of GPUs 1210-1213 are communicatively coupled to a plurality of multi-core processors 1205-1206 via high-speed interconnects 1240-1243 (e.g., buses, point-to-point links, etc.). In one embodiment, high-speed interconnects 1240-1243 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0195] Additionally, and in one embodiment, two or more of the GPUs 1210-1213 are interconnected via high-speed interconnects 1229-1230, which may be implemented using the same or different protocols / connections than those used for high-speed interconnects 1240-1243. Likewise, two or more of the multi-core processors 1205-1206 may be interconnected via the high-speed interconnect 1228, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between different Fig. 12A using the same protocols / connections (e.g., via a common interconnection structure).

[0196] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to a processor memory 1201-1202 via memory interconnects 1226-1227, respectively, and each GPU 1210-1213 is communicatively coupled to GPU memory 1220-1223 via GPU memory interconnects 1250-1253, respectively. Memory interconnects 1226-1227 and 1250-1253 may use the same or different memory access technologies. For example, and not by way of limitation, the processor memories 1201-1202 and the GPU memories 1220-1223 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memories (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-RAM. In one embodiment, a portion of the processor memories 1201-1202 may be volatile memory, and another portion may be non-volatile memory (e.g.,using a two-level memory (2LM) hierarchy).

[0197] As described herein, although different processors 1205-1206 and GPUs 1210-1213 may each be physically coupled to a particular memory 1201-1202, 1220-1223, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as "effective address space") is distributed across different physical memories. For example, processor memories 1201-1202 may each comprise 64 GB of system memory address space, and GPU memories 1220-1223 may each comprise 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0198] Fig. 12B illustrates additional details for a connection between a multi-core processor 1207 and a graphics acceleration module 1246 according to an example embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card coupled to the processor 1207 via the high-speed interconnect 1240. Alternatively, the graphics acceleration module 1246 may be integrated on the same package or chip as the processor 1207.

[0199] In at least one embodiment, the illustrated processor 1207 includes a plurality of cores 1260A-1260D, each with a translation buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, the cores 1260A-1260D may include various other components for executing instructions and processing data that are not illustrated. The caches 1262A-1262D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1256 may be included in the caches 1262A-1262D and shared by sets of cores 1260A-1260D. For example, one embodiment of processor 1207 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores.The processor 1207 and the graphics acceleration module 1246 are connected to the system memory 1214, which includes the processor memories 1201-1202. Fig. 12A may include.

[0200] Coherency is maintained for data and instructions stored in various caches 1262A-1262D, 1256, and system memory 1214 via intercore communication over a coherency bus 1264. For example, each cache may have cache coherency logic / circuitry associated with it to communicate over the coherency bus 1264 in response to detected reads or writes to specific cache lines. In one implementation, a cache sniffing protocol is implemented over the coherency bus 1264 to sniff cache accesses.

[0201] In one embodiment, a proxy circuit 1225 communicatively couples the graphics acceleration module 1246 to the coherence bus 1264, enabling the graphics acceleration module 1246 to participate in a cache coherence protocol as a peer of the cores 1260A-1260D. An interface 1235 provides connectivity to the proxy circuit 1225 via the high-speed interconnect 1240 (e.g., a PCIe bus, NVLink, etc.), and an interface 1237 connects the graphics acceleration module 1246 to the interconnect 1240.

[0202] In one implementation, an accelerator integration circuit 1236 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1231, 1232, N of the graphics acceleration module 1246. The graphics processing engines 1231, 1232, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, N may comprise various types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines.In at least one embodiment, the graphics acceleration module 1246 may be a GPU having a plurality of graphics processing engines 1231-1232, N, or the graphics processing engines 1231-1232, N may be individual GPUs integrated on a common package, line card, or chip.

[0203] In one embodiment, accelerator integration circuitry 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1214. MMU 1239 may also include a translation buffer (TLB) (not shown) for caching virtual / effective to physical / real translations. In one embodiment, data stored in cache 1238 and graphics memories 1233-1234, M is maintained coherent with core caches 1262A-1262D, 1262B, and system memory 1214. As mentioned, this can be achieved via the proxy circuit 1225 for the cache 1238 and the memories 1233-1234, M (e.g.Sending updates to cache 1238 regarding modifications / accesses to cache lines on processor caches 1262A-1262D, 1256 and receiving updates from cache 1238).

[0204] A set of registers 1245 stores context data for threads executed by the graphics processing engines 1231-1232, N, and a context management circuit 1248 manages thread contexts. For example, the context management circuit 1248 may perform save and restore operations to save and restore contexts of different threads during context switches (e.g., saving a first thread and saving a second thread so that a second thread can be executed by a graphics processing engine). For example, upon a context switch, the context management circuit 1248 may save current register values ​​to a designated region in memory (e.g., identified by a context pointer). It may then restore register values ​​when returning to a context.In one embodiment, an interrupt management circuit 1247 receives and processes interrupts received from system devices.

[0205] In one implementation, virtual / effective addresses from a graphics processing engine 1231 are translated by the MMU 1239 into real / physical addresses in system memory 1214. One embodiment of the accelerator integration circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. The graphics accelerator module 1246 may be dedicated to a single application executing on the processor 1207 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is illustrated in which resources of the graphics processing engines 1231-1232, N are shared among multiple applications or virtual machines (VMs).In at least one embodiment, resources may be divided into "slices" that are assigned to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0206] In at least one embodiment, accelerator integration circuitry 1236 operates as a bridge to a system for graphics acceleration module 1246, providing address translation and system memory caching services. Additionally, accelerator integration circuitry 1236 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1231-1232, interrupts, and memory management.

[0207] Because hardware resources of graphics processing engines 1231-1232, N are explicitly mapped to a real address space seen by host processor 1207, each host processor can directly address these resources using an effective address value. One function of accelerator integration circuit 1236, in one embodiment, is to physically separate graphics processing engines 1231-1232, N so that they appear to a system as independent entities.

[0208] In at least one embodiment, one or more graphics memories 1233-1234, M are each coupled to each of the graphics processing engines 1231-1232, N. The graphics memories 1233-1234, M may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0209] In one embodiment, to reduce data traffic over interconnect 1240, biasing techniques are used to ensure that data stored in graphics memories 1233-1234, M is data most frequently used by graphics processing engines 1231-1232, N and preferably not used by cores 1260A-1260D (at least not frequently). Similarly, a biasing mechanism attempts to keep data needed by the cores (and preferably not by graphics processing engines 1231-1232, N) within the caches 1262A-1262D, 1256 of the cores and system memory 1214.

[0210] Fig. 12C illustrates another exemplary embodiment in which the accelerator integration circuit 1236 is integrated within the processor 1207. In this embodiment, the graphics processing engines 1231-1232, N communicate directly over the high-speed interconnect 1240 with the accelerator integration circuit 1236 via the interface 1237 and the interface 1235 (which may again use any form of bus or interface protocol). The accelerator integration circuit 1236 may perform the same operations as those described with respect to Fig. 12B, but possibly with higher throughput given their close proximity to the coherence bus 1264 and the caches 1262A-1262D, 1256. One embodiment supports different programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1236 and programming models controlled by the graphics acceleration module 1246.

[0211] In at least one embodiment, the graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to the graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0212] In at least one embodiment, the graphics processing engines 1231-1232,N may be shared between multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize the graphics processing engines 1231-1232,N to allow access by any operating system. For single-partition systems without a hypervisor, the graphics processing engines 1231-1232,N are owned by an operating system. In at least one embodiment, an operating system may virtualize the graphics processing engines 1231-1232,N to provide access to any process or application.

[0213] In at least one embodiment, the graphics acceleration module 1246 or an individual graphics processing engine 1231-1232,N selects a process element using a process handle. In one embodiment, process elements are stored in system memory 1214 and are addressable from an effective address to a real address using translation techniques described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when its context is registered with the graphics processing engine 1231-1232,N (that is, system software is invoked to add a process element to a linked list of process elements). In at least one embodiment, a lower 16-bit of a process handle may be an offset of the process element within a linked list of process elements.

[0214] Fig. 12D illustrates an exemplary accelerator integration slice 1290. As used herein, a "slice" comprises a specified portion of processing resources of accelerator integration circuitry 1236. The application's effective address space 1282 within system memory 1214 stores process elements 1283. In one embodiment, process elements 1283 are stored in response to GPU calls 1281 from applications 1280 executing on processor 1207. A process element 1283 contains process state for the corresponding application 1280. A work descriptor (WD) 1284 contained within the process element 1283 may be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 1284 is a pointer to a job request queue in the address space 1282 of an application.

[0215] The graphics acceleration module 1246 and / or individual graphics processing engines 1231-1232, N may be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing a process state and sending a WD 1284 to a graphics acceleration module 1246 to start a job in a virtualized environment may be included.

[0216] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1246 or a single graphics processing engine 1231. Because the graphics acceleration module 1246 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1236 for an ownership partition, and an operating system initializes the accelerator integration circuit 1236 for an ownership process when the graphics acceleration module 1246 is assigned.

[0217] In operation, a WD fetch unit 1291 in the accelerator integration slice 1290 fetches the next WD 1284, which includes an indication of the work to be performed by one or more graphics processing engines of the graphics acceleration module 1246. Data from the WD 1284 may be stored in registers 1245 and used by the MMU 1239, the interrupt management circuitry 1247, and / or the context management circuitry 1248, as illustrated. For example, one embodiment of the MMU 1239 includes segment / page browsing circuitry for accessing segment / page tables 1286 within the OS virtual address space 1285. The interrupt management circuitry 1247 may process interrupt events 1292 received from the graphics acceleration module 1246.When performing graphics operations, an effective address 1293 generated by a graphics processing engine 1231-1232, N is translated into a real address by the MMU 1239.

[0218] In one embodiment, a similar set of registers 1245 is duplicated for each graphics processing engine 1231-1232, N, and / or the graphics acceleration module 1246 and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in an accelerator integration slice 1290. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor-initialized registers 1 Scheibensteuerregister 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0219] Example registers that can be initialized by an operating system are shown in Table 2. Table 2 - Operating system initialized registers 1 Prozess- und Thread-Identifikation 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Arbeitsdeskriptor

[0220] In one embodiment, each WD 1284 is specific to a particular graphics acceleration module 1246 and / or graphics processing engines 1231-1232, N. It contains all the information required by a graphics processing engine 1231-1232, N to perform work, or it may be a pointer to a memory location where an application has established a command queue of work to be completed.

[0221] Fig. 12E illustrates additional details for an exemplary embodiment of a shared model. This embodiment includes a real hypervisor address space 1298 in which a process element list 1299 is stored. The real hypervisor address space 1298 is accessible via a hypervisor 1296 that virtualizes graphics acceleration engine engines for the operating system 1295.

[0222] In at least one embodiment, shared programming models enable all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1246. There are two programming models where the graphics acceleration module 1246 is shared among multiple processes and partitions: shared time slices and shared graphics control.

[0223] In this model, the system hypervisor 1296 owns the graphics acceleration module 1246 and exposes its functionality to all operating systems 1295. For a graphics acceleration module 1246 to support virtualization by the system hypervisor 1296, the graphics acceleration module 1246 may consider the following: 1) An application's job request must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 1246 must provide a context save and restore mechanism. 2) An application's job request is guaranteed by the graphics acceleration module 1246 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1246 provides the ability to preempt the processing of a job.3) The graphics acceleration module 1246 must guarantee fairness between processes when operating in a controlled shared programming model.

[0224] In at least one embodiment, the application 1280 must make a system call to the operating system 1295 with a graphics acceleration module 1246 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module 1246 type may be a system-specific value.In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1246 and may be in the form of a graphics acceleration module 1246 instruction, an effective address pointer to a user-defined structure, an effective address pointer to a queue of instructions, or any other data structure for describing work to be performed by the graphics acceleration module 1246. In one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR.If accelerator integration circuitry 1236 and graphics acceleration module 1246 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. Hypervisor 1296 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1283. In at least one embodiment, the CSRP is one of registers 1245 that contains an effective address of a region in an application's address space 1282 for graphics acceleration module 1246 to save and restore context state. This pointer is optional when no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be pinned system memory.

[0225] Upon receiving a system call, the operating system 1295 can verify that the application 1280 is registered and has been granted permission to use the graphics acceleration module 1246. The operating system 1295 then calls the hypervisor 1296 with the information shown in Table 3. Table 3 - OS-to-Hypervisor call parameters 1 Ein Arbeitsdeskriptor (WD) 2 Ein Authority Mask Register (AMR)-Wert (möglicherweise maskiert) 3 Ein Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 Eine Prozess-ID (PID) und optionale Thread-ID (TID) 5 Ein Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Eine Logical Interrupt Service Number (LISN)

[0226] Upon receiving a hypervisor call, the hypervisor 1296 verifies that the operating system 1295 is registered and has been granted permission to use the graphics acceleration module 1246. The hypervisor 1296 then places the process element 1283 in a linked list of process elements for a corresponding graphics acceleration module 1246 type. A process element may include information shown in Table 4. Table 4 - Process element information 1 Ein Arbeitsdeskriptor (WD) 2 Ein Authority Mask Register (AMR)-Wert (möglicherweise maskiert). 3 Ein Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 Eine Prozess-ID (PID) und optionale Thread-ID (TID) 5 Ein Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Eine Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table, abgeleitet von Hypervisor-Aufrufparametern 9 Ein Status Register (SR) Wert 10 Eine Logical Partition ID (LPID) 11 Ein Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0227] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1290 registers 1245.

[0228] As in Fig. 12F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations performed on GPUs 1210-1213 use the same virtual / effective memory address space to access processor memories 1201-1202 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1201, a second portion is assigned to second processor memory 1202, a third portion is assigned to GPU memory 1220, and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1201-1202 and GPU memories 1220-1223, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0229] In one embodiment, bias / coherence management circuitry 1294A-1294E within one or more of the MMUs 1239A-1239E ensures cache coherence between caches of one or more host processors (e.g., 1205) and GPUs 1210-1213 and implements bias techniques that indicate physical memories in which certain types of data should be stored. While multiple instances of bias / coherence management circuitry 1294A-1294E in Fig. 12F, the bias / coherence circuit may be implemented within an MMU of one or more host processors 1205 and / or within the accelerator integration circuit 1236.

[0230] One embodiment enables GPU-bound memory 1220-1223 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without incurring performance penalties associated with full system cache coherence. In at least one embodiment, a capability for GPU-bound memory 1220-1223 to be accessed as system memory without costly cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement enables host processor 1205 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU-bound memory 1220-1223 without cache coherence overheads may be critical to the execution time of an offloaded computation. For example, in cases with significant streaming write memory traffic, the cache coherence overhead may significantly reduce the effective write bandwidth seen by a GPU 1210-1213. In at least one embodiment, operand facility efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of GPU offloading.

[0231] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure (i.e., controlled to a memory page granularity) including 1 or 2 bits per GPU-bound memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU-bound memories 1220-1223 with or without a bias cache in the GPU 1210-1213 (e.g., to cache frequently / recently used bias table entries). Alternatively, an entire bias table may be maintained within a GPU.

[0232] In at least one embodiment, a bias table entry associated with each access to GPU-bound memory 1220-1223 is accessed prior to the actual access to a GPU memory, causing the following operations. First, local requests from GPU 1210-1213 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1220-1223. Local requests from a GPU that find their page in the host bias are forwarded to processor 1205 (e.g., over a high-speed interconnect, as discussed above). In one embodiment, requests from processor 1205 that find a requested page in the host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU 1210-1213.In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, the bias state of a page may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0233] A mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn invokes a GPU device driver, which in turn sends a message to a GPU (or queues a command descriptor) instructing it to change a bias state and, for some transitions, performs a cache flush operation in a host. In at least one embodiment, the cache flush operation is used for a transition from the host processor 1205 bias to the GPU bias, but is not used for an opposite transition.

[0234] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 1205. To access these pages, processor 1205 may request access from GPU 1210, which may or may not grant access immediately. Thus, to reduce communication between processor 1205 and GPU 1210, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by the host processor 1205, and vice versa.

[0235] In at least one embodiment, at least one component that is related to one or more of Fig. 12A-F is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 12A-F, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, identify and / or select MCS and / or a number of RBs, generate transmission priority metrics, or otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one GPU and / or multi-core processor described with respect to Fig. 12A-F, is used to perform a selection of packet MCS information 140, an identification of RB information 144, a generation of transmission priority metrics 148, a generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one GPU and / or multi-core processor, which is shown or described with respect to Fig. 12A-F, at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142 and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0236] Fig. Figure 13 illustrates example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0237] Fig. 13 is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 1300 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic, including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I.sup.2S / I.sup.2C controller 1340.In at least one embodiment, integrated circuit 1300 may include a display device 1345 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1350 and a mobile industry processor interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1370.

[0238] In at least one embodiment, at least one component related to Fig. 13 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 13, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, the graphics processor 1310 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, the graphics processor 1310 performs at least one aspect that is related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0239] Fig. 14A-14B illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0240] Fig. 14A-14B are block diagrams illustrating example graphics processors for use within an SoC according to embodiments described herein. Fig. 14A illustrates an exemplary graphics processor 1410 of an integrated system-on-a-chip circuit that may be fabricated using one or more IP cores, according to at least one embodiment. Fig. 14B illustrates an additional exemplary graphics processor 1440 of a system-on-a-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1410 is Fig. 14A is a low-performance graphics processor core. In at least one embodiment, the graphics processor 1440 is Fig. 14B, a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1410, 1440 may be variants of the graphics processor 1310 of Fig. be 13.

[0241] In at least one embodiment, graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D through 1415N-1, and 1415N). In at least one embodiment, graphics processor 1410 may execute different shader programs via separate logic, such that vertex processor 1405 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1405 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1415A-1415N use primitive and vertex data generated by the vertex processor 1405 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1415A-1415N are optimized to execute fragment shader programs, such as those provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program, such as those provided in a Direct 3D API.

[0242] In at least one embodiment, graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, cache(s) 1425A-1425B, and circuit interconnect(s) 1430A-1430B. In at least one embodiment, one or more MMU(s) 1420A-1420B provide a virtual-to-physical mapping for graphics processor 1410, including vertex processor 1405 and / or fragment processor(s) 1415A-1415N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more cache(s) 1425A-1425B. In at least one embodiment, one or more MMU(s) 1420A-1420B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1305, image processors 1315, and / or video processors 1320 of Fig. 13, so that each processor 1305-1320 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0243] In at least one embodiment, the graphics processor 1440 includes one or more MMU(s) 1420A-1420B, caches 1425A-1425B, and circuit interconnects 1430A-1430B of the graphics processor 1410 of Fig. 14A. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F through 1455N-1, and 1455N), providing a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or computational shaders. In at least one embodiment, the number of shader cores may vary.In at least one embodiment, the graphics processor 1440 includes an intercore task manager 1445 acting as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N, and a tiling unit 1458 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are partitioned into image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0244] In at least one embodiment, at least one component related to Fig. 14A and Fig. 14B is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 14A and / or Fig. 14B, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, identify and / or select MCS and / or a number of RBs, generate transmission priority metrics, or otherwise perform operations associated with Fig. 1-5. In at least one embodiment, the graphics processor 1410 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, the graphics processor 1410 performs at least one aspect that is related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0245] Fig. 15A-15B illustrate additional example graphics processor logic according to embodiments described herein. Fig. 15A illustrates a graphics core 1500 included in at least one embodiment in the graphics processor 1310 of Fig. 13 and in at least one embodiment, a unified shader core 1455A -1455N as in Fig. 14B can be. Fig. 15B illustrates a highly parallel, general-purpose graphics processing unit 1530 suitable for use on a multi-chip module in at least one embodiment.

[0246] In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, a texture unit 1518, and a cache / shared memory 1520, which are execution resources shared within graphics core 1500. In at least one embodiment, graphics core 1500 may include multiple slices 1501A-1501N, or a partition for each core, and a graphics processor may include multiple instances of graphics core 1500. Slices 1501A-1501N may include support logic including a local instruction cache 1504A-1504N, a thread scheduler 1506A-1506N, a thread dispatcher 1508A-1508N, and a set of registers 1510A-1510N.In at least one embodiment, the slices 1501A-1501N may include a set of additional functional units (AFUs 1512A-1512N), floating point units (FPU 1514A-1514N), integer arithmetic logic units (ALUs 1516-1516N), address calculation units (ACU 1513A-1513N), double precision floating point units (DPFPU 1515A-1515N), and matrix processing units (MPU 1517A-1517N).

[0247] In at least one embodiment, the FPUs 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1515A-1515N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1516A-1516N can perform 8-bit, 16-bit, and 32-bit variable-precision integer operations and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations.In at least one embodiment, MPUs 1517-1517N may perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general purpose matrix-matrix multiplication (GEMM). In at least one embodiment, AFUs 1512A-1512N may perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0248] In at least one embodiment, at least one component related to Fig. 15A is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 15A, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, identify and / or select MCS and / or a number of RBs, generate transmission priority metrics, or otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one graphics processor 1500 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one graphics processor 1500 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0249] Fig. 15B illustrates a general-purpose processing unit (GPGPU) 1530 that may be configured to enable highly parallel computational operations performed, in at least one embodiment, by an array of graphics processing units. In at least one embodiment, the GPGPU 1530 may be directly linked to other instances of the GPGPU 1530 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1530 includes a host interface 1532 to enable connection to a host processor. In at least one embodiment, the host interface 1532 is a PCI Express interface. In at least one embodiment, the host interface 1532 may be a vendor-specific communication interface or communication fabric.In at least one embodiment, GPGPU 1530 receives instructions from a host processor and uses a global scheduler 1534 to dispatch execution threads associated with those instructions to a set of compute clusters 1536A-1536H. In at least one embodiment, compute clusters 1536A-1536H share a cache 1538. In at least one embodiment, cache 1538 may serve as a higher-level cache for caches within compute clusters 1536A-1536H.

[0250] In at least one embodiment, GPGPU 1530 includes memory 1544A-1544B coupled to compute clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memory 1544A-1544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR).

[0251] In at least one embodiment, the compute clusters 1536A-1536H each include a set of graphics cores, such as the graphics core 1500 of Fig. 15A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0252] In at least one embodiment, multiple instances of GPGPU 1530 may be configured to operate as a compute cluster. In at least one embodiment, the communication used by compute clusters 1536A-1536H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to a GPU interconnect 1540 that enables direct connection to other instances of GPGPU 1530. In at least one embodiment, GPU interconnect 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530.In at least one embodiment, GPU interconnect 1540 couples to a high-speed interconnect for transmitting and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 reside in separate computing systems and communicate via a network device accessible via host interface 1532. In at least one embodiment, GPU interconnect 1540 may be configured to enable connection to a host processor in addition to, or as an alternative to, host interface 1532.

[0253] In at least one embodiment, the GPGPU 1530 may be configured to train neural networks. In at least one embodiment, the GPGPU 1530 may be used within an inference platform. In at least one embodiment where the GPGPU 1530 is used for inference, the GPGPU may include fewer compute clusters 1536A-1536H compared to when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1544A-1544B may differ between inference and training configurations, with higher-bandwidth memory technologies dedicated to training configurations. In at least one embodiment, the inference configuration of the GPGPU 1530 may support the inference of specific instructions.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer product instructions that may be used during inference operations for deployed neural networks.

[0254] In at least one embodiment, at least one component related to Fig. 15B is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 15B, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, identify and / or select MCS and / or a number of RBs, generate transmission priority metrics, or otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one GPGPU 1530 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one GPGPU 1530 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0255] Fig. 16 is a block diagram illustrating a computer system 1600 according to at least one embodiment. In at least one embodiment, computer system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604 communicating via an interconnect that may include a storage node 1605. In at least one embodiment, storage node 1605 may be a separate component within a chipset component or may be integrated within one or more processors 1602. In at least one embodiment, storage node 1605 couples to an I / O subsystem 1611 via a communications link 1606. In at least one embodiment, I / O subsystem 1611 includes an I / O node 1607 that may enable computer system 1600 to receive input from one or more input devices 1608.In at least one embodiment, I / O node 1607 may enable a display controller, which may be included in one or more processors 1602, to provide outputs to one or more display devices 1610A. In at least one embodiment, one or more display devices 1610A coupled to I / O node 1607 may include a local, internal, or embedded display device.

[0256] In at least one embodiment, processing subsystem 1601 includes one or more parallel processors 1612 coupled to storage node 1605 via a bus or other communication link 1613. In at least one embodiment, communication link 1613 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1612 form a compute-focused parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as an integrated multi-core (MIC) processor.In at least one embodiment, one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one or more display devices 1610A coupled via I / O node 1607. In at least one embodiment, one or more parallel processors 1612 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0257] In at least one embodiment, a system storage unit 1614 may connect to the I / O node 1607 to provide a storage mechanism for the computing system 1600. In at least one embodiment, an I / O switch 1616 may be used to provide an interface mechanism to enable connections between the I / O node 1607 and other components, such as a network adapter 1618 and / or wireless network adapter 1619 that may be integrated into the platform, and various other devices that may be added via one or more add-on devices 1620. In at least one embodiment, the network adapter 1618 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 1619 may include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0258] In at least one embodiment, computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to I / O node 1607. In at least one embodiment, communication paths connecting various components in Fig. 16 interconnect, be implemented using any suitable protocols, such as PCI-based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect or link protocols.

[0259] In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory node 1605, processor(s) 1602, and I / O node 1607 may be integrated into a system-on-chip (SoC) integrated circuit.In at least one embodiment, components of computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 1600 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0260] In at least one embodiment, at least one component related to Fig. 16 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 16, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one of the processor 1602 and the parallel processor 1612 are used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one of the processor 1602 and the parallel processor 1612 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described. PROCESSORS

[0261] Fig. 17A illustrates a parallel processor 1700 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1700 is a variant of one or more in Fig. 16, according to an exemplary embodiment.

[0262] In at least one embodiment, parallel processor 1700 includes a parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 may connect directly to other devices. In at least one embodiment, I / O unit 1704 connects to other devices through the use of a node or switch interface, such as storage node 1705. In at least one embodiment, connections between storage node 1705 and I / O unit 1704 form a communication link.In at least one embodiment, the I / O unit 1704 connects to a host interface 1706 and a memory crossbar 1716, where the host interface 1706 receives commands directed to performing processing operations and the memory crossbar 1716 receives commands directed to performing memory operations.

[0263] In at least one embodiment, when the host interface 1706 receives a command buffer via the I / O unit 1704, the host interface 1706 may direct work operations to a front end 1708 to perform those commands. In at least one embodiment, the front end 1708 couples to a scheduler 1710 configured to dispatch commands or other work items to a processing cluster array 1712. In at least one embodiment, the scheduler 1710 ensures that the processing cluster array 1712 is properly configured and in a valid state before dispatching tasks to the processing cluster array 1712 of the processing cluster array 1712. In at least one embodiment, the scheduler 1710 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 1710 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 1712. In at least one embodiment, host software may allocate workloads for scheduling on the processing array 1712 via one of several graphics processing doorbells. In at least one embodiment, workloads may then be automatically distributed across the processing array 1712 by the logic of the scheduler 1710 within a microcontroller that includes the scheduler 1710.

[0264] In at least one embodiment, the processing cluster arrangement 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of the processing cluster arrangement 1712 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 may allocate work to the clusters 1714A-1714N of the processing cluster arrangement 1712 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1710 or may be partially assisted by compiler logic during compilation of the program logic configured for execution by the processing cluster arrangement 1712.In at least one embodiment, different clusters 1714A-1714N of the processing cluster arrangement 1712 may be assigned to process different types of programs or to perform different types of computations.

[0265] In at least one embodiment, processing cluster assembly 1712 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster assembly 1712 is configured to perform parallel, general-purpose computing operations. For example, in at least one embodiment, processing cluster assembly 1712 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0266] In at least one embodiment, processing cluster assembly 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster assembly 1712 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tiling logic and other vertex processing logic. In at least one embodiment, processing cluster assembly 1712 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tile shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1702 may transfer data from system memory via I / O unit 1704 for processing.In at least one embodiment, data transferred during processing may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory.

[0267] In at least one embodiment, when the parallel processing unit 1702 is used to perform graphics processing, the scheduler 1710 may be configured to divide a processing workload into approximately equally sized tasks to better facilitate the distribution of graphics processing operations across multiple clusters 1714A-1714N of the processing cluster assembly 1712. In at least one embodiment, portions of the processing cluster assembly 1712 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tile and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N may be stored in buffers to enable intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0268] In at least one embodiment, processing cluster arrangement 1712 may receive processing tasks to be executed via scheduler 1710, which receives commands defining processing tasks from frontend 1708. In at least one embodiment, processing tasks may include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how data is to be processed (e.g., which program is to be executed). In at least one embodiment, scheduler 1710 may be configured to retrieve indices corresponding to tasks or may receive indices from frontend 1708. In at least one embodiment, frontend 1708 may be configured to ensure that processing cluster arrangement 1712 is configured to a valid state before executing a workload defined by incoming command buffers (e.g.,stack buffer, push buffer, etc.) is specified.

[0269] In at least one embodiment, each of one or more instances of parallel processing unit 1702 may be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 may be accessed via memory crossbar 1716, which may receive memory requests from processing cluster array 1712 as well as I / O unit 1704. In at least one embodiment, memory crossbar 1716 may access parallel processor memory 1722 via a memory interface 1718. In at least one embodiment, memory interface 1718 may include a plurality of partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 1722.In at least one embodiment, a number of partition units 1720A-1720N is configured to equal a number of storage units, such that a first partition unit 1720A has a corresponding first storage unit 1724A, a second partition unit 1720B has a corresponding storage unit 1724B, and an Nth partition unit 1720N has a corresponding Nth storage unit 1724N. In at least one embodiment, a number of partition units 1720A-1720N may not equal a number of storage devices.

[0270] In at least one embodiment, the memory units 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR). In at least one embodiment, the memory units 1724A-1724N may also include stacked 3D memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across the memory units 1724A-1724N, allowing the partition units 1720A-1720N to write portions of each render target in parallel to efficiently utilize available bandwidth of the parallel processor memory 1722.In at least one embodiment, a local instance of parallel processor memory 1722 may be eliminated in favor of a unified memory design that uses system memory in conjunction with local cache memory.

[0271] In at least one embodiment, any of the clusters 1714A-1714N of the processing cluster arrangement 1712 may process data written to any of the memory units 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 may be configured to transfer an output of each cluster 1714A-1714N to any of the partition units 1720A-1720N or to another cluster 1714A-1714N that may perform additional processing operations on an output. In at least one embodiment, each cluster 1714A-1714N may communicate with the memory interface 1718 through the memory crossbar 1716 to read from or write to various external memory devices.In at least one embodiment, the memory crossbar 1716 includes a connection to the memory interface 1718 to communicate with the I / O unit 1704, as well as a connection to a local instance of the parallel processor memory 1722, which enables processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to the parallel processing unit 1702. In at least one embodiment, the memory crossbar 1716 may use virtual channels to separate traffic flows between the clusters 1714A-1714N and the partition units 1720A-1720N.

[0272] In at least one embodiment, multiple instances of the parallel processing unit 1702 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1702 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. In at least one embodiment, the parallel processing unit 1702 may be configured to interoperate with one or more instances of the parallel processing unit 1702. For example, in at least one embodiment, some instances of the parallel processing unit 1702 may include higher-precision floating-point units relative to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 1702 or the parallel processor 1700 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld PCs, servers, workstations, game consoles, and / or embedded systems.

[0273] Fig. 17B is a block diagram of a partition unit 1720 according to at least one embodiment. In at least one embodiment, the partition unit 1720 is an instance of one of the partition units 1720A-1720N of Fig. 17A. In at least one embodiment, partition unit 1720 includes an L2 cache 1721, a frame buffer interface 1725, and a ROP 1726 (raster operation unit). L2 cache 1721 is a read / write cache configured to perform load and store operations received from memory crossbar 1716 and ROP 1726. In at least one embodiment, read misses and urgent write-back requests are issued by L2 cache 1721 to frame buffer interface 1725 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 1725 for processing. In at least one embodiment, frame buffer interface 1725 interfaces with one of the memory units in parallel processor memory, such as memory units 1724A-1724N of Fig. 17 (e.g. within the parallel processor memory 1722).

[0274] In at least one embodiment, ROP 1726 is a processing unit that performs raster operations such as stencil, z-test, blending, and the like. In at least one embodiment, ROP 1726 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, the type of compression performed by ROP 1726 may vary based on statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0275] In at least one embodiment, the ROP 1726 is within each processing cluster (e.g., clusters 1714A-1714N of Fig. 17) rather than within the partition unit 1720. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted over the memory crossbar 1716. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1610 of Fig. 16, are displayed, are passed for further processing by the processor(s) 1602 or for further processing by one of the processing entities within the parallel processor 1700 of Fig. 17A.

[0276] Fig. 17C is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 1714A-1714N of Fig. 17. In at least one embodiment, the processing cluster 1714 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction-multiple-data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction-multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters.

[0277] In at least one embodiment, the operation of the processing cluster 1714 may be controlled by a pipeline manager 1732 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 receives instructions from the scheduler 1710 of Fig. 17 and manages the execution of these instructions via a graphics multiprocessor 1734 and / or a texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 1714. In at least one embodiment, one or more instances of the graphics multiprocessor 1734 may be included within a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 may process data, and a data crossbar 1740 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 1732 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 1740.

[0278] In at least one embodiment, each graphics multiprocessor 1734 within the processing cluster 1714 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, in which new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may be present.

[0279] In at least one embodiment, instructions transferred to processing cluster 1714 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within a graphics multiprocessor 1734. In at least one embodiment, a thread group may contain fewer threads than a number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when a thread group contains fewer threads than a number of processing engines, one or more processing engines may be idle during cycles in which that thread group is processing.In at least one embodiment, a thread group may also include more threads than a number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when a thread group includes more threads than a number of processing engines within the graphics multiprocessor 1734, processing may be executed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 1734.

[0280] In at least one embodiment, the graphics multiprocessor 1734 includes an internal cache to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1734 may forgo an internal cache and use a cache (e.g., L1 cache 1748) within the processing cluster 1714. In at least one embodiment, each graphics multiprocessor 1734 also has access to L2 caches within partition units (e.g., partition units 1720A-1720N of Fig. 17) that are shared by all processing clusters 1714 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 can be used as global memory. In at least one embodiment, processing cluster 1714 includes multiple instances of graphics multiprocessor 1734 that can share common instructions and data, which can be stored in L1 cache 1748.

[0281] In at least one embodiment, each processing cluster 1714 may include a memory management unit (MMU) 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1745 may reside within the memory interface 1718 of Fig. 17. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, the MMU 1745 may include address translation buffers (TLBs) or caches that may be located within the graphics multiprocessor 1734 or the L1 cache or the processing cluster 1714. In at least one embodiment, the physical address is processed to distribute surface data access locality to enable efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0282] In at least one embodiment, a processing cluster 1714 may be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 issues processed tasks to the data crossbar 1740 to provide a processed task to another processing cluster 1714 for further processing or to store a processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1716.In at least one embodiment, the PreROP 1742 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1734, pass data to the ROP units, which may be located with partition units as described herein (e.g., partition units 1720A-1720N of . Fig. 17). In at least one embodiment, the PreROP 1742 unit may perform optimizations for color mixing, organize pixel color data, and perform address translations.

[0283] In at least one embodiment, at least one component related to Fig. 17A-C is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 17, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one parallel processor 1700 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one parallel processor 1700 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0284] Fig. 17D illustrates a graphics multiprocessor 1734 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1734 is coupled to the pipeline manager 1732 of the processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general-purpose graphic processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to the cache memory 1772 and the shared memory 1770 via a memory and cache interconnect 1768.

[0285] In at least one embodiment, instruction cache 1752 receives a stream of instructions to be executed from pipeline manager 1732. In at least one embodiment, instructions are cached in instruction cache 1752 and dispatched for execution by instruction unit 1754. In at least one embodiment, instruction unit 1754 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within GPGPU core 1762. In at least one embodiment, an instruction may access any of a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, the address mapping unit 1756 may be used to translate addresses in a unified address space into a unique memory address that can be accessed by the load / store units 1766.

[0286] In at least one embodiment, register file 1758 provides a set of registers for functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 1762, load / store units 1766) of graphics multiprocessor 1734. In at least one embodiment, register file 1758 is partitioned between each of the functional units such that each functional unit is assigned a dedicated portion of register file 1758. In at least one embodiment, register file 1758 is partitioned between different warps executed by graphics multiprocessor 1734.

[0287] In at least one embodiment, the GPGPU cores 1762 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of the graphics multiprocessor 1734. The GPGPU cores 1762 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of the GPGPU cores 1762 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic.In at least one embodiment, graphics multiprocessor 1734 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0288] In at least one embodiment, GPGPU cores 1762 include SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 1762 may physically execute instructions from SIMD4, SIMD8, and SIMD16, and logically execute instructions from SIMD1, SIMD2, and SIMD32. In at least one embodiment, SIMD instructions for GPGPU cores may be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single-program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may execute from a single SIMD instruction.For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0289] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network that connects each functional unit of the graphics multiprocessor 1734 to the register file 1758 and to the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a crossbar interconnect that enables the load / store unit 1766 to implement load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 may operate at the same frequency as the GPGPU cores 1762, such that data transfer between the GPGPU cores 1762 and the register file 1758 has very low latency.In at least one embodiment, shared memory 1770 may be used to enable communication between threads executing on functional units within graphics multiprocessor 1734. In at least one embodiment, cache 1772 may be used, for example, as a data cache to cache texture data communicated between the functional units and texture unit 1736. In at least one embodiment, shared memory 1770 may also be used as a cached managed program. In at least one embodiment, threads executing on GPGPU cores 1762 may programmatically store data within shared memory in addition to automatically cached data stored within cache 1772.

[0290] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or die as the cores and communicatively coupled to the cores via an internal processor bus / interconnect (i.e., internal to the package or die).In at least one embodiment, processor cores, regardless of how the GPU is connected, may allocate work to the GPU in the form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0291] In at least one embodiment, at least one component related to Fig. 17D is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 17D, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, identify and / or select MCS and / or a number of RBs, generate transmission priority metrics, or otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one graphics multiprocessor 1734 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one graphics multiprocessor 1734 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0292] Fig. 18 illustrates a multi-GPU computing system 1800 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general-purpose graphic processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, the host interface switch 1804 is a PCI Express switch device that couples the processor 1802 to a PCI Express bus over which the processor 1802 can communicate with GPGPUs 1806A-D. In at least one embodiment, the GPU-to-GPU connections 1816 connect to each of the GPGPUs 1806A-D via a dedicated GPU connection. In at least one embodiment, the P2P GPU connections 1816 enable direct communication between each of the GPGPUs 1806A-D without requiring communication over the host interface bus 1804 to which the processor 1802 is connected.In at least one embodiment, host interface bus 1804 remains available with GPU-to-GPU traffic directed to P2P GPU connections 1816 for system memory access or for communicating with other instances of multi-GPU computing system 1800, for example, via one or more network devices. While GPGPUs 1806A-D connect to processor 1802 via host interface switch 1804 in at least one embodiment, processor 1802 includes direct support for P2P GPU connections 1816 and may connect directly to GPGPUs 1806A-D in at least one embodiment.

[0293] In at least one embodiment, at least one component related to Fig. 18 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 18, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one GPGPU 1806 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one GPGPU 1806 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0294] Fig. 19 is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, the graphics processor 1900 includes a ring interconnect 1902, a pipelined front-end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, the ring interconnect 1902 couples the graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1900 is one of many processors integrated into a multi-core processing system.

[0295] In at least one embodiment, graphics processor 1900 receives batches of commands via ring interconnect 1902. In at least one embodiment, incoming commands are interpreted by a command streamer 1903 in pipeline front-end 1904. In at least one embodiment, graphics processor 1900 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 1980A-1980N. In at least one embodiment, command streamer 1903 provides commands to geometry pipeline 1936 for 3D geometry processing commands. In at least one embodiment, command streamer 1903 provides commands to a video front-end 1934 coupled to a media engine 1937 for at least some media processing commands.In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing and a multi-format encoder / decoder (MFX) engine 1933 to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0296] In at least one embodiment, graphics processor 1900 includes scalable threaded execution resources with modular cores 1980A-1980N (sometimes referred to as core slices), each having a plurality of sub-cores 1950A-1980N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1900 may include any number of graphics cores 1980A-1980N. In at least one embodiment, graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, graphics processor 1900 is a low-performance processor having a single sub-core (e.g., 1950A). In at least one embodiment, the graphics processor 1900 includes a plurality of graphics cores 1980A-1980N, each including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N.In at least one embodiment, each subcore in the first subcores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each subcore in the second subcores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each subcore 1950A-1950N, 1960A-1960N utilizes a set of shared resources 1970A-1970N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0297] In at least one embodiment, at least one component related to Fig. 19 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 19, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one graphics processor 1900 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one graphics processor 1900 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0298] Fig. 20 is a block diagram illustrating a microarchitecture for a processor 2000 that may include logic circuitry to execute instructions according to at least one embodiment. In at least one embodiment, the processor 2000 may execute instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2010 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point forms, may operate on packed data elements accompanying single instruction, multiple data ("SIMD"), and streaming SIMD extension ("SSE") instructions.In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond technology (commonly referred to as "SSEx") may hold such packed data operands. In at least one embodiment, processors 2010 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0299] In at least one embodiment, processor 2000 includes an in-order front end ("front end") 2001 to fetch instructions to be executed and prepare instructions to be used later in the processor pipeline. In at least one embodiment, front end 2001 may include multiple units. In at least one embodiment, an instruction prefetcher 2026 fetches instructions from memory and supplies instructions to an instruction decoder 2028, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2028 decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also referred to as "micro-ops" or "uops"), that the machine may execute.In at least one embodiment, instruction decoder 2028 parses instructions into an opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2030 can assemble decoded uops into program-ordered sequences or tracks in a uop queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters a complex instruction, a microcode ROM 2032 provides uops needed to complete the operation.

[0300] In at least one embodiment, some instructions may be converted into a single micro-operation, while others may require multiple micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, instruction decoder 2028 may access microcode ROM 2032 to perform an instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing at instruction decoder 2028. In at least one embodiment, an instruction may be stored within microcode ROM 2032 if a number of micro-operations are required to complete the operation.In at least one embodiment, trace cache 2030 refers to a programmable entry point logic array ("PLA") for determining a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2032 according to at least one embodiment. In at least one embodiment, after microcode ROM 2032 finishes sequencing microoperations for an instruction, machine front-end 2001 may resume fetching microoperations from trace cache 2030.

[0301] In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 2003 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has a number of buffers to smooth and reorder the flow of instructions to optimize performance as they enter the pipeline and are scheduled for execution. The out-of-order execution engine 2003 includes, without limitation, an allocator / register renamer 2040, a memory uop queue 2042, an integer / floating point uop queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general floating point scheduler ("slow / general FP scheduler") 2004, and a simple floating point scheduler ("simple FP scheduler") 2006. In at least one embodiment, the allocator / register renamer 2040 allocates machine buffers and resources that each uop requires to execute.In at least one embodiment, the allocator / register renamer 2040 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2040 also allocates an entry for each uop in one of two uop queues, the memory uop queue 2042 for memory operations and the integer / floating point uop queue 2044 for non-memory operations, prior to the memory scheduler 2046 and the uop schedulers 2002, 2004, 2006. In at least one embodiment, the uop schedulers 2002, 2004, 2006 determine when a uop is ready for execution based on the readiness of its dependent input register operand sources and the availability of execution resources that uops require to complete their operation.In at least one embodiment, the fast scheduler 2002 of at least one embodiment may schedule on each half of the main clock cycle, while the slow / general floating-point scheduler 2004 and the simple floating-point scheduler 2006 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2002, 2004, 2006 arbitrate dispatch ports to schedule uops for execution.

[0302] In at least one embodiment, execution block b11 includes, without limitation, an integer register file / bypass network 2008, a floating-point register file / bypass network (“FP register file / bypass network”) 2010, address generation units (“AGUs”) 2012 and 2014, fast arithmetic logic units (ALUs) (“Fast ALUs”) 2016 and 2018, a slow arithmetic logic unit (“Slow ALU”) 2020, a floating-point ALU (“FP”) 2022, and a floating-point move unit (“FP move”) 2024. In at least one embodiment, the integer register file / bypass network 2008 and the floating-point register file / bypass network 2010 are also referred to herein as “register files 2008, 2010.”In at least one embodiment, the AGUs 2012 and 2014, the fast ALUs 2016 and 2018, the slow ALU 2020, the floating-point ALU 2022, and the floating-point movement unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024." In at least one embodiment, the execution block b11 may include, without limitation, any number (including zero) and any type of register files, bypass networks, address generation units, and execution units in any combination.

[0303] In at least one embodiment, register files 2008, 2010 may be located between uop schedulers 2002, 2004, 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / bypass network 2008 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008, 2010 may include, without limitation, a bypass network that may bypass just-completed results that have not yet been written to the register file or forward them to new dependent uops. In at least one embodiment, register files 2008, 2010 may communicate data with each other.In at least one embodiment, the integer register file / bypass network 2008 may include, without limitation, two separate register files, one register file for 32 low-order data bits and a second register file for 32 high-order data bits. In at least one embodiment, the floating-point register file / bypass network 2010 may include, without limitation, 128-bit wide entries, as floating-point instructions typically have operands 64 to 128 bits wide.

[0304] In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 may execute instructions. In at least one embodiment, register files 2008, 2010 store integer and floating-point data operand values ​​that microinstructions must execute. In at least one embodiment, processor 2000 may include, without limitation, any number and combination of execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024. In at least one embodiment, floating-point ALU 2022 and floating-point move unit 2024 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating-point ALU 2022 may include, without limitation, a 64-bit by 64-bit floating-point divider for performing divide, square root, and remainder micro-ops.In at least one embodiment, instructions involving a floating-point value may be handled with floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2016, 2018. In at least one embodiment, the fast ALUs 2016, 2018 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, the most complex integer operations go to the slow ALU 2020, since the slow ALU 2020 may include, without limitation, integer execution hardware for some type of long-latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by the ALUs 2012, 2014.In at least one embodiment, the fast ALU 2016, the fast ALU 2018, and the slow ALU 2020 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2016, the fast ALU 2018, and the slow ALU 2020 may be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 may be implemented to support a range of operands with bits of different widths. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0305] In at least one embodiment, the uop schedulers 2002, 2004, 2006 dispatch dependent operations before the predecessor load has completed execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2000, the processor 2000 may also include logic to handle memory misses. In at least one embodiment, when a data load fails in the data cache, there may be dependent operations in flight in the pipeline that have exited the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks instructions that use incorrect data and reexecutes them. In at least one embodiment, dependent operations may need to be replayed and independent operations may complete.In at least one embodiment, the schedulers and rendering mechanism of at least one embodiment of a processor may also be configured to detect instruction sequences for text string comparison operations. In at least one embodiment, the schedulers and rendering mechanism of at least one embodiment of a processor may be configured to detect instruction sequences for text string comparison operations.

[0306] In at least one embodiment, the term "register" may refer to on-board processor memory locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, a register may store data, provide data, and perform functions described herein.In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0307] In at least one embodiment, at least one component related to Fig. 20 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 20, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one processor 2000 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one processor 2000 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0308] Fig. 21 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2100 includes one or more processors 2102 and one or more graphics processors 2108, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system with a large number of processors 2102 or processor cores 2107. In at least one embodiment, system 2100 is a processing platform embodied in a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0309] In at least one embodiment, system 2100 may include a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console, or may be included in a server-based gaming platform. In at least one embodiment, system 2100 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2100 may also include, be coupled to, or integrated with a wearable device, such as a wearable smartwatch device, a smartglass device, an augmented reality device, or a virtual reality device.In at least one embodiment, processing system 2100 is a television or set-top box device having one or more processors 2102 and a graphical interface generated by one or more graphics processors 2108.

[0310] In at least one embodiment, one or more processors 2102 each include one or more processor cores 2107 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2107 is configured to process a specific instruction set 2109. In at least one embodiment, the instruction set 2109 may enable complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW) computing. In at least one embodiment, the processor cores 2107 may each process a different instruction set 2109, which may include instructions to enable emulation of other instruction sets. In at least one embodiment, the processor core 2107 may also include other processing devices, such as a digital signal processor (DSP).

[0311] In at least one embodiment, processor 2102 includes cache memory 2104. In at least one embodiment, processor 2102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared by various components of processor 2102. In at least one embodiment, processor 2102 also uses an external cache (e.g., a Level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared by processor cores 2107 using known cache coherence techniques. In at least one embodiment, register file 2106 is additionally included in processor 2102, which may include various types of registers for storing various types of data (e.g., integer registers, floating-point registers, status registers, and an instruction pointer register).In at least one embodiment, register file 2106 may include general purpose registers or other registers.

[0312] In at least one embodiment, one or more processors 2102 are coupled to one or more interface buses 2110 to communicate communication signals, such as address, data, or control signals, between the processor 2102 and other components in the system 2100. In at least one embodiment, the interface bus 2110 may be a processor bus, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface 2110 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor(s) 2102 include an integrated memory controller 2116 and a platform control node 2130.In at least one embodiment, the memory controller 2116 enables communication between a memory device and other components of the system 2100, while the platform control node (PCH) 2130 provides connections to I / O devices via a local I / O bus.

[0313] In at least one embodiment, memory device 2120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or other memory device with suitable performance to serve as process memory. In at least one embodiment, memory device 2120 may operate as system memory for system 2100 to store data 2122 and instructions 2121 for use when one or more processors 2102 are executing an application or process. In at least one embodiment, memory controller 2116 also couples to an optional external graphics processor 2112 that can communicate with one or more graphics processors 2108 in processors 2102 to perform graphics and media operations.In at least one embodiment, a display device 2111 may be connected to the processor(s) 2102. In at least one embodiment, the display device 2111 may include one or more of an internal display device, such as in a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2111 may include a head-mounted display (HMD), such as a stereoscopic display device, for use in virtual reality (VR) or augmented reality (AR) applications.

[0314] In at least one embodiment, the platform control node 2130 enables peripherals to connect to the storage device 2120 and the processor 2102 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, among others, an audio controller 2146, a network controller 2134, a firmware interface 2128, a wireless transceiver 2126, touch sensors 2125, and a data storage device 2124 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2124 may connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, the touch sensors 2125 may include touchscreen sensors, pressure sensors, or fingerprint sensors.In at least one embodiment, the wireless transceiver 2126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a cellular network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2128 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2134 may enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to the interface bus 2110. In at least one embodiment, the audio controller 2146 is a multi-channel high-resolution audio controller. In at least one embodiment, the system 2100 includes an optional legacy I / O controller 2140 for coupling legacy (e.g.,Personal System 2 (PS / 2) devices to the system. In at least one embodiment, the platform control node 2130 may also be connected to one or more Universal Serial Bus (USB) controllers 2142 that connect input devices, such as keyboard and mouse combinations 2143, a camera 2144, or other USB input devices.

[0315] In at least one embodiment, an instance of the memory controller 2116 and the platform control node 2130 may be integrated into a discrete external graphics processor, such as the external graphics processor 2112. In at least one embodiment, the platform control node 2130 and / or the memory controller 2116 may be located external to one or more processors 2102. For example, in at least one embodiment, the system 2100 may include an external memory controller 2116 and a platform control node 2130, which may be configured as a memory control node and a peripheral control node within a system chipset in communication with the processor(s) 2102.

[0316] In at least one embodiment, at least one component related to Fig. 21 is used to implement techniques and / or functions associated with Fig. 1-5. In at least one embodiment, one or more components related to Fig. 21, logic or otherwise to predict one or more wireless transmission error rates based at least in part on one or more SNR measurements, to identify and / or select MCS and / or a number of RBs, to generate transmission priority metrics, or to otherwise perform operations associated with Fig. 1-5. In at least one embodiment, at least one graphics processor 2108 is used to perform selection of packet MCS information 140, identification of RB information 144, generation of transmission priority metrics 148, generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER and / or scheduling a wireless packet transmission based at least in part on SNR. In at least one embodiment, at least one graphics processor 2108 performs at least one aspect related to the processor 118, the accelerator 122, the processor 124, the error rate predictor 134, the MCS selector 138, the RB identifier 142, and / or the packet transmission scheduler 146 of Fig. 1, the technology 200 of Fig. 2, the technology 300 of Fig. 3, the processor 402 of Fig. 4 and / or one or more APIs 510 of Fig. 5 is described.

[0317] Fig. 22 is a block diagram of a processor 2200 having one or more processor cores 2202A-2202N, an integrated memory controller 2214, and an integrated graphics processor 2208, accord...

Claims

[1] Processor comprising: one or more circuits for predicting one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements. [2] The processor of claim 1, wherein the one or more circuits are to cause a modulation and coding scheme to be selected based at least in part on the one or more wireless transmission error rates. [3] The processor of claim 1, wherein the one or more circuits are to cause a number of resource blocks to be selected based at least in part on the one or more wireless transmission error rates. [4] The processor of claim 1, wherein the one or more circuits are to cause a modulation and coding scheme and a number of resource blocks to be selected based at least in part on the one or more wireless transmission error rates. [5] The processor of claim 1, wherein the one or more SNR measurements are based at least in part on one or more indications of channel quality between a base station and one or more user equipment (UE) devices. [6] The processor of claim 1, wherein the one or more circuits are to cause a modulation and coding scheme to be selected based at least in part on the one or more wireless transmission error rates and to cause one or more packets to be transmitted based at least in part on the modulation and coding scheme. [7] The processor of claim 1, wherein the one or more circuits are to cause a number of resource blocks to be selected based at least in part on the one or more wireless transmission error rates, cause one or more transmission priority metrics to be generated based at least in part on the number of resource blocks, and cause one or more packets to be transmitted based at least in part on the one or more transmission priority metrics. [8] System comprising: one or more processors for predicting one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements. [9] The system of claim 8, wherein the one or more wireless transmission error rates are block error rates (BLER) of packets to be transmitted to one or more user equipment (UE) devices. [10] The system of claim 8, wherein the one or more processors are to cause a modulation and coding scheme to be selected based at least in part on the one or more wireless transmission error rates. [11] The system of claim 8, wherein the one or more processors are to cause a number of resource blocks to be selected to transmit a particular packet based at least in part on the one or more wireless transmission error rates. [12] The system of claim 8, wherein the one or more SNR measurements are based at least in part on one or more indications of channel quality received by a gNodeB from one or more user equipment (UE) devices. [13] The system of claim 8, wherein the one or more processors are also to cause a number of resource blocks to be selected to transmit a particular packet based at least in part on the one or more wireless transmission error rates; and cause the particular packet to be scheduled to be transmitted based at least in part on the number of resource blocks. [14] Method comprising: Predicting one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements. [15] The method of claim 14, further comprising: selecting a modulation and coding scheme based at least in part on the one or more wireless transmission error rates. [16] The method of claim 14, further comprising: selecting a number of resource blocks to be used to transmit data based at least in part on the one or more wireless transmission error rates. [17] The method of claim 14, further comprising: selecting a modulation and coding scheme and a number of resource blocks to be used to transmit data based at least in part on the one or more wireless transmission error rates. [18] The method of claim 14, wherein the wireless transmission error rates are block error rates (BLER) of packets to be transmitted from a base station to one or more user equipment (UE) devices. [19] The method of claim 14, wherein the wireless transmission error rates are block error rates (BLER) of packets, and the method further comprises: Selecting a modulation and coding scheme (MCS) and a number of resource blocks to be used to transmit data based at least in part on the one or more wireless transmission error rates; and Generating one or more scheduling metrics based at least in part on the number of resource blocks. [20] A non-transitory computer-readable medium having stored thereon a set of instructions which, when executed by one or more processors, cause the one or more processors to perform at least the method of claim 14.

Images