Application programming interface for decryption

Abstract

Apparatus, systems, and techniques for implementing an application programming interface (API). In at least one embodiment, the API is to cause encrypted information to be decrypted based at least in part on one or more encryption algorithm indicators.

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application incorporates by reference for all purposes the entire disclosure of copending U.S. patent application No. _____, filed concurrently with this application, entitled "ENCRYPTION ALGORITHM IDENTIFICATION" (Attorney Docket No. 0112912-507US0), and copending U.S. patent application No. _____, filed concurrently herewith, entitled "APPLICATION PROGRAMMING INTERFACE TO ENCRYPT" (Attorney Docket No. 0112912-B94US0). AREA

[0002] At least one embodiment relates to one or more encryption algorithms identified by one or more indicators. For example, at least one embodiment relates to computer-executable instructions that include one or more indicators that identify one or more encryption algorithms. BACKGROUND

[0003] Encryption algorithms can be used to conceal information. Typically, an encryption algorithm is used to convert plaintext information into ciphertext. More specifically, the encryption algorithm converts plaintext information into ciphertext that is understandable to humans and / or machines. The encryption algorithm can convert ciphertext into plaintext information that is understandable to humans and / or machines. The techniques for using encryption algorithms can be improved to improve data protection, memory utilization, data storage utilization, computing resource performance, and the like. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an exemplary environment for encrypting information according to at least one embodiment; Fig.2 shows an exemplary environment for encrypting one or more parameters of a neural network according to at least one embodiment; Fig. 3 shows an exemplary system environment for decrypting information according to at least one embodiment; Fig. 4 shows an exemplary system environment for decrypting information according to at least one embodiment; Fig. 5 shows an exemplary system environment including a system usable for performing cryptographic operations according to at least one embodiment; Fig. 6 illustrates an exemplary system environment including a system usable for performing cryptographic operations in accordance with at least one embodiment; Fig.7 is a block diagram including a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment; Fig. 8 shows an encryption process according to at least one embodiment; Fig. 9 shows an encryption process according to at least one embodiment; Fig. 10 shows a decryption process according to at least one embodiment; Fig. 11 shows a decryption process according to at least one embodiment; Fig. 12 shows an exemplary data center according to at least one embodiment; Fig. 13 shows a processing system according to at least one embodiment; Fig. 14 shows a computer system according to at least one embodiment; Fig.15 shows a system according to at least one embodiment; Fig. 16 shows an exemplary integrated circuit according to at least one embodiment; Fig. 17 shows a computer system according to at least one embodiment; Fig. 18 shows an APU according to at least one embodiment; Fig. 19 shows a CPU according to at least one embodiment; Fig. 20 shows an exemplary accelerator integration slice according to at least one embodiment; Fig. 21A-21B illustrate exemplary graphics processors according to at least one embodiment; Fig. 22A shows a graphics core according to at least one embodiment; Fig. 22B shows a GPGPU according to at least one embodiment; Fig. 23A shows a parallel processor according to at least one embodiment; Fig.23B shows a processing cluster according to at least one embodiment; Fig. 23C shows a graphics multiprocessor according to at least one embodiment; Fig. 24 shows a graphics processor according to at least one embodiment; Fig. 25 shows a processor according to at least one embodiment; Fig. 26 shows a processor according to at least one embodiment; Fig. 27 shows a graphics processor core according to at least one embodiment; Fig. 28 shows a PPU according to at least one embodiment; Fig. 29 shows a GPC according to at least one embodiment; Fig. 30 shows a streaming multiprocessor according to at least one embodiment; Fig. 31 shows a software stack of a programming platform according to at least one embodiment; Fig.32 shows a CUDA implementation of a software stack of Fig. 31 according to at least one embodiment; Fig. 33 shows a ROCm implementation of a software stack of Fig. 31 according to at least one embodiment; Fig. 34 shows an OpenCL implementation of a software stack of Fig. 31 according to at least one embodiment; Fig. 35 shows software supported by a programming platform according to at least one embodiment; Fig. 36 shows compiling code for execution on programming platforms of the Fig. 31 - 34 according to at least one embodiment; Fig. 37 shows in more detail how to compile code for execution on programming platforms of the Fig. 31 - 34 according to at least one embodiment; Fig.38 illustrates the translation of source code prior to compiling source code in accordance with at least one embodiment; Fig. 39A shows a system configured to compile and execute CUDA source code using different types of processing units according to at least one embodiment; Fig. Figure 39B shows a system configured to run the CUDA source code from Fig. 39A compiles and executes using a CPU and a CUDA-enabled GPU according to at least one embodiment; Fig. Figure 39C shows a system configured to run the CUDA source code from Fig. 39A compiles and executes using a CPU and a non-CUDA-capable GPU according to at least one embodiment; Fig. 40 shows an example kernel translated by a CUDA-to-HIP translation tool from Fig.39C according to at least one embodiment; Fig. 41 shows a non-CUDA capable GPU from Fig. 39C in greater detail, in accordance with at least one embodiment; Fig. 42 shows how threads of an example CUDA grid are allocated to different processing units of Fig. 41, in accordance with at least one embodiment; Fig. 43 shows how existing CUDA code is migrated to Data Parallel C++ code, according to at least one embodiment; and Fig. 44 shows components of a system for accessing a large language model, according to at least one embodiment. DETAILED DESCRIPTION

[0004] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, one skilled in the art will appreciate that the inventive concepts may be practiced without one or more of these specific details.

[0005] In at least one embodiment, the information is identified for encryption. In at least one embodiment, the information is data. In at least one embodiment, the information is associated with at least one neural network. In at least one embodiment, the information is generated based on the training of at least one neural network. In at least one embodiment, the information comprises the parameters of a neural network. In at least one embodiment, the information comprises weights of a neural network. In at least one embodiment, the information comprises parameters of a neural network model generated by the training of at least one neural network.

[0006] In at least one embodiment, the information identified for encryption is located in a data structure. In at least one embodiment, the data structure is a file accessible by a computer system. In at least one embodiment, the data structure is an archive file. In at least one embodiment, the archive file may include one or more parameters of at least one neural network. In at least one embodiment, the archive file may include one or more weights of at least one neural network.

[0007] In at least one embodiment, the information identified for encryption is obtained by computer-executable instructions executed by at least one processor. In at least one embodiment, the described computer-executable instructions are executed by at least one processor to perform the behavior and / or functions described herein. In at least one embodiment, the information to be identified comprises at least one identifier. In at least one embodiment, the at least one identifier is associated with an encryption algorithm. In at least one embodiment, the computer-executable instructions comprise the encryption algorithm, and the encryption algorithm can be located using the at least one identifier. In at least one embodiment, the identifier is associated with a salt.In at least one embodiment, the salt is a string that can be combined with an encryption algorithm. In at least one embodiment, the salt is a random sequence of bytes generated by a string generator function.

[0008] In at least one embodiment, the computer-executable instructions use the at least one identifier to locate an associated encryption algorithm. In at least one embodiment, the computer-executable instructions use the associated encryption algorithm to encrypt information. In at least one embodiment, the at least one identifier is associated with encrypted information. In at least one embodiment, the at least one identifier is associated with metadata of encrypted information.

[0009] In at least one embodiment, computer-executable instructions decrypt encrypted information. In at least one embodiment, the computer-executable instructions locate an encryption algorithm using at least one identifier associated with the encrypted information. In at least one embodiment, the computer-executable instructions locate the encryption algorithm by referring to metadata of the encrypted information, determine that the metadata includes at least one identifier, and determine the encryption algorithm based on the at least one identifier. In at least one embodiment, the located encryption algorithm is used by computer-executable instructions to decrypt encrypted information.

[0010] In at least one embodiment, a computer-implemented system receives information to be encrypted. In at least one embodiment, the computer-implemented system selects at least one encryption algorithm from a plurality of encryption algorithms to encrypt the information. In at least one embodiment, each of the plurality of encryption algorithms has an associated identifier. In at least one embodiment, the computer-implemented system randomly selects at least one encryption algorithm from a plurality of encryption algorithms to encrypt the information. In at least one embodiment, the computer-implemented system associates an identifier associated with an encryption algorithm that encrypted the information with the encrypted information.In at least one embodiment, the identifier is included in the metadata of the encrypted information.

[0011] Fig.1 shows an exemplary system environment 100 for encrypting information according to at least one embodiment. In at least one embodiment, a system 102 provides information 104. In at least one embodiment, the system 102 includes one or more processors and one or more computer-executable instructions executeable by the one or more processors. In at least one embodiment, the one or more processors execute the one or more computer-executable instructions to generate information 104. In at least one embodiment, the system 102 includes one or more neural networks for providing information 104.In at least one embodiment, the one or more computer-executable instructions are hosted by one or more computer-implemented memories, such as a volatile and / or a non-volatile computer-implemented memory.

[0012] In at least one embodiment, information 104 is received by a system 106. In at least one embodiment, information 104 is communicated by system 102 to system 106. In at least one embodiment, systems 102 and 106 are systems separated by a wired and / or wireless communication arrangement. In at least one embodiment, systems 102 and 106 are collectively integrated into a common systems environment. In at least one embodiment, system 106 includes one or more processors and one or more computer-executable instructions executed by the one or more processors.

[0013] In at least one embodiment, system 106 includes a cryptography engine 108. In at least one embodiment, cryptography engine 108 performs one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, cryptography engine 108 is included in the one or more computer-executable instructions of system 106. In at least one embodiment, cryptography engine 108 includes hardware and / or software, such as hardware and / or software of system 106.

[0014] In at least one embodiment, the cryptography engine 108 includes an encryption algorithm lookup table 110. In at least one embodiment, the encryption algorithm lookup table 110 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 110 includes a plurality of encryption algorithm indicators, each encryption algorithm indicator associated with an encryption algorithm. In at least one embodiment, an encryption algorithm indicator can be used to locate an associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 110 provides a mapping of encryption algorithm indicators to encryption algorithms.In at least one embodiment, the cryptography engine 108 assigns encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls assign encryption algorithm indicators to encryption algorithms.

[0015] In at least one embodiment, system 106 includes an encryption algorithm memory 112. In at least one embodiment, encryption algorithm memory 112 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, encryption algorithm memory 112 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in encryption algorithm memory 112 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, an encryption algorithm indicator is associated with at least one encryption algorithm in encryption algorithm memory 112.In at least one embodiment, an encryption algorithm indicator is included in the metadata of at least one encryption algorithm in the encryption algorithm store 112.

[0016] In at least one embodiment, the cryptography engine 108 may locate an encryption algorithm in the encryption algorithm memory 112 by referencing the encryption algorithm lookup table 110, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate an encryption algorithm in the encryption algorithm memory 112 by matching the encryption algorithm indicator in the encryption algorithm lookup table 110 with a similar encryption algorithm indicator associated with an encryption algorithm housed in the encryption algorithm memory 112.

[0017] In at least one embodiment, the information 104 may be received by the system 106. In at least one embodiment, the information 104 is to be encrypted by the cryptography engine 108. In at least one embodiment, the cryptography engine 108 locates an encryption algorithm indicator in the encryption algorithm lookup table 110. In at least one embodiment, the encryption algorithm indicator is an opaque identifier for an encryption algorithm. In at least one embodiment, the cryptography engine 108 randomly finds an encryption algorithm indicator in the encryption algorithm lookup table 110. In at least one embodiment, the cryptography engine 108 locates an encryption algorithm indicator in the encryption algorithm lookup table 110 based on an encryption algorithm indicator specified in the information 104.In at least one embodiment, the cryptography engine 108 uses the encryption algorithm indicator contained in the information 104 to locate the encryption algorithm indicator in the encryption algorithm lookup table 110. In at least one embodiment, the encryption algorithm indicator in the encryption algorithm lookup table 110 is associated with an encryption algorithm stored in the encryption algorithm memory 112. In at least one embodiment, the encryption algorithm associated with the encryption algorithm indicator is used to encrypt information 104. In at least one embodiment, the encryption of information 104 by the cryptography engine 108 and the located encryption algorithm produces encrypted information 114.In at least one embodiment, the encryption algorithm indicator associated with the encryption algorithm used to generate encrypted information 114 is associated with encrypted information 114. In at least one embodiment, the encryption algorithm indicator is associated with the metadata 116 of the encrypted information 114. In at least one embodiment, the encryption algorithm indicator is linked to other information associated with encrypted information 114.

[0018] Fig.2 shows an exemplary system environment 200 for encrypting one or more parameters of a neural network, according to at least one embodiment. In at least one embodiment, a neural network 202 provides one or more parameters 204. In at least one embodiment, the neural network 202 may be executed by one or more processors. In at least one embodiment, the one or more processors execute the neural network 202 to generate one or more parameters 204.

[0019] In at least one embodiment, one or more parameters 204 may include one or more weights, which may include the strength or amplitude of the connections between neurons in the neural network 202. In at least one embodiment, the weights may be adjusted during a learning process to reduce a difference between an actual output and an expected output of the neural network 202. In at least one embodiment, one or more parameters 204 may include one or more biases. In at least one embodiment, biases are parameters that may be added to a weighted sum of inputs to shift an activation function, which may be useful for learning a neural network.In at least one embodiment, one or more parameters 204 may include one or more activation functions, which are mathematical equations that determine an output of a neural network. This function is associated with one or more neurons in a network and determines whether or not to activate it based on whether the input of the one or more neurons is relevant to predicting a model. In at least one embodiment, one or more parameters 204 may include one or more learning rates. In at least one embodiment, a learning rate is a hyperparameter that determines a step size at each iteration while moving toward a minimum of a loss function. In at least one embodiment, one or more parameters 204 may include one or more numbers of layers and / or nodes in each layer.In at least one embodiment, a number of layers in a neural network may determine how the network will learn from data.

[0020] In at least one embodiment, one or more parameters 204 are determined by a system 206. In at least one embodiment, one or more parameters 204 are communicated to the system 206 by a neural network 202. In at least one embodiment, the neural network 202 and the system 206 are separated by a wired and / or wireless communication arrangement. In at least one embodiment, the neural network 202 and the system 206 are jointly integrated into a common system environment. In at least one embodiment, the system 206 includes one or more processors and one or more computer-executable instructions executed by the one or more processors.

[0021] In at least one embodiment, system 206 includes a cryptography engine 208. In at least one embodiment, cryptography engine 208 performs one or more cryptographic operations, such as encrypting and / or decrypting information, such as one or more parameters 204. In at least one embodiment, cryptography engine 208 is included in one or more computer-executable instructions of system 206. In at least one embodiment, cryptography engine 208 includes hardware and / or software, such as hardware and / or software of system 206.

[0022] In at least one embodiment, the cryptography engine 208 includes an encryption algorithm lookup table 210. In at least one embodiment, the encryption algorithm lookup table 210 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 210 includes a plurality of encryption algorithm indicators, each encryption algorithm indicator associated with an encryption algorithm. In at least one embodiment, an encryption algorithm indicator can be used to locate an associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 210 provides a mapping of encryption algorithm indicators to encryption algorithms.In at least one embodiment, the cryptography engine 208 assigns encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls assign encryption algorithm indicators to encryption algorithms.

[0023] In at least one embodiment, system 206 includes an encryption algorithm memory 212. In at least one embodiment, encryption algorithm memory 212 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, encryption algorithm memory 212 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in encryption algorithm memory 212 includes an associated encryption algorithm indicator. In at least one embodiment, an encryption algorithm indicator is associated with at least one encryption algorithm in encryption algorithm memory 212.In at least one embodiment, an encryption algorithm indicator is included in the metadata of at least one encryption algorithm in the encryption algorithm store 212.

[0024] In at least one embodiment, the cryptography engine 208 may locate an encryption algorithm in the encryption algorithm store 212 by referencing the encryption algorithm lookup table 210, locate an encryption algorithm indicator, and use the encryption algorithm indicator to locate an encryption algorithm in the encryption algorithm store 212 by comparing the encryption algorithm indicator in the encryption algorithm lookup table 210 to a matching encryption algorithm indicator associated with an encryption algorithm hosted in the encryption algorithm store 212.

[0025] In at least one embodiment, one or more parameters 204 may be received from system 206. In at least one embodiment, one or more parameters 204 are to be encrypted by cryptography engine 208. In at least one embodiment, cryptography engine 208 locates an encryption algorithm indicator in encryption algorithm lookup table 210. In at least one embodiment, cryptography engine 208 randomly searches for an encryption algorithm indicator in encryption algorithm lookup table 210. In at least one embodiment, cryptography engine 208 finds an encryption algorithm indicator in encryption algorithm lookup table 210 based on an encryption algorithm indicator specified in one or more parameters 204.In at least one embodiment, the cryptography engine 208 uses the encryption algorithm indicator contained in one or more parameters 204 to locate the encryption algorithm indicator in the encryption algorithm lookup table 210. In at least one embodiment, the encryption algorithm indicator in the encryption algorithm lookup table 210 is associated with an encryption algorithm stored in the encryption algorithm memory 212. In at least one embodiment, the encryption algorithm associated with the encryption algorithm indicator is used to encrypt one or more parameters 204. In at least one embodiment, encrypting one or more parameters 204 by the cryptography engine 208 and the encryption algorithm therein generates one or more encrypted parameters 204.In at least one embodiment, the encryption algorithm indicator associated with the encryption algorithm used to generate one or more encrypted parameters 214 is associated with one or more encrypted parameters 214. In at least one embodiment, the encryption algorithm indicator is associated with the metadata 216 of the one or more encrypted parameters 214. In at least one embodiment, the encryption algorithm indicator is associated with other information associated with one or more encrypted parameters 214.

[0026] In at least one embodiment, the encrypted parameter 214 is further secured by a key. In at least one embodiment, the encrypted parameter 214 is secured with the key by the cryptography engine 208. In at least one embodiment, the key is provided by a user. In at least one embodiment, the key is generated by the cryptography engine 208. In at least one embodiment, the key is generated by the cryptography engine 208 and provided to a user. In at least one embodiment, the user may provide the key to the cryptography engine 208 to further secure the encrypted parameter 214.

[0027] Fig.3 shows an example system environment 300 for decrypting information in accordance with at least one embodiment. In at least one embodiment, the encrypted information 314 is obtained by the system 306. In at least one embodiment, the system 306 includes one or more processors and one or more computer-executable instructions executeable by the one or more processors. In at least one embodiment, the system 306 includes a cryptography engine 308. In at least one embodiment, the cryptography engine 308 performs one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptography engine 308 is included in the one or more computer-executable instructions of the system 306.In at least one embodiment, the cryptography engine 308 comprises hardware and / or software, such as hardware and / or software of the system 306.

[0028] In at least one embodiment, the cryptography engine 308 includes an encryption algorithm lookup table 310. In at least one embodiment, the encryption algorithm lookup table 310 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 310 includes a plurality of encryption algorithm indicators, each encryption algorithm indicator associated with an encryption algorithm. In at least one embodiment, an encryption algorithm indicator can be used to locate an associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 310 provides a mapping of encryption algorithm indicators to encryption algorithms.In at least one embodiment, the cryptography engine 308 assigns encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls assign encryption algorithm indicators to encryption algorithms.

[0029] In at least one embodiment, system 306 includes an encryption algorithm memory 312. In at least one embodiment, encryption algorithm memory 312 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, encryption algorithm memory 312 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in encryption algorithm memory 312 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, an encryption algorithm indicator is associated with at least one encryption algorithm in encryption algorithm memory 312.In at least one embodiment, an encryption algorithm indicator is included in the metadata of at least one encryption algorithm in the encryption algorithm store 312.

[0030] In at least one embodiment, the cryptography engine 308 may locate an encryption algorithm in the encryption algorithm memory 312 by referencing the encryption algorithm lookup table 310, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate an encryption algorithm in the encryption algorithm memory 312 by matching the encryption algorithm indicator in the encryption algorithm lookup table 310 with a similar encryption algorithm indicator associated with an encryption algorithm housed in the encryption algorithm memory 312.

[0031] In at least one embodiment, encrypted information 314 may be received by system 306. In at least one embodiment, the encrypted information 314 is to be decrypted by the cryptography engine 308. In at least one embodiment, the cryptography engine 308 locates an encryption algorithm indicator in the encryption algorithm lookup table 310. In at least one embodiment, the encryption algorithm indicator is an opaque identifier for an encryption algorithm. In at least one embodiment, the cryptography engine 308 locates an encryption algorithm indicator in the encryption algorithm lookup table 310 based on an encryption algorithm indicator comprising the encrypted information 314.In at least one embodiment, the cryptography engine 308 uses the encryption algorithm indicator comprising the encrypted information 314 to locate the encryption algorithm indicator in the encryption algorithm lookup table 310. In at least one embodiment, the encryption algorithm indicator located in the encryption algorithm lookup table 310 is associated with an encryption algorithm stored in the encryption algorithm memory 312. In at least one embodiment, the encryption algorithm associated with the encryption algorithm indicator is used to decrypt encrypted information 314 to provide information 304.In at least one embodiment, decryption of encrypted information 314 by the cryptography engine 308 and the localized encryption algorithm generates decrypted information 304. In at least one embodiment, the encryption algorithm indicator is associated with the metadata 316 of the encrypted information 314. In at least one embodiment, the encryption algorithm indicator is associated with other information associated with the encrypted information 314. In at least one embodiment, the information 304 is provided to the system 302.

[0032] Fig.4 shows an example system environment 400 for decrypting information in accordance with at least one embodiment. In at least one embodiment, the encrypted one or more parameters 414 are obtained by system 406. In at least one embodiment, system 406 includes one or more processors and one or more computer-executable instructions executeable by the one or more processors. In at least one embodiment, system 406 includes a cryptography engine 408. In at least one embodiment, cryptography engine 408 performs one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, cryptography engine 408 is included in the one or more computer-executable instructions of system 406.In at least one embodiment, the cryptography engine 408 comprises hardware and / or software, such as hardware and / or software of the system 406.

[0033] In at least one embodiment, the cryptography engine 408 includes an encryption algorithm lookup table 410. In at least one embodiment, the encryption algorithm lookup table 410 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 410 includes a plurality of encryption algorithm indicators, each encryption algorithm indicator associated with an encryption algorithm. In at least one embodiment, an encryption algorithm indicator can be used to locate an associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 410 provides a mapping of encryption algorithm indicators to encryption algorithms.In at least one embodiment, the cryptography engine 408 assigns encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls assign encryption algorithm indicators to encryption algorithms.

[0034] In at least one embodiment, system 406 includes an encryption algorithm memory 412. In at least one embodiment, encryption algorithm memory 412 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, encryption algorithm memory 412 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in encryption algorithm memory 412 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, an encryption algorithm indicator is associated with at least one encryption algorithm in encryption algorithm memory 412.In at least one embodiment, an encryption algorithm indicator is included in the metadata of at least one encryption algorithm in the encryption algorithm store 412.

[0035] In at least one embodiment, the cryptography engine 408 may locate an encryption algorithm in the encryption algorithm store 412 by referencing the encryption algorithm lookup table 410, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate an encryption algorithm in the encryption algorithm store 412 by matching the encryption algorithm indicator in the encryption algorithm lookup table 410 with a similar encryption algorithm indicator associated with an encryption algorithm hosted in the encryption algorithm store 412.

[0036] In at least one embodiment, one or more encrypted parameters 414 may be received by system 406. In at least one embodiment, one or more encrypted parameters 414 are to be decrypted by cryptography engine 408. In at least one embodiment, cryptography engine 408 locates an encryption algorithm indicator in encryption algorithm lookup table 410. In at least one embodiment, the encryption algorithm indicator is an opaque identifier for an encryption algorithm. In at least one embodiment, cryptography engine 408 locates an encryption algorithm indicator in encryption algorithm lookup table 410 based on an encryption algorithm indicator that includes one or more encrypted parameters 414.In at least one embodiment, the cryptography engine 408 uses the encryption algorithm indicator, which includes one or more encrypted parameters 414, to locate the encryption algorithm indicator in the encryption algorithm lookup table 410. In at least one embodiment, the encryption algorithm indicator in the encryption algorithm lookup table 410 is associated with an encryption algorithm stored in the encryption algorithm memory 412. In at least one embodiment, the encryption algorithm associated with the encryption algorithm indicator is used to decrypt one or more encrypted parameters 414. In at least one embodiment, decryption of the encrypted parameters 414 by the cryptography engine 408 and the located encryption algorithm produces the decrypted parameters 404.In at least one embodiment, the encryption algorithm indicator is associated with the metadata 416 of one or more encrypted parameters 414. In at least one embodiment, the encryption algorithm indicator is linked to other information associated with one or more encrypted parameters 414. In at least one embodiment, the parameters 404 are provided to the neural network 402.

[0037] Fig. 5 shows an exemplary system environment 500 including a system suitable for performing cryptographic operations according to at least one embodiment. In at least one embodiment, a system 506 is included in the system environment 500. In at least one embodiment, the system 506 may be one or more of the systems described in system environments 100, 200, 300, and / or 400.

[0038] In at least one embodiment, system 506 includes a cryptography engine 508. In at least one embodiment, cryptography engine 508 performs one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, cryptography engine 508 is included in the one or more computer-executable instructions of system 506. In at least one embodiment, cryptography engine 508 includes hardware and / or software, such as hardware and / or software of system 506.

[0039] In at least one embodiment, the cryptography engine 508 includes an encryption algorithm lookup table 510. In at least one embodiment, the encryption algorithm lookup table 510 includes one or more encryption algorithm indicators 1-N associated with one or more encryption algorithms 1-N. In at least one embodiment, the encryption algorithm lookup table 510 includes a plurality of encryption algorithm indicators 1-N, each encryption algorithm indicator 1-N associated with an encryption algorithm 1-N. In at least one embodiment, an encryption algorithm indicator 1-N can be used to locate an associated encryption algorithm 1-N.In at least one embodiment, encryption algorithm lookup table 510 provides a mapping of encryption algorithm indicators to encryption algorithms. In at least one embodiment, cryptography engine 508 maps encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls map encryption algorithm indicators to encryption algorithms.

[0040] In at least one embodiment, system 506 includes an encryption algorithm memory 512. In at least one embodiment, encryption algorithm memory 512 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, encryption algorithm memory 512 includes one or more encryption algorithms 1-N. In at least one embodiment, at least one encryption algorithm 1-N in encryption algorithm memory 512 includes an associated encryption algorithm indicator 1-N. In at least one embodiment, encryption algorithm indicator 1-N is an opaque identifier of encryption algorithm 1-N. In at least one embodiment, an encryption algorithm indicator 1-N is associated with at least one encryption algorithm in encryption algorithm memory 512.In at least one embodiment, an encryption algorithm indicator 1-N is included in the metadata of at least one encryption algorithm 1-N in the encryption algorithm memory 512. In at least one embodiment, one or more of the encryption algorithm indicators 1-N is a character string, such as a numeric value, an alphanumeric value, or the like.

[0041] Fig. 6 shows an exemplary system environment 600 including a system that can be used to perform cryptographic operations according to at least one embodiment. In at least one embodiment, a system 606 is included in the system environment 600. In at least one embodiment, the system 606 may be one or more of the systems described in system environments 100, 200, 300, and / or 400.

[0042] In at least one embodiment, system 606 includes a cryptography engine 608. In at least one embodiment, cryptography engine 608 performs one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, cryptography engine 608 is included in the one or more computer-executable instructions of system 606. In at least one embodiment, cryptography engine 608 includes hardware and / or software, such as hardware and / or software of system 606.

[0043] In at least one embodiment, the cryptography engine 608 includes an encryption salt lookup table 610. In at least one embodiment, the encryption salt lookup table 610 includes one or more encryption salt indicators 1-N that can be combined with one or more encryption algorithms. In at least one embodiment, the encryption salt lookup table 610 includes a plurality of encryption salt indicators 1-N, each encryption salt indicator 1-N associated with an encryption salt 1-N. In at least one embodiment, an encryption salt indicator 1-N can be used to locate an associated encryption salt 1-N. In at least one embodiment, one or more of the encryption salts 1-N is a value, such as a character string.In at least one embodiment, one or more of the encryption salts 1-N is a randomly generated value, for example, a randomly generated string. In at least one embodiment, one or more of the encryption salts 1-N is randomly generated by the cryptography engine 608. In at least one embodiment, one or more of the encryption salts 1-N can be combined with one or more encryption algorithms to generate an encryption algorithm that can be used to encrypt and / or decrypt information, such as data or parameters of a neural network.

[0044] In at least one embodiment, system 606 includes memory 612. In at least one embodiment, memory 612 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, memory 612 includes one or more encryption salts 614 and one or more encryption algorithms 616. In at least one embodiment, one or more encryption salts 614 includes encryption salts 1-N. In at least one embodiment, memory 612 includes one or more encryption algorithms 616. In at least one embodiment, at least one encryption salt 1-N in memory 612 includes an associated encryption salt indicator 1-N. In at least one embodiment, encryption salt indicator 1-N is an opaque identifier of encryption salt 1-N.In at least one embodiment, an encryption salt indicator 1-N is associated with at least one encryption salt in memory 612. In at least one embodiment, an encryption salt indicator 1-N comprises the metadata of at least one encryption algorithm, for example, encryption algorithm 616.

[0045] Fig.7 is a block diagram illustrating a driver and / or runtime 704 including one or more libraries 706 to provide one or more application programming interfaces (APIs) 710 in accordance with at least one embodiment. In at least one embodiment, system 700 includes one or more processors for executing one or more APIs. In at least one embodiment, a software program 702 is a software module. In at least one embodiment, software program 702 includes one or more software modules coupled to one or more processors. In at least one embodiment, software program 702 includes one or more of the cryptographic engines described herein. In at least one embodiment, software program 702 is implemented by one or more of the systems and / or system environments described herein.

[0046] In at least one embodiment, one or more APIs 710 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, drivers / runtimes 704, and / or other grouping of software and / or executable code, further described herein. In at least one embodiment, one or more APIs 710 perform one or more computational operations in response to being invoked by software programs 702.In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to invoke one or more other instruction sets, such as APIs 710 or API functions 712 (e.g., to perform a cryptographic operation 716, such as encrypting or decrypting data or one or more parameters). In at least one embodiment, the functionality provided by one or more APIs 710 includes software functions 712, such as those capable of performing one or more cryptographic operations 716 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0047] In at least one embodiment, APIs 710 are hardware interfaces to one or more circuits to perform one or more computational operations, such as cryptographic operations. In at least one embodiment, one or more software APIs 710 described herein are implemented as one or more circuits to perform one or more of the following in connection with Fig. 1-11. In at least one embodiment, one or more software programs 702 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further in connection with Fig. 1-11 are described.

[0048] In at least one embodiment, software programs 702, such as user-implemented software programs, use one or more APIs 710 to perform various cryptographic operations, such as encryption of data or parameters, decryption of data or parameters, encryption of data or parameters in data structures such as files, decryption of data or parameters in data structures such as files, or any computational operation performed by one or more processors or parallel processing units (PPUs), such as graphics processing units (GPUs), as described herein.In at least one embodiment, one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and / or functions, that individually perform one or more functions and / or operations, such as encrypting data or parameters, decrypting data or parameters, encrypting data or parameters in data structures such as files, decrypting data or parameters in data structures such as files, and such cryptographic operations related to encrypting and / or decrypting information. For example, in one embodiment, one or more APIs 710 provide functions 712 to perform cryptographic operations or functions.In at least one embodiment, one or more APIs 710 may be used by one or more cryptographic engines (e.g., cryptographic engine modules) described herein. In at least one embodiment, one or more APIs 710 may be used by one or more systems and / or system environments described herein.

[0049] In at least one embodiment, one or more software programs 702 interact or communicate with one or more APIs 710 to perform one or more computational operations, such as cryptographic operations, using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to perform one or more cryptographic operations 716 on information, data, parameters, etc., generated by one or more systems and / or one or more neural networks.

[0050] In at least one embodiment, an interface consists of software instructions that, when executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, a software program 702 uses a local interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to one or more APIs 710. In at least one embodiment, one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that includes instructions for executing one or more APIs 710.In at least one embodiment, one or more software programs 702 are dynamically compiled, and the one or more software programs use a linker to link to one or more precompiled libraries 706 that include one or more APIs 710.

[0051] In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 706 comprising one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, one or more libraries 706 comprising one or more APIs 710 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 706 comprising one or more APIs 710 are executed by another computer host that provides the one or more APIs 710 to one or more software programs 702.

[0052] In at least one embodiment, a processor executing or using one or more software programs 702 invokes, uses, executes, or otherwise implements one or more APIs 710 to allocate, access, and / or otherwise manage memory 714 used by software programs 702. In at least one embodiment, one or more software programs 702 use one or more APIs 710 to allocate, access, and otherwise manage memory 714 used by one or more portions of the software programs 702 to perform one or more cryptographic operations described herein. In at least one embodiment, the software programs 702 may request a neural network and / or other described systems and / or software to perform functions 712 provided, in one embodiment, by one or more APIs 710.

[0053] In at least one embodiment, API 710 is an API for facilitating parallel computing, and in at least one embodiment, for facilitating one or more cryptographic operations. In at least one embodiment, API 710 is any other API further described herein. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime.In at least one embodiment, a driver (e.g., driver / runtime 704) is comprised of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 712 of an API 710 during the loading and execution of one or more portions of a software program 702. In at least one embodiment, a runtime 704 is comprised of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 712 of an API 710 during the execution of a software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or a runtime 704 to perform one or more cryptographic operations 716.In at least one embodiment, one or more described cryptographic engines and / or modules use one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform one or more cryptographic operations 716, which may include the encryption and / or decryption of data, information, parameters, data structures, files, compressed files, and the like.

[0054] Fig. 8 shows an encryption process 800 in accordance with at least one embodiment. In at least one embodiment, the encryption process 800 is implemented by one or more described computer system environments, such as one or more computer system environments 100-700 and / or one or more systems of Fig. 1-7.

[0055] In at least one embodiment, the particular implementation of the technologies disclosed herein is a matter of choice, depending on the performance and other requirements of one or more computing devices. Accordingly, in at least one embodiment, the logical operations described herein, also referred to as acts, are referred to as states, operations, structural devices, or modules. In at least one embodiment, these states, operations, structural devices, acts, and modules may be implemented in hardware, software, firmware, special-purpose digital logic, and any combination thereof. In at least one embodiment, more or fewer operations may be performed than illustrated in the figures and described herein. In at least one embodiment, these operations may also be performed in a different order than described herein.At least in one embodiment, it is also to be understood that the methods described herein may be terminated at any time and need not be performed in their entirety.

[0056] In at least one embodiment, some or all of the operations of the processes / methods described herein and / or substantially equivalent operations may be performed by executing computer-readable instructions embodied on computer storage media. In at least one embodiment, the term "computer-readable instructions," "computer-executable instructions," and variations thereof, as used in the specification and claims, is broadly defined herein to include routines, applications, application modules, program modules, system modules, programs, components, data structures, algorithms, and so forth.In at least one embodiment, computer-readable instructions may be implemented on various system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, distributed computing systems, personal computers, portable computing devices, programmable consumer electronics, combinations thereof, and so forth.

[0057] Thus, in at least one embodiment, the logical operations described herein should be implemented (1) as a sequence of computer-implemented acts or program modules, such as one or more cryptography engines running on a computer system, and / or (2) as interconnected machine logic circuits or circuit modules within the computer system. In at least one embodiment, the implementation is a matter of choice depending on the performance and other requirements of a computer system. Accordingly, in at least one embodiment, the logical operations described herein are referred to as states, operations, structural devices, acts, or modules. In at least one embodiment, these states, operations, structural devices, acts, and modules may be implemented in software, firmware, special-purpose digital logic, and any combination thereof.

[0058] In at least one embodiment, information is obtained at 802. In at least one embodiment, the information comprises data. In at least one embodiment, the information comprises parameters. In at least one embodiment, the information comprises parameters from at least one neural network. In at least one embodiment, the information is obtained in a data structure. In at least one embodiment, the information is obtained from a file. In at least one embodiment, the information is obtained in an archive file. In at least one embodiment, the archive file comprises one or more parameters, such as one or more parameters from one or more neural networks. In at least one environment, the information comprises an indicator of an encryption algorithm.In at least one embodiment, the information includes a specifier, such as a flag, a binary value, or other indicator, indicating that the information should be encrypted. In at least one embodiment, the information is obtained by a system and stored in volatile memory, at least temporarily. In at least one embodiment, the information is obtained by a system and stored in protected volatile memory, such as encrypted volatile memory. In at least one embodiment, all of the volatile memory in which the information is stored is encrypted. In at least one embodiment, only a portion of the volatile memory in which the information is stored is encrypted.

[0059] In at least one embodiment, at 804, the information is analyzed to determine whether the information is to be encrypted. In at least one embodiment, determining whether the information is to be encrypted comprises analyzing the information to determine whether the information includes a specifier indicating that the information is to be encrypted. In at least one embodiment, if the information is not to be encrypted, a system performing the encryption process 800 enters a steady state waiting for additional information to process. In at least one embodiment, if the information is to be encrypted, the information is analyzed to determine 806 whether the information includes an indication of an encryption algorithm.

[0060] In at least one embodiment, at 806, if the information includes the encryption algorithm indicator, at 808 the indicator is used to locate an encryption algorithm that has an associated indicator that matches the indicator included in the information. In at least one embodiment, the encryption algorithm is stored in protected storage, such as protected volatile or non-volatile memory. In at least one embodiment, the encryption algorithm is stored in encrypted storage, such as encrypted volatile or non-volatile memory.

[0061] In at least one embodiment, at 810, the encryption algorithm located using the indicator comprising the information and the indicator associated with the encryption algorithm is used to encrypt the information. In at least one embodiment, the protection of the encrypted information is further enhanced by associating a key with the encrypted information. In at least one embodiment, the key is a user's key. In at least one embodiment, to decrypt the encrypted information, the encryption algorithm and the key are required to decrypt the encrypted information.In at least one embodiment, to decrypt the encrypted information, the encryption algorithm, which is located using its associated identifier, and the key are required to decrypt the encrypted information.

[0062] In at least one embodiment, encrypted information is disseminated at 812. In at least one embodiment, the encrypted information is distributed to a user and / or one or more systems to use the encrypted information after decryption. In at least one embodiment, the encrypted information includes metadata comprising the indicator associated with the encryption algorithm used to encrypt the information. In at least one embodiment, the encryption algorithm is decryptable by software and / or hardware having access to an encryption algorithm used to encrypt the information.The software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information by searching for the encryption algorithm that has an associated indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encryption algorithm is decryptable only by software and / or hardware that has access to an encryption algorithm used to encrypt the encrypted information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information.

[0063] In at least one embodiment, at 814, if the information to be encrypted does not include an indication, an indicator is selected. In at least one embodiment, this indicator corresponds to an encryption algorithm with an associated similar indicator. In at least one embodiment, the indicator is selected from a plurality of indicators, each corresponding to an associated encryption algorithm. In at least one embodiment, the indicator is randomly selected from a plurality of indicators. In at least one embodiment, the plurality of indicators, each corresponding to an associated encryption algorithm, is listed in a lookup table. In at least one embodiment, the selected indicator is selected from the lookup table. In at least one embodiment, the selected indicator is randomly selected from the lookup table.In at least one embodiment, the encryption algorithm lookup table provides a mapping of encryption algorithm indicators to encryption algorithms. In at least one embodiment, the cryptography engine maps encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APls map encryption algorithm indicators to encryption algorithms.

[0064] In at least one embodiment, at 816, an encryption algorithm is located based on a selected indicator. In at least one embodiment, the selected indicator is used to query system memory for an encryption algorithm that has an associated indicator that matches the selected indicator.

[0065] In at least one embodiment, at 818, the encryption algorithm located using the indicator is used to encrypt the information.

[0066] In at least one embodiment, encrypted information is distributed at 820. In at least one embodiment, the encrypted information is distributed to a user and / or one or more systems to use the encrypted information once decrypted. In at least one embodiment, the encrypted information includes metadata comprising the indicator associated with the encryption algorithm used to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware having access to an encryption algorithm used to encrypt the information.The software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information by searching for the encryption algorithm that has an associated indicator that corresponds to the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to an encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information.

[0067] Fig.9 shows an encryption process 900 in accordance with at least one embodiment. In at least one embodiment, the encryption process 900 is implemented by one or more described computer system environments, such as one or more computer system environments 100-700 and / or one or more systems of Fig. 1-7.

[0068] In at least one embodiment, information is obtained at 902. In at least one embodiment, the information comprises data. In at least one embodiment, the information comprises parameters. In at least one embodiment, the information comprises parameters from at least one neural network. In at least one embodiment, the information is obtained in a data structure. In at least one embodiment, the information is obtained from a file. In at least one embodiment, the information is obtained in an archive file. In at least one embodiment, the archive file comprises one or more parameters, such as one or more parameters from one or more neural networks. In at least one environment, the information comprises an indication of a salt.In at least one embodiment, the information includes a specifier, such as a flag, a binary value, or other indicator, indicating that the information should be encrypted. In at least one embodiment, the information is obtained by a system and stored in volatile memory, at least temporarily. In at least one embodiment, the information is obtained by a system and stored in protected volatile memory, such as encrypted volatile memory. In at least one embodiment, all of the volatile memory in which the information is stored is encrypted. In at least one embodiment, only a portion of the volatile memory in which the information is stored is encrypted.

[0069] In at least one embodiment, at 904, the information is analyzed to determine whether the information is to be encrypted. In at least one embodiment, determining whether the information is to be encrypted comprises analyzing the information to determine whether the information includes a specifier indicating that the information is to be encrypted. In at least one embodiment, if the information is not to be encrypted, a system performing the encryption process 900 enters a steady state waiting for additional information to process. In at least one embodiment, if the information is to be encrypted, the information is analyzed to determine 906 whether the information includes an indication of a salt.

[0070] In at least one embodiment, at 906, if the information includes the indicator of the salt, the indicator is used to locate a salt having an associated indicator that matches the indicator included in the information. In at least one embodiment, the salt is stored in protected storage, such as protected volatile or non-volatile memory. In at least one embodiment, the salt is stored in encrypted storage, such as encrypted volatile or non-volatile memory. In at least one embodiment, a plurality of salts may be stored, and each of the plurality of salts includes an associated indication.

[0071] In at least one embodiment, at 910, the salt located using the indicator comprising the information and the indicator associated with the salt is combined with an encryption algorithm to generate an encryption algorithm modified by the salt. In at least one embodiment, the salt is a random value. In at least one embodiment, a salt is an input to an encryption algorithm. In at least one embodiment, the salt is used to increase the amount of work required to perform a brute-force attack against information encrypted with the encryption algorithm that processes the salt as input. In at least one embodiment, the encryption algorithm modified by the salt is used to encrypt the information and generate encrypted information.In at least one embodiment, the protection of the encrypted information is further enhanced by associating a key with the encrypted information. In at least one embodiment, the key is a user key. In at least one embodiment, the encryption algorithm, the salt, and the key are required to decrypt the encrypted information. In at least one embodiment, the encryption algorithm, modified by the salt, and the key are required to decrypt the encrypted information.

[0072] In at least one embodiment, encrypted information is disseminated at 912. In at least one embodiment, the encrypted information is distributed to a user and / or one or more systems to use the encrypted information once decrypted. In at least one embodiment, the encrypted information includes metadata comprising the indicator associated with the salt used to modify the encryption algorithm employed to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware having access to an encryption algorithm and salt used to encrypt the information.The software and / or hardware uses the indicator associated with the encrypted information to locate a salt by searching for the salt that has a corresponding indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to the salt and the encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the salt used to encrypt the information.

[0073] In at least one embodiment, at 914, if the information to be encrypted does not include an indicator, an indicator is selected. In at least one embodiment, this indicator corresponds to a salt with an associated similar indicator. In at least one embodiment, the indicator is selected from a plurality of indicators, each corresponding to an associated salt. In at least one embodiment, the indicator is randomly selected from a plurality of indicators. In at least one embodiment, the plurality of indicators, each corresponding to an associated salt, is listed in a lookup table. In at least one embodiment, the selected indicator is selected from the lookup table. In at least one embodiment, the selected indicator is randomly selected from the lookup table.

[0074] In at least one embodiment, at 916, a salt is located based on a selected indicator. In at least one embodiment, the selected indicator is used to query system memory for a salt that has an associated indicator that matches the selected indicator.

[0075] In at least one embodiment, at 918, the salt located using the indicator is used with an encryption algorithm to encrypt information.

[0076] In at least one embodiment, at 920, encrypted information is disseminated. In at least one embodiment, the encrypted information is distributed to a user and / or one or more systems to use the encrypted information once decrypted. In at least one embodiment, the encrypted information includes metadata comprising the indicator associated with the salt used to modify the encryption algorithm employed to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware having access to an encryption algorithm and salt used to encrypt the information.The software and / or hardware uses the indicator associated with the encrypted information to locate a salt by searching for the salt that has a corresponding indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to the salt and the encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the salt used to encrypt the information.

[0077] Fig.10 shows a decryption process 1000 in accordance with at least one embodiment. In at least one embodiment, the decryption process 1000 is implemented by one or more described computer system environments, such as one or more computer system environments 100-700 and / or one or more systems of Fig. 1-7.

[0078] In at least one embodiment, encrypted information is obtained at 1002. In at least one embodiment, the encrypted information comprises encrypted data. In at least one embodiment, the encrypted information comprises encrypted parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters that are confidential neural network parameters of a trained neural network model. In at least one embodiment, the confidential neural network parameters remain encrypted and hidden from a neural network system and / or user that uses the confidential neural network parameters.

[0079] In at least one embodiment, at 1004, an indicator associated with the encrypted information is determined. In at least one embodiment, the indicator associated with the encrypted information is determined from metadata of the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information that is separate from the encrypted information. In at least one embodiment, the other information is obtained separately from the encrypted information.

[0080] In at least one embodiment, an encryption algorithm is located at 1006. In at least one embodiment, the encryption algorithm is located using the indicator associated with the encryption information. In at least one embodiment, the encryption algorithm is located by reference to a lookup table comprising one or more indicators. In at least one embodiment, each of the one or more indicators of the lookup table includes an associated reference to an encryption algorithm. In at least one embodiment, the encryption algorithm may be retrieved from a computer-implemented memory based on using the indicator associated with the encryption information to locate the encryption algorithm.

[0081] In at least one embodiment, a user key is obtained at 1008. In at least one embodiment, the user key has been used in combination with an encryption algorithm to encrypt the encrypted information. In at least one embodiment, the user key is obtained from a user. In at least one embodiment, the user key is obtained from a system, software, and / or hardware that provided the encrypted information.

[0082] In at least one embodiment, at 1010, the localized encryption algorithm is used to decrypt the encrypted information. In at least one embodiment, the localized encryption algorithm and the user key are used to decrypt the encrypted information. In at least one embodiment, a system that uses the localized encryption algorithm to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, a system that uses the localized encryption algorithm and the user key to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users.In at least one embodiment, the decrypted information is disclosed only to a system that uses the decrypted information. In at least one embodiment, the decrypted information is disclosed only to a neural network that uses the decrypted information. In at least one embodiment, encrypted information is stored in a protected computer-implemented memory, such as an encrypted volatile and / or non-volatile memory.

[0083] Fig. 11 shows a decryption process 1100 in accordance with at least one embodiment. In at least one embodiment, the decryption process 1100 is implemented by one or more described computer system environments, such as one or more computer system environments 100-700 and / or one or more systems of Fig. 1-7.

[0084] In at least one embodiment, encrypted information is obtained at 1102. In at least one embodiment, the encrypted information comprises encrypted data. In at least one embodiment, the encrypted information comprises encrypted parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters that are confidential neural network parameters of a trained neural network model. In at least one embodiment, the confidential neural network parameters remain encrypted and hidden from a neural network system and / or user that uses the confidential neural network parameters.

[0085] In at least one embodiment, at 1104, an indicator associated with the encrypted information is determined. In at least one embodiment, the indicia associated with the encrypted information is determined from metadata of the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other indicia associated with the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information that is separate from the encrypted information. In at least one embodiment, the other information is obtained separately from the encrypted information.

[0086] In at least one embodiment, a salt is located at 1106. In at least one embodiment, the salt is located using the indicator associated with the encrypted information. In at least one embodiment, the salt is located by reference to a lookup table comprising one or more indicators. In at least one embodiment, each of the one or more indicators of the lookup table comprises an associated reference to a salt. In at least one embodiment, a salt may be retrieved from a computer-implemented memory based on using the indicator associated with the salt to locate the salt.

[0087] In at least one embodiment, a user key is obtained at 1108. In at least one embodiment, the user key was used in combination with an encryption algorithm to encrypt the encrypted information. In at least one embodiment, the user key is obtained from a user. In at least one embodiment, the user key is obtained from a system, software, and / or hardware that provided the encrypted information.

[0088] In at least one embodiment, at 1110, the localized salt is used in combination with an encryption algorithm to decrypt the encrypted information. In at least one embodiment, the localized salt is used in combination with an encryption algorithm and the user key to decrypt the encrypted information. In at least one embodiment, a system that uses the localized salt in combination with an encryption algorithm to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, a system that uses the localized salt in combination with an encryption algorithm and the user key to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users.In at least one embodiment, the decrypted information is disclosed only to a system that uses the decrypted information. In at least one embodiment, the decrypted information is disclosed only to a neural network that uses the decrypted information. In at least one embodiment, the encrypted information is stored in a protected computer-implemented memory, such as an encrypted volatile and / or non-volatile memory. Data center

[0089] Fig. 12 illustrates an exemplary data center 1200 in accordance with at least one embodiment. In at least one embodiment, the data center 1200 includes, without limitation, a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0090] In at least one embodiment, as in Fig.12, the data center infrastructure layer 1210 may include a resource orchestrator 1212, clustered compute resources 1214, and node compute resources (“Node CRs”) 1216(1)-1216(N), where “N” represents any positive integer. In at least one embodiment, the node CRs 1216(1)-1216(N) may include any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), data processing units ("DPUs") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or hard disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more node CRs among the node CRs 1216(1)-1216(N) may be a server that has one or more of the computing resources listed above.

[0091] In at least one embodiment, the grouped computing resources 1214 may include separate groupings of node CRs housed in one or more racks (not shown), or multiple racks housed in data centers in different geographic locations (also not shown). Separate groupings of node CRs within the grouped computing resources 1214 may include grouped computing, networking, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0092] In at least one embodiment, resource orchestrator 1212 may configure or otherwise control one or more node CRs 1216(1)-1216(N) and / or clustered computing resources 1214. In at least one embodiment, resource orchestrator 1212 may include a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource orchestrator 1212 may include hardware, software, or a combination thereof.

[0093] In at least one embodiment, as in Fig.12, the framework layer 1220 includes, without limitation, a job scheduler 1232, a configuration manager 1234, a resource manager 1236, and a distributed file system 1238. In at least one embodiment, the framework layer 1220 may include a framework for supporting the software 1252 of the software layer 1230 and / or one or more applications 1242 of the application layer 1240. In at least one embodiment, the software 1252 or the application(s) 1242 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure.In at least one embodiment, the framework layer 1220 may be some type of free and open-source software web application framework such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 1238 for processing large amounts of data (e.g., "Big Data"). In at least one embodiment, the job scheduler 1232 may include a Spark driver to facilitate the scheduling of workloads supported by different layers of the data center 1200. In at least one embodiment, the configuration manager 1234 may be capable of configuring different layers such as the software layer 1230 and the framework layer 1220, which include Spark and the distributed file system 1238 to support the processing of big data.In at least one embodiment, resource manager 1236 may be capable of managing clustered or grouped computing resources allocated to support distributed file system 1238 and job scheduler 1232. In at least one embodiment, the clustered or grouped computing resources may include clustered computing resource 1214 in data center infrastructure layer 1210. In at least one embodiment, resource manager 1236 may be coordinated with resource orchestrator 1212 to manage these allocated or assigned computing resources.

[0094] In at least one embodiment, the software 1252 included in software layer 1230 may include software used by at least portions of node CRs 1216(1)-1216(N), clustered computing resources 1214, and / or distributed file system 1238 of framework layer 1220. One or more types of software may include, but are not limited to, Internet website search software, email virus scanning software, database software, and streaming video content software.

[0095] In at least one embodiment, the application(s) 1242 included in the application layer 1240 may include one or more types of applications used by at least portions of the node CRs 1216(1)-1216(N), clustered computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. At least one or more types of applications may include, without limitation, CUDA applications.

[0096] In at least one embodiment, any configuration manager 1234, resource manager 1236, and resource orchestrator 1212 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve an operator of a data center 1200 from potentially making poor configuration decisions and potentially avoiding underutilized and / or poorly performing sections of a data center.

[0097] In at least one embodiment, one or more systems and / or other hardware / software included in Fig.12 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 12 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein. Computer-aided systems

[0098] The following figures illustrate, without limitation, exemplary computer systems that may be used to implement at least one embodiment.

[0099] Fig.13 shows a processing system 1300 in accordance with at least one embodiment. In at least one embodiment, the processing system 1300 includes one or more processors 1302 and one or more graphics processors 1308, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system with a large number of processors 1302 or processor cores 1307. In at least one embodiment, the processing system 1300 is a processing platform integrated into a system-on-a-chip ("SoC") integrated circuit for use in mobile, portable, or embedded devices. In at least one embodiment, a processor core 1307 is referred to as a compute unit.

[0100] In at least one embodiment, processing system 1300 may include or be integrated with a server-based gaming platform, a game console, a media console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, processing system 1300 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing device 1300 may also include, be coupled to, or integrated with a wearable device, such as a wearable device in the form of a smart watch, smart glasses, an augmented reality device, or a virtual reality device.In at least one embodiment, processing system 1300 is a device for a television or set-top box that includes one or more processors 1302 and a graphical interface generated by one or more graphics processors 1308.

[0101] In at least one embodiment, one or more processors 1302 each include one or more processing cores 1307 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 1307 is configured to process a particular instruction set 1309. In at least one embodiment, the instruction set 1309 may enable Complex Instruction Set Computing ("CISC"), Reduced Instruction Set Computing ("RISC"), or Very Long Instruction Word ("VLIW") computing. In at least one embodiment, the processor cores 1307 may each process a different instruction set 1309, which may include instructions that facilitate emulation of other instruction sets.In at least one embodiment, the processor core 1307 may also include other processing devices, such as a digital signal processor ("DSP").

[0102] In at least one embodiment, processor 1302 includes a cache 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache is shared by various components of processor 1302. In at least one embodiment, processor 1302 also uses an external cache (e.g., a Level 3 ("L3") cache or Last Level Cache ("LLC")) (not shown), which may be shared by processor cores 1307 using known cache coherence techniques. In at least one embodiment, a register file 1306 is additionally included in processor 1302, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and an instruction pointer register).In at least one embodiment, register file 1306 may include general-purpose registers or other registers.

[0103] In at least one embodiment, one or more processors 1302 are coupled to one or more interface buses 1310 to communicate communication signals, such as address, data, or control signals, between processor 1302 and other components in processing system 1300. In at least one embodiment, interface bus 1310 may be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, interface bus 1310 is not limited to a DMI bus and may include one or more Peripheral Component Interconnect (e.g., "PCI," PCI Express ("PCIe")) buses, memory interconnects, or other types of interface buses. In at least one embodiment, processor(s) 1302 include an integrated memory controller 1316 and a memory controller hub 1330.In at least one embodiment, memory controller 1316 facilitates communication between a memory device and other components of processing system 1300, while platform control hub ("PCH") 1330 establishes connections to input / output ("I / O") devices via a local I / O bus. In at least one embodiment, one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for processors.

[0104] In at least one embodiment, memory device 1320 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or other memory device having suitable performance to serve as processor memory. In at least one embodiment, memory device 1320 may operate as system memory for processing system 1300 to store data 1322 and instructions 1321 for use when one or more processors 1302 are executing an application or process. In at least one embodiment, memory controller 1316 is also coupled to an optional external graphics processor 1312 that can communicate with one or more graphics processors 1308 in processors 1302 to perform graphics and media operations.In at least one embodiment, a display device 1311 may be connected to the processor(s) 1302. In at least one embodiment, the display device 1311 may comprise one or more internal display devices, for example, in a mobile electronic device or a laptop, or an external display device connected via an interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1311 may comprise a head-mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications.

[0105] In at least one embodiment, the storage control hub 1330 enables the connection of peripherals to the storage device 1320 and the processor 1302 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, among others, an audio controller 1346, a network interface 1334, a firmware interface 1328, a wireless transceiver 1326, touch sensors 1325, and a storage device 1324 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1324 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, the touch sensors 1325 can include touchscreen sensors, pressure sensors, or fingerprint sensors.In at least one embodiment, wireless transceiver 1326 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a cellular network transceiver such as a 3G, 4G, or Long Term Evolution ("LTE") transceiver. In at least one embodiment, firmware interface 1328 enables communication with system firmware and may, for example, be a Unified Extensible Firmware Interface ("UEFI"). In at least one embodiment, network controller 1334 may enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1310. In at least one embodiment, audio controller 1346 is a multi-channel high-definition audio controller.In at least one embodiment, the processing system 1300 includes an optional I / O controller 1340 for connecting legacy devices (e.g., Personal System 2 ("PS / 2")) to the processing system 1300. In at least one embodiment, the platform control hub 1330 may also be connected to one or more Universal Serial Bus ("USB") controllers 1342 that connect input devices, such as keyboard and mouse combinations 1343, a camera 1344, or other USB input devices.

[0106] In at least one embodiment, an instance of the memory controller 1316 and the memory controller hub 1330 may be integrated into a discrete external graphics processor, such as the external graphics processor 1312. In at least one embodiment, the platform controller hub 1330 and / or the memory controller 1316 may be external to one or more processors 1302. For example, in at least one embodiment, the processing system 1300 may include an external memory controller 1316 and a platform controller hub 1330, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with the processor(s) 1302.

[0107] In at least one embodiment, one or more systems and / or other hardware / software included in Fig.13 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 13 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0108] Fig.14 shows a computer system 1400 in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 may be a system of interconnected devices and components, a SOC, or a combination thereof. In at least one embodiment, the computer system 1400 is configured with a processor 1402, which may include execution units for executing an instruction. In at least one embodiment, the computer system 1400 may include, without limitation, a component such as the processor 1402 to employ execution units including logic for performing algorithms for processing data.In at least one embodiment, computer system 1400 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including personal computers with other microprocessors, technical workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1400 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical interfaces may also be used.

[0109] In at least one embodiment, computer system 1400 may be used in other devices such as handheld devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions.

[0110] In at least one embodiment, computer system 1400 may include, without limitation, a processor 1402, which may include, without limitation, one or more execution units 1408 that may be configured to execute a Compute Unified Device Architecture ("CUDA") program (CUDA® is developed by NVIDIA Corporation of Santa Clara, CA). In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system 1400 is a desktop or server system having a processor. In at least one embodiment, computer system 1400 may be a multiprocessor system.In at least one embodiment, processor 1402 may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor. In at least one embodiment, processor 1402 may be connected to a processor bus 1410 that may transmit data signals between processor 1402 and other components in computer system 1400.

[0111] In at least one embodiment, processor 1402 may include, without limitation, an internal Level 1 ("L1") cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may be external to processor 1402. In at least one embodiment, processor 1402 may also include a combination of both internal and external caches. In at least one embodiment, a register file 1406 may store different data types in various registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0112] In at least one embodiment, execution unit 1408, which includes, without limitation, logic for performing integer and floating-point operations, is also located in processor 1402. Processor 1402 may also include microcode read-only memory ("ROM") ("ucode") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1408 may include logic for handling a packed instruction set 1409. In at least one embodiment, by including a packed instruction set 1409 in an instruction set of a general-purpose processor 1402, along with associated instruction execution circuitry, operations used by many multimedia applications can be performed using packed data in a general-purpose processor 1402.In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across a processor's data bus to perform one or more operations on one data element at a time.

[0113] In at least one embodiment, execution unit 1408 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1400 may include, without limitation, a memory 1420. In at least one embodiment, memory 1420 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1420 may store instruction(s) 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0114] In at least one embodiment, a system logic chip may be connected to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip may include, without limitation, a memory control hub ("MCH") 1416, and the processor 1402 may communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 may provide a high-bandwidth memory path 1418 to the memory 1420 for storing instructions and data, as well as for storing graphics instructions, data, and textures. In at least one embodiment, the MCH 1416 may route data signals between the processor 1402, the memory 1420, and other components of the computer system 1400, and may bridge data signals between the processor bus 1410, the memory 1420, and a system I / O 1422.In at least one embodiment, the system logic chip may provide a graphics port for connection to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to memory 1420 via a high-bandwidth memory path 1418, and the graphics / video card 1412 may be coupled to the MCH 1416 via an accelerated graphics port (AGP) connection 1414.

[0115] In at least one embodiment, computer system 1400 may use system I / O 1422, which is a proprietary hub interface, to connect MCH 1416 to I / O Controller Hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1420, a chipset, and processor 1402. Examples may include, but are not limited to, a firmware hub (“Flash BIOS”) 1428, a wireless transceiver 1426, a data store 1424, a legacy I / O controller 1423 with a user input interface 1425 and a keyboard interface, a serial expansion port 1427, such as USB, and a network controller 1434.The data storage 1424 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0116] In at least one embodiment, Fig. 14 a system comprising interconnected hardware devices or "chips." In at least one embodiment, Fig. 14 show an exemplary SoC. In at least one embodiment, the Fig. 14 may be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of system 1400 are interconnected using Compute Express Link ("CXL") interconnects.

[0117] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 14 are used to provide an application programming interface (API), such as for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 14 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0118] Fig.15 shows a system 1500 in accordance with at least one embodiment. In at least one embodiment, the system 1500 is an electronic device employing a processor 1510. In at least one embodiment, the system 1500 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premises or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0119] In at least one embodiment, system 1500 may include, without limitation, a processor 1510 communicatively coupled to any number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled via a bus or interface, such as an I2C bus, a System Management Bus ("SMBus"), a Low Pin Count Bus ("LPC"), a Serial Peripheral Interface ("SPI"), a High Definition Audio Bus ("HDA"), a Serial Advance Technology Attachment Bus ("SATA"), a USB bus (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter Bus ("UART"). In at least one embodiment, Fig. 15 a system comprising interconnected hardware devices or "chips." In at least one embodiment, Fig. 15 show an exemplary SoC. In at least one embodiment, the Fig.15 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 15 interconnected using CXL connections.

[0120] In at least one embodiment, Fig.15 a display 1524, a touchscreen 1525, a touchpad 1530, a near-field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, an express chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1522, a DSP 1560, a solid-state disk (“SSD”) or hard disk (“HDD”) 1520, a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (“GPS”) 1555, a camera (“USB 3.0 camera”) 1554, such as a USB 3.0 camera, or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1515, implemented, for example, in the LPDDR3 standard. These components can be implemented in any suitable manner.

[0121] In at least one embodiment, other components may be communicatively coupled to the processor 1510 via the components described above. In at least one embodiment, an accelerometer 1541, an ambient light sensor ("ALS") 1542, a compass 1543, and a gyroscope 1544 may be communicatively coupled to the sensor hub 1540. In at least one embodiment, a thermal sensor 1539, a fan 1537, a keyboard 1536, and a touchpad 1530 may be communicatively coupled to the EC 1535. In at least one embodiment, a speaker 1563, a headset 1564, and a microphone ("mic") 1565 may be communicatively coupled to an audio unit ("audio codec and class d amp") 1562, which in turn may be communicatively coupled to the DSP 1560. In at least one embodiment, the audio unit 1562 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1557 may be communicatively coupled to the WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and the Bluetooth unit 1552, as well as the WWAN unit 1556, may be implemented in a Next Generation Form Factor ("NGFF").

[0122] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 15 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig.15 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0123] Fig.16 shows an example integrated circuit 1600 in accordance with at least one embodiment. In at least one embodiment, the example integrated circuit 1600 is a SoC that can be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs, DPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I2S / I2C controller 1640.In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of the following interfaces: a High Definition Multimedia Interface ("HDMI") controller 1650 and a Mobile Industry Processor Interface ("MIPI") display interface 1655. In at least one embodiment, memory may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0124] In at least one embodiment, one or more systems and / or other hardware / software included in Fig.16 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 16 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein.

[0125] Fig.17 shows a computer system 1700 according to at least one embodiment; in at least one embodiment, the computer system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704 communicating via an interconnect connection that may include a memory hub 1705. In at least one embodiment, the memory hub 1705 may be a separate component within a chipset component or integrated with one or more processors 1702. In at least one embodiment, the memory hub 1705 is coupled to an I / O subsystem 1711 via a communication connection 1706. In at least one embodiment, the I / O subsystem 1711 includes an I / O hub 1707 that may enable the computer system 1700 to receive input from one or more input devices 1708.In at least one embodiment, the I / O hub 1707 may enable a display controller, which may be included in one or more processors 1702, to provide outputs to one or more display devices 1710A. In at least one embodiment, one or more display devices 1710A connected to the I / O hub 1707 may comprise a local, internal, or embedded display device.

[0126] In at least one embodiment, processing subsystem 1701 includes one or more parallel processors 1712 connected to storage hub 1705 via a bus or other communication link 1713. In at least one embodiment, communication link 1713 may be any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or a vendor-specific communication interface or structure. In at least one embodiment, one or more parallel processors 1712 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a plurality of integrated core processors or processing units.In at least one embodiment, one or more parallel processors 1712 form a graphics processing subsystem that can output pixels to one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, one or more parallel processors 1712 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1710B.

[0127] In at least one embodiment, a system storage unit 1714 may be connected to the I / O hub 1707 to provide a storage mechanism for the computer system 1700. In at least one embodiment, an I / O switch 1716 may be used to provide an interface enabling connections between the I / O hub 1707 and other components, such as a network adapter 1718 and / or a wireless network adapter 1719 that may be integrated into a platform, and various other devices that may be added via one or more add-in devices 1720. In at least one embodiment, the network adapter 1718 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 1719 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices that include one or more wireless radios.

[0128] In at least one embodiment, the computer system 1700 may include other components not explicitly shown, including USB or other connectors, optical storage devices, video capture devices, and the like, which may also be connected to the I / O hub 1707. In at least one embodiment, communication paths connecting various components in Fig. 17 interconnection may be implemented using any suitable protocols, such as PCI-based protocols (e.g., PCIe) or other bus or point-to-point communication interfaces and / or protocols, such as NVLink high-speed interconnections or interconnection protocols.

[0129] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general processing. In at least one embodiment, components of computer system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, memory hub 1705, processor(s) 1702, and I / O hub 1707 may be integrated into an SoC integrated circuit.In at least one embodiment, the components of computer system 1700 may be integrated into a single chassis to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of computer system 1700 may be integrated into a multi-chip module ("MCM") that may be interconnected with other multi-chip modules to form a modular computer system. In at least one embodiment, I / O subsystem 1711 and display devices 1710B are not included in computer system 1700. In at least one embodiment, one or more parallel processors 1712 include one or more tensor memory accelerator (TMA) units that may transfer blocks of data between global memory and shared memory.In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, for example, from global to shared memory and vice versa.

[0130] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 17 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 17 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig.1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or other operations described herein. Processing systems

[0131] The following figures illustrate, without limitation, exemplary processing systems that may be used to implement at least one embodiment.

[0132] Fig.18 shows an accelerated processing unit ("APU") 1800 in accordance with at least one embodiment. In at least one embodiment, the APU 1800 is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, the APU 1800 may be configured to execute an application program, such as a CUDA program. In at least one embodiment, the APU 1800 includes, without limitation, a core complex 1810, a graphics complex 1840, a fabric 1860, I / O interfaces 1870, memory interfaces 1880, a display controller 1892, and a multimedia engine 1894. In at least one embodiment, the APU 1800 may include, without limitation, any number of core complexes 1810, any number of graphics complexes 1850, any number of display controllers 1892, and any number of multimedia engines 1894 in any combination.For explanatory purposes, multiple instances of the same object are referred to here with reference numbers that identify the object and with parentheses that identify the instance if necessary.

[0133] In at least one embodiment, core complex 1810 is a CPU, graphics complex 1840 is a GPU, and APU 1800 is a processing unit that integrates, without limitation, 1810 and 1840 on a single chip. In at least one embodiment, some tasks may be assigned to core complex 1810 and other tasks to graphics complex 1840. In at least one embodiment, core complex 1810 is configured to execute main control software associated with APU 1800, such as an operating system. In at least one embodiment, core complex 1810 is the main processor of APU 1800, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1810 issues instructions that control the operation of graphics complex 1840.In at least one embodiment, core complex 1810 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1840 may be configured to execute device executable code derived from CUDA source code.

[0134] In at least one embodiment, core complex 1810 includes, without limitation, cores 1820(1)-1820(4) and an L3 cache 1830. In at least one embodiment, core complex 1810 may include, without limitation, any number of cores 1820 and any number and type of caches in any combination. In at least one embodiment, cores 1820 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1820 is a CPU core. In at least one embodiment, core 1820 is referred to as a compute unit.

[0135] In at least one embodiment, each core 1820 includes, without limitation, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch unit 1822 fetches instructions, decodes such instructions, generates micro-operations, and sends separate micro-instructions to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch unit 1822 may concurrently send one micro-instruction to the integer execution engine 1824 and another micro-instruction to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs, without limitation, integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs, without limitation, floating-point and vector operations.In at least one embodiment, fetch unit 1822 forwards microinstructions to a single execution engine that replaces both integer execution engine 1824 and floating point execution engine 1826.

[0136] In at least one embodiment, each core 1820(i), where i is an integer representing a particular instance of core 1820, can access L2 cache 1828(i) that includes core 1820(i). In at least one embodiment, each core 1820 included in core complex 1810(j), where j is an integer representing a particular instance of core complex 1810, is connected to other cores 1820 included in core complex 1810(j) via L3 cache 1830(j) included in core complex 1810(j). In at least one embodiment, the cores 1820 included in core complex 1810(j), where j is an integer representing a particular instance of core complex 1810, may access the entire L3 cache 1830(j) included in core complex 1810(j). In at least one embodiment, L3 cache 1830 may include any number of slices, without limitation.

[0137] In at least one embodiment, graphics complex 1840 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1840 is configured to perform graphics pipeline operations such as drawing instructions, pixel operations, geometric calculations, and other operations related to rendering an image on a display. In at least one embodiment, graphics complex 1840 is configured to perform non-graphics operations. In at least one embodiment, graphics complex 1840 is configured to perform both graphics-related and non-graphics operations.

[0138] In at least one embodiment, the graphics complex 1840 includes, without limitation, any number of compute units 1850 and an L2 cache 1842.

[0139] In at least one embodiment, the compute units 1850 share the L2 cache 1842. In at least one embodiment, the L2 cache 1842 is partitioned. In at least one embodiment, the graphics complex 1840 includes, without limitation, any number of compute units 1850 and any number (including zero) and type of caches. In at least one embodiment, the graphics complex 1840 includes, without limitation, any amount of dedicated graphics hardware.

[0140] In at least one embodiment, each compute unit 1850 includes, without limitation, any number of SIMD units 1852 and a shared memory 1854. In at least one embodiment, each SIMD unit 1852 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1850 can execute any number of thread blocks, but each thread block executes on a single compute unit 1850. In at least one embodiment, a thread block includes, without limitation, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1852 executes a different warp.In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of instructions based on a single set of instructions. In at least one embodiment, predication can be used to deactivate one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp thread. In at least one embodiment, different wavefronts in a thread block can synchronize with each other and communicate via a shared memory 1854.In at least one embodiment, each compute unit 1850 includes one or more thread block clusters, where a thread block cluster may enable programmatic control of locality at a greater granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently across streaming multiprocessors to synchronize and collectively retrieve, exchange, or otherwise use data.

[0141] In at least one embodiment, structure 1860 is a system interconnect that enables data and control transfers between core complex 1810, graphics complex 1840, I / O interfaces 1870, memory interfaces 1880, display controller 1892, and multimedia engine 1894. In at least one embodiment, APU 1800 may include, without limitation, any number and type of system interconnect in addition to or in place of structure 1860 that enables data and control transfers across any number and type of directly or indirectly connected components that may be internal or external to APU 1800. In at least one embodiment, I / O interfaces 1870 are representative of any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.).In at least one embodiment, various types of peripheral devices are coupled to I / O interfaces 1870. In at least one embodiment, peripheral devices coupled to I / O interfaces 1870 may include, without limitation, keyboards, mice, printers, scanners, joysticks or other types of gaming controllers, media recording devices, external storage devices, network interface cards, and so forth.

[0142] In at least one embodiment, the display controller AMD92 displays images on one or more display devices, such as a liquid crystal display ("LCD") device. In at least one embodiment, the multimedia engine 1894 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video processor, an image signal processor, etc. In at least one embodiment, the memory controllers 1880 facilitate data transfer between the APU 1800 and a unified system memory 1890. In at least one embodiment, the core complex 1810 and the graphics complex 1840 share a unified system memory 1890.

[0143] In at least one embodiment, the APU 1800 implements a memory subsystem, including, without limitation, any number and type of memory controllers 1880 and memory devices (e.g., shared memory 1854) that may be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 1800 implements a cache subsystem, including, without limitation, one or more caches (e.g., L2 caches 1828, L3 cache 1830, and L2 cache 1842), each of which may be private or shared among any number of components (e.g., cores 1820, core complex 1810, SIMD units 1852, compute units 1850, and graphics complex 1840).

[0144] In at least one embodiment, one or more systems and / or other hardware / software included in Fig.18 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 18 systems shown are used to implement one or more systems and / or processes as used in connection with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein.

[0145] Fig.19 shows a CPU 1900 in accordance with at least one embodiment. In at least one embodiment, the CPU 1900 is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, the CPU 1900 may be configured to execute an application program. In at least one embodiment, the CPU 1900 is configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 1900 issues instructions that control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1900 may be configured to execute executable code on the host derived from CUDA source code, and an external GPU may be configured to execute executable code on the device derived from such CUDA source code.In at least one embodiment, CPU 1900 includes, without limitation, any number of core complexes 1910, fabric 1960, I / O interfaces 1970, and memory controllers 1980.

[0146] In at least one embodiment, core complex 1910 includes, without limitation, cores 1920(1)-1920(4) and an L3 cache 1930. In at least one embodiment, core complex 1910 may include, without limitation, any number of cores 1920 and any number and type of caches in any combination. In at least one embodiment, cores 1920 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1920 is a CPU core.

[0147] In at least one embodiment, each core 1920 includes, without limitation, a fetch / decode unit 1922, an integer execution engine 1924, a floating-point execution engine 1926, and an L2 cache 1928. In at least one embodiment, the fetch unit 1922 fetches instructions, decodes such instructions, generates micro-operations, and sends separate micro-instructions to the integer execution engine 1924 and the floating-point execution engine 1926. In at least one embodiment, the fetch unit 1922 may concurrently send one micro-instruction to the integer execution engine 1924 and another micro-instruction to the floating-point execution engine 1926. In at least one embodiment, the integer execution engine 1924 executes, without limitation, integer and memory operations. In at least one embodiment, the floating-point execution engine 1926 performs, without limitation, floating-point and vector operations.In at least one embodiment, the fetch unit 1922 forwards microinstructions to a single execution engine that replaces both the integer execution engine 1924 and the floating-point execution engine 1926.

[0148] In at least one embodiment, each core 1920(i), where i is an integer representing a particular instance of core 1920, can access L2 cache 1928(i) that includes core 1920(i). In at least one embodiment, each core 1920 included in core complex 1910(j), where j is an integer representing a particular instance of core complex 1910, is connected to other cores 1920 in core complex 1910(j) via L3 cache 1930(j) included in core complex 1910(j). In at least one embodiment, the cores 1920 included in core complex 1910(j), where j is an integer representing a particular instance of core complex 1910, may access the entire L3 cache 1930(j) included in core complex 1910(j). In at least one embodiment, L3 cache 1930 may include any number of slices, without limitation.

[0149] In at least one embodiment, structure 1960 is a system interconnect that facilitates data and control transfers between core complexes 1910(1)-1910(N) (where N is an integer greater than zero), I / O interfaces 1970, and memory controllers 1980. In at least one embodiment, CPU 1900 may include, without limitation, any amount and type of system interconnection in addition to or in place of structure 1960 that enables data and control transfers via any number and type of directly or indirectly connected components that may be internal or external to CPU 1900. In at least one embodiment, I / O interfaces 1970 are representative of any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interfaces 1970.In at least one embodiment, peripheral devices coupled to I / O interfaces 1970 may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks or other types of gaming controllers, media recording devices, external storage devices, network interface cards, and so forth.

[0150] In at least one embodiment, memory controllers 1980 facilitate data transfer between CPU 1900 and system memory 1990. In at least one embodiment, core complex 1910 and graphics complex 1940 share system memory 1990. In at least one embodiment, CPU 1900 implements a memory subsystem, including, without limitation, any number and type of memory controllers 1980 and memory devices that may be dedicated to a component or shared by multiple components. In at least one embodiment, CPU 1900 implements a cache subsystem, including, without limitation, one or more caches (e.g., L2 caches 1928 and L3 caches 1930), each of which may be dedicated to or shared by any number of components (e.g., cores 1920 and core complex 1910).

[0151] Fig.20 shows an exemplary accelerator integration slice 2090 in accordance with at least one embodiment. As used herein, a "slice" comprises a particular portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines.In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0152] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 19 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 19 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig.1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0153] An effective application address space 2082 in system memory 2014 stores process elements 2083. In one embodiment, the process elements 2083 are stored in response to GPU calls 2081 from applications 2080 executing on the processor 2007. A process element 2083 contains the state of the process for the corresponding application 2080. A work description ("WO") 2084 contained in the process element 2083 may be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 2084 is a pointer to a job request queue in the application's effective address space 2082.

[0154] The graphics acceleration module 2046 and / or individual graphics processing engines may be shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for establishing process state and sending WD 2084 to the graphics acceleration module 2046 to start a job in a virtualized environment may be included.

[0155] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 2046 or an individual graphics processing engine. Because the graphics acceleration module 2046 is owned by a single process, a hypervisor initializes an accelerator integration circuit for an owning partition, and an operating system initializes the accelerator integration circuit for an owning process when the graphics acceleration module 2046 is allocated.

[0156] In operation, a WD fetch unit 2091 in accelerator integration slice 2090 fetches the next WD 2084, which includes an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 2046. The data from WD 2084 may be stored in registers 2045 and used by a memory management unit ("MMU") 2039, interrupt management circuitry 2047, and / or context management circuitry 2048 (see figure). For example, one embodiment of MMU 2039 includes segment / page browsing circuitry for accessing segment / page tables 2086 in operating system virtual address space 2085. Circuitry 2047 may process interrupt events ("INT") 2092 received from graphics acceleration module 2046. When performing graphics operations, an effective address 2093 generated by a graphics processing engine is translated into a real address by the MMU 2039.

[0157] In one embodiment, the same set of registers 2045 is duplicated for each graphics processing engine and / or graphics acceleration module 2046 and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in the accelerator integration slice 2090. Example registers that may be initialized by a hypervisor are listed in Table 1. Table 1 - Registers initialized by the hypervisor 1 Slice control register 2 Real Address (RA) Area pointer for scheduled processes 3 Authority mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry boundary 6 Condition register 7 Logical partition ID 8 Real Address (RA) Pointer for the Accelerator Workload Set (Hypervisor Pointer for the Accelerator Workload Set) 9 Memory description register

[0158] Example registers that can be initialized by an operating system are listed in Table 2. Table 2 - Initialized operating system registers 1 Process and thread identification 2 Effective Address (EA) Context Store / Restore Pointer 3 Virtuelle Adresse (VA) Zeiger für den Beschleunigerauslastungssatz (Zeiger fürden Beschleunigerauslastungssatz) 4 Virtuelle Adresse (VA) Zeiger auf die Speichersegmenttabelle 5 Autoritätsmaske 6 Arbeitsbeschreibung

[0159] In one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or a particular graphics processing engine. It contains all the information a graphics processing engine needs to perform work, or it may be a pointer to a memory location where an application has a command queue of work to be performed.

[0160] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 20 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 20 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0161] Fig. 21A-21B illustrate example graphics processors in accordance with at least one embodiment. In at least one embodiment, each of the example graphics processors may be fabricated using one or more IP cores. In addition to the embodiments shown, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the example graphics processors are intended for use within a SoC.

[0162] Fig. 21A shows an exemplary graphics processor 2110 of an integrated circuit SoC that may be manufactured with one or more IP cores in accordance with at least one embodiment. Fig. 21B shows another exemplary graphics processor 2140 of an integrated circuit (SoC) that may be manufactured using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 2110 is Fig. 21A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2140 is Fig. 21B, a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 2110, 2140 may be a variant of the graphics processor 1610 of Fig. be 16.

[0163] In at least one embodiment, graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D, through 2115N-1, and 2115N). In at least one embodiment, graphics processor 2110 may execute different shader programs via separate logic, such that vertex processor 2105 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2105 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 2115A-2115N use the primitive and vertex data generated by the vertex processor 2105 to generate a framebuffer displayed on a display device. In at least one embodiment, the fragment processor(s) 2115A-2115N are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program as provided in a Direct 3D API.

[0164] In at least one embodiment, graphics processor 2110 additionally includes one or more MMU(s) 2120A-2120B, cache(s) 2125A-2125B, and circuit interconnect(s) 2130A-2130B. In at least one embodiment, one or more MMU(s) 2120A-2120B provide virtual-to-physical address mapping for graphics processor 2110, including vertex processor 2105 and / or fragment processor(s) 2115A-2115N, which may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in one or more cache(s) 2125A-2125B. In at least one embodiment, one or more MMU(s) 2120A-2120B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processors 1605, image processors 1615, and / or video processors 1620 of Fig. 16, so that each processor 1605-1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable the graphics processor 2110 to interface with other IP cores within an SoC, either via an internal bus of the SoC or via a direct connection.

[0165] In at least one embodiment, the graphics processor 2140 includes one or more MMU(s) 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B of the graphics processor 2110 of Fig. 21A. In at least one embodiment, the graphics processor 2140 includes one or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F through 2155N-1, and 2155N) that provide a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader code implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary.In at least one embodiment, the graphics processor 2140 includes an inter-core task manager 2145 acting as a thread dispatcher to distribute execution threads to one or more shader cores 2155A-2155N and a tiling unit 2158 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0166] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 21 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 21 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0167] Fig. 22A shows a graphics core 2200 in accordance with at least one embodiment. In at least one embodiment, the graphics core 2200 may be included in the graphics processor 1610 of Fig. 16. In at least one embodiment, the graphics core 2200 may be a unified shader core 2155A-2155N as shown in Fig. 21B. In at least one embodiment, the graphics core 2200 includes a shared instruction cache 2202, a texture unit 2218, and a cache / shared memory 2220 that are common to the execution resources within the graphics core 2200. In at least one embodiment, the graphics core 2200 may include multiple slices 2201A-2201N or partitions for each core, and a graphics processor may include multiple instances of the graphics core 2200. The slices 2201A-2201N may include support logic including a local instruction cache 2204A-2204N, a thread scheduler 2206A-2206N, a thread dispatcher 2208A-2208N, and a set of registers 2210A-2210N.In at least one embodiment, slices 2201A-2201N may include a set of additional functional units ("AFUs") 2212A-2212N, floating-point units ("FPUs") 2214A-2214N, integer arithmetic logic units ("ALUs") 2216-2216N, address calculation units ("ACUs") 2213A-2213N, double-precision floating-point units ("DPFPUs") 2215A-2215N, and matrix processing units ("MPUs") 2217A-2217N. In at least one embodiment, a graphics core 2200 is also referred to as a compute unit.

[0168] In at least one embodiment, the FPUs 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2215A-2215N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2216A-2216N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, MPUs 2217-2217N may perform a variety of matrix operations to accelerate CUDA programs, including support for accelerated general purpose matrix-matrix multiplication ("GEMM").In at least one embodiment, AFUs 2212A-2212N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0169] Fig. Figure 22B illustrates a general purpose graphics processing unit ("GPGPU") 2230 in accordance with at least one embodiment. In at least one embodiment, GPGPU 2230 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2230 can be configured to allow highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 2230 can be directly connected to other instances of GPGPU 2230 to form a multi-GPU cluster and improve execution time for CUDA programs. In at least one embodiment, GPGPU 2230 includes a host interface 2232 to enable connection to a host processor. In at least one embodiment, host interface 2232 is a PCIe interface.In at least one embodiment, host interface 2232 may be a vendor-specific communications interface or communications structure. In at least one embodiment, GPGPU 2230 receives instructions from a host processor and uses a global scheduler 2234 to distribute the execution threads associated with those instructions among a number of compute clusters 2236A-2236H. In at least one embodiment, compute clusters 2236A-2236H share a cache 2238. In at least one embodiment, cache 2238 may serve as a higher-level cache for caches within compute clusters 2236A-2236H.

[0170] In at least one embodiment, GPGPU 2230 includes memory 2244A-2244B coupled to compute clusters 2236A-2236H via a set of memory controllers 2242A-2242B. In at least one embodiment, memory 2244A-2244B may include various types of memory devices, including DRAM or graphics random access memory, such as synchronous graphics random access memory ("SGRAM"), including double data rate graphics memory ("GDDR").

[0171] In at least one embodiment, the compute clusters 2236A-2236H each include a set of graphics cores, such as the graphics core 2200 of Fig. 22A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, also suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 2236A-2236H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0172] In at least one embodiment, multiple instances of GPGPU 2230 may be configured to operate as a compute cluster. Compute clusters 2236A-2236H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to a GPU interconnect 2240 that enables direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU interconnect 2240 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2230.In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect to send and receive data to other GPGPUs 2230 or parallel processors. In at least one embodiment, multiple GPGPU instances 2230 are located in separate computing systems and communicate via a network interface accessible via host interface 2232. In at least one embodiment, GPU link 2240 may be configured to enable connection to a processor in addition to, or alternatively to, host interface 2232. In at least one embodiment, GPGPU 2230 may be configured to execute a CUDA program.

[0173] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 22 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 22 depicted systems are used to implement one or more systems and / or processes as used in connection with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0174] Fig. Figure 23A illustrates a parallel processor 2300 in accordance with at least one embodiment. In at least one embodiment, various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits ("ASICs"), or FPGAs.

[0175] In at least one embodiment, parallel processor 2300 includes a parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 may be directly connected to other devices. In at least one embodiment, I / O unit 2304 is connected to other devices via a hub or switch interface, such as storage hub 2305. In at least one embodiment, the connections between storage hub 2305 and I / O unit 2304 form a communication link.In at least one embodiment, the I / O unit 2304 is coupled to a host interface 2306 and a memory crossbar 2316, where the host interface 2306 receives commands to perform processing operations and the memory crossbar 2316 receives commands to perform memory operations.

[0176] In at least one embodiment, when host interface 2306 receives a command buffer via I / O unit 2304, host interface 2306 may forward work operations to a front end 2308 for execution of those commands. In at least one embodiment, front end 2308 is coupled to a scheduler 2310 configured to dispatch commands or other work items to a processing array 2312. In at least one embodiment, scheduler 2310 ensures that processing array 2312 is properly configured and in a valid state before dispatching tasks to processing array 2312. In at least one embodiment, scheduler 2310 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2310 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 2312. In at least one embodiment, host software may announce workloads for scheduling on the processing array 2312 via one of several graphics processing doorbells. In at least one embodiment, the workloads may then be automatically distributed across the processing array 2312 by the logic of the scheduler 2310 within a microcontroller that includes the scheduler 2310.

[0177] In at least one embodiment, processing array 2312 may include up to "N" clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N). In at least one embodiment, each cluster 2314A-2314N of processing array 2312 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2310 may allocate work to clusters 2314A-2314N of processing array 2312 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each program or compute type. In at least one embodiment, scheduling may be performed dynamically by scheduler 2310 or may be assisted in part by compiler logic during compilation of program logic configured for execution by processing array 2312.In at least one embodiment, different clusters 2314A-2314N of the processing array 2312 may be allocated for processing different types of programs or for performing different types of computations.

[0178] In at least one embodiment, processing array 2312 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing array 2312 may include logic to perform tasks including filtering video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0179] In at least one embodiment, processing array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 2312 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 2312 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2302 may transfer data from system memory via I / O unit 2304 for processing.In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to system memory.

[0180] In at least one embodiment, when the graphics processing unit 2302 is used to perform graphics processing, the scheduler 2310 may be configured to divide a workload into approximately equal-sized tasks to enable better distribution of graphics processing operations across multiple clusters 2314A-2314N of the processing array 2312. In at least one embodiment, portions of the processing array 2312 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N may be stored in buffers to facilitate transfer of intermediate data between clusters 2314A-2314N for further processing.

[0181] In at least one embodiment, processing array 2312 may receive processing tasks to be executed via scheduler 2310, which receives commands defining processing tasks from frontend 2308. In at least one embodiment, the processing tasks may include indices of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, scheduler 2310 may be configured to retrieve indices corresponding to the tasks or to receive indices from frontend 2308.In at least one embodiment, the front end 2308 may be configured to ensure that the processing array 2312 is placed in a valid state before initiating a workload specified by incoming instruction buffers (e.g., stack buffers, push buffers, etc.).

[0182] In at least one embodiment, each of one or more instances of parallel processing unit 2302 may be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 may be accessed via memory crossbar 2316, which may receive memory requests from processing array 2312 as well as from I / O unit 2304. In at least one embodiment, memory crossbar 2316 may access parallel processor memory 2322 via a memory interface 2318. In at least one embodiment, memory interface 2318 may include multiple partition units (e.g., partition unit 2320A, partition unit 2320B, through partition unit 2320N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 2322.In at least one embodiment, a number of partition units 2320A-2320N is configured to be equal to a number of storage units, such that a first partition unit 2320A has a corresponding first storage unit 2324A, a second partition unit 2320B has a corresponding storage unit 2324B, and an Nth partition unit 2320N has a corresponding Nth storage unit 2324N. In at least one embodiment, a number of partition units 2320A-2320N may not be equal to a number of storage devices.

[0183] In at least one embodiment, memory units 2324A-2324N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units 2324A-2324N may also include 3D stacked memories, including but not limited to high-bandwidth memories ("HBM"). In at least one embodiment, rendering targets, such as frame buffers or texture maps, may be stored across memory units 2324A-2324N so that partition units 2320A-2320N can write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 2322.In at least one embodiment, a local instance of parallel processor memory 2322 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with the local cache memory.

[0184] In at least one embodiment, each of the clusters 2314A-2314N of the processing array 2312 can process data written to any of the processing units 2324A-2324N in the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to transfer an output of each cluster 2314A-2314N to any of the partition units 2320A-2320N or to another cluster 2314A-2314N that can perform additional processing operations on an output. In at least one embodiment, each cluster 2314A-2314N can communicate with the memory interface 2318 via the memory crossbar 2316 to read from or write to various external devices.In at least one embodiment, the memory crossbar 2316 includes a connection to the memory interface 2318 to communicate with the I / O unit 2304, as well as a connection to a local instance of the parallel processor memory 2322, which enables the processing units in the different clusters 2314A-2314N to communicate with system memory or other memory not local to the parallel processing unit 2302. In at least one embodiment, the memory crossbar 2316 may use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0185] In at least one embodiment, multiple instances of the parallel processing unit 2302 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2302 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2302 may include higher-precision floating-point units compared to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 2302 or the parallel processor 2300 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0186] Fig. 23B shows a processing cluster 2394 in accordance with at least one embodiment. In at least one embodiment, the processing cluster 2394 is included in a parallel processing unit. In at least one embodiment, the processing cluster 2394 is one of the processing clusters 2314A-2314N of Fig. 23. In at least one embodiment, the processing cluster 2394 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data ("SIMD") instruction issuance techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread ("SIMT") techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2394.

[0187] In at least one embodiment, the operation of the processing cluster 2394 may be controlled by a pipeline manager 2332, which distributes the processing tasks to the parallel SIMT processors. In at least one embodiment, the pipeline manager 2332 receives instructions from the scheduler 2310 of the Fig. 23 and manages the execution of these instructions via a graphics multiprocessor 2334 and / or a texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included in the processing cluster 2394. In at least one embodiment, the processing cluster 2394 may include one or more instances of the graphics multiprocessor 2334. In at least one embodiment, the graphics multiprocessor 2334 may process data, and a data crossbar 2340 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2332 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2340.

[0188] In at least one embodiment, each graphics multiprocessor 2334 within the processing cluster 2394 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units ("LSUs"), etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline in which new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the computation of various algebraic functions. In at least one embodiment, the same hardware with functional units may be used to perform different operations, and any combination of functional units may be present.

[0189] In at least one embodiment, the instructions transferred to the processing cluster 2394 form a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program with different input data. In at least one embodiment, each thread within a thread group may be assigned to a different engine within the graphics multiprocessor 2334. In at least one embodiment, a thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during the cycles in which that thread group is processing.In at least one embodiment, a thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, if a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2334, processing may occur in consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on the graphics multiprocessor 2334.

[0190] In at least one embodiment, the graphics multiprocessor 2334 includes an internal cache for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2334 may forgo an internal cache and utilize a cache (e.g., L1 cache 2348) within the processing cluster 2394. In at least one embodiment, each graphics multiprocessor 2334 also has access to Level 2 ("L2") caches within partition units (e.g., partition units 2320A-2320N of Fig. 23A) that are shared by all processing clusters 2394 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2334 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2302 can be used as global memory. In at least one embodiment, the processing cluster 2394 includes multiple instances of the graphics multiprocessor 2334, which can share common instructions and data that can be stored in the L1 cache 2348.

[0191] In at least one embodiment, each processing cluster 2394 may include an MMU 2345 configured to translate virtual addresses into physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in the memory interface 2318 of Fig. 23. In at least one embodiment, MMU 2345 includes a set of page table entries ("PTEs") used to map a virtual address to a physical address of a tile, and optionally a cache line index. In at least one embodiment, MMU 2345 may include address translation lookaside buffers ("TLBs") or caches, which may be located in graphics multiprocessor 2334, L1 cache 2348, or processing cluster 2394. In at least one embodiment, a physical address is processed to distribute access locality to surface data to enable efficient interleaving of requests between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0192] In at least one embodiment, processing cluster 2394 may be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, such as determining texture pattern positions, reading texture data, and filtering texture data. In at least one embodiment, the texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2334 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed.In at least one embodiment, each graphics multiprocessor 2334 outputs a processed task to the data crossbar 2340 to provide the processed task to another processing cluster 2394 for further processing via the memory crossbar 2316, or to store the processed task in an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, a pre-raster operations unit ("preROP") 2342 is configured to receive data from the graphics multiprocessor 2334 and forward data to ROP units, which may be arranged with partition units as described herein (e.g., partition units 2320A-2320N of FIG. Fig. 23). In at least one embodiment, PreROP 2342 may perform optimizations for color mixing, organizing pixel color data, and address translations.

[0193] Fig. 23C shows a graphics multiprocessor 2396 in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2396 is the graphics multiprocessor 2334 of Fig. 23B. In at least one embodiment, graphics multiprocessor 2396 is coupled to pipeline manager 2332 of processing cluster 2394. In at least one embodiment, graphics multiprocessor 2396 has an execution pipeline including, among other things, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more GPGPU cores 2362, and one or more LSUs 2366. GPGPU cores 2362 and LSUs 2366 are coupled to cache memory 2372 and shared memory 2370 via a memory and cache interconnect 2368.

[0194] In at least one embodiment, instruction cache 2352 receives a stream of instructions to be executed by pipeline manager 2332. In at least one embodiment, the instructions are cached in instruction cache 2352 and forwarded for execution by instruction unit 2354. In at least one embodiment, instruction unit 2354 may dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 2362. In at least one embodiment, an instruction may access a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2356 may be used to translate addresses in a unified address space into a unique memory address accessible by LSUs 2366.

[0195] In at least one embodiment, register file 2358 provides a set of registers for functional units of graphics multiprocessor 2396. In at least one embodiment, register file 2358 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2362, LSUs 2366) of graphics multiprocessor 2396. In at least one embodiment, register file 2358 is partitioned among individual functional units such that each functional unit is assigned its own section of register file 2358. In at least one embodiment, register file 2358 is partitioned among different thread groups executed by graphics multiprocessor 2396.

[0196] In at least one embodiment, the GPGPU cores 2362 may each include FPUs and / or integer ALUs used to execute instructions of the graphics multiprocessor 2396. The GPGPU cores 2362 may have a similar architecture or differ in architecture. In at least one embodiment, a first portion of the GPGPU cores 2362 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores 2362 includes a double-precision FPU. In at least one embodiment, the FPUs may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2396 may additionally include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or blending pixels.In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed functional logic or special functional logic.

[0197] In at least one embodiment, GPGPU cores 2362 include SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores 2362 can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for Single Program Multiple Data ("SPMD") or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can execute via a single SIMD instruction.For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0198] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network that connects each functional unit of the graphics multiprocessor 2396 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a crossbar interconnect that enables the LSU 2366 to perform load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 may operate at the same frequency as the GPGPU cores 2362, such that data transfer between the GPGPU cores 2362 and the register file 2358 has very low latency. In at least one embodiment, a shared memory 2370 may be used to enable communication between threads executing on functional units within the graphics multiprocessor 2396.For example, in at least one embodiment, cache 2372 may be used as a data cache to cache texture data transferred between functional units and texture unit 2336. In at least one embodiment, shared memory 2370 may also be used as a programmatic cache. In at least one embodiment, threads executing on GPGPU cores 2362 may programmatically store data in shared memory in addition to the automatically cached data stored in cache 2372.

[0199] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to the host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a graphics processor may be integrated on the same package or die as cores and communicate with the cores via a processor bus / interconnect located within a package or die.In at least one embodiment, regardless of how a GPU is connected, the processor cores can assign work to the GPU in the form of sequences of instructions contained in a WD. In at least one embodiment, the GPU then uses special circuitry / logic to efficiently process these instructions.

[0200] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 23 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 23 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0201] Fig. 24 shows a graphics processor 2400 in accordance with at least one embodiment. In at least one embodiment, the graphics processor 2400 includes a ring interconnect 2402, a pipelined front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, the ring interconnect 2402 connects the graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processing cores. In at least one embodiment, the graphics processor 2400 is one of many processors integrated into a multi-core processing system.

[0202] In at least one embodiment, graphics processor 2400 receives batches of commands via ring interconnect 2402. In at least one embodiment, the incoming commands are interpreted by a command streamer 2403 in pipeline front end 2404. In at least one embodiment, graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, command streamer 2403 provides commands to geometry pipeline 2436 for 3D geometry processing commands. In at least one embodiment, command streamer 2403 provides commands to a video front end 2434 coupled to a media engine 2437 for at least some media processing commands.In at least one embodiment, the media engine 2437 includes a video quality engine ("VQE") 2430 for video and image post-processing and a multi-format encoder / decoder ("MFX") engine 2433 for hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate execution threads for threaded execution resources provided by at least one graphics core 2480A.

[0203] In at least one embodiment, graphics processor 2400 includes scalable threaded execution resources with modular graphics cores 2480A-2480N (sometimes referred to as core slices), each having a plurality of sub-cores 2450A-2480N, 2460A-2460N (sometimes referred to as a core slice). In at least one embodiment, graphics processor 2400 may include any number of graphics cores 2480A-2480N. In at least one embodiment, graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, graphics processor 2400 is a low-power processor with a single sub-core (e.g., sub-core 2450A). In at least one embodiment, the graphics processor 2400 includes a plurality of graphics cores 2480A-2480N, each including a group of first sub-cores 2450A-2450N and a group of second sub-cores 2460A-2460N.In at least one embodiment, each subcore in the first subcores 2450A-2450N includes at least a first group of execution units ("EUs") 2452A-2452N and media / texture units 2454A-2454N. In at least one embodiment, each subcore in the second subcores 2460A-2460N includes at least a second group of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each subcore 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources 2470 include a shared cache memory and pixel operation logic.

[0204] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 24 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 24 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0205] Fig. 25 shows a processor 2500 in accordance with at least one embodiment. In at least one embodiment, the processor 2500 may include, without limitation, logic circuitry for executing instructions. In at least one embodiment, the processor 2500 may execute instructions including x86 instructions, ARM instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors employing MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, which are available in both integer and floating-point form, may operate on packed data elements accompanying SIMD and Streaming SIMD Extensions ("SSE") instructions.In at least one embodiment, 128-bit XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond technologies (commonly referred to as "SSEx") may accommodate such packed data operands. In at least one embodiment, processors 2510 may execute instructions to accelerate CUDA programs.

[0206] In at least one embodiment, processor 2500 includes an in-order front-end ("front-end") 2501 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, front-end 2501 may include multiple units. In at least one embodiment, an instruction prefetcher 2526 fetches instructions from memory and passes them to an instruction decoder 2528, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2528 decodes a received instruction into one or more operations referred to as "micro-instructions" or "micro-operations" (also called "microOps" or "uOps").In at least one embodiment, instruction decoder 2528 decomposes the instruction into opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations. In at least one embodiment, a trace cache 2530 may assemble decoded uOps into program-ordered sequences or traces in a uOps queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, a microcode ROM 2532 provides uOps needed to complete an operation.

[0207] In at least one embodiment, some instructions may be converted into a single micro-op, while others may require multiple micro-ops to perform a complete operation. In at least one embodiment, if more than four micro-ops are required to execute an instruction, instruction decoder 2528 may access microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing in instruction decoder 2528. In at least one embodiment, an instruction may be stored in microcode ROM 2532 if a number of micro-ops are required to perform the operation.In at least one embodiment, trace cache 2530 refers to a programmable logic array ("PLA") as an entry point to determine a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2532. In at least one embodiment, after microcode ROM 2532 finishes sequencing micro-ops for an instruction, machine front-end 2501 may resume fetching micro-ops from trace cache 2530.

[0208] In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 2503 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic includes a series of buffers to smooth and reorder the flow of instructions to optimize performance as they traverse a pipeline and are scheduled for execution. The out-of-order execution engine 2503 includes, among other things, an allocator / register renamer 2540, a memory uOps queue 2542, an integer / floating point uOps queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general FP scheduler 2504, and a simple FP scheduler 2506.In at least one embodiment, the fast scheduler 2502, the slow / general floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to herein as "uOps schedulers 2502, 2504, 2506." Allocator / register renamer 2540 allocates machine buffers and resources required by each uOps for execution. In at least one embodiment, allocator / register renamer 2540 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2540 also assigns each uOps an entry in one of two uOps queues, the memory uOps queue 2542 for memory operations and the integer / floating point uOps queue 2544 for non-memory operations, which precede the memory scheduler 2546 and the uOps schedulers 2502, 2504, 2506.In at least one embodiment, schedulers 2502, 2504, 2506 determine the readiness of a uOp to execute based on the readiness of its dependent input register operand sources and the availability of the execution resources required by the uOps to complete their operation. In at least one embodiment, fast scheduler 2502 may create a schedule in each half of the main clock cycle, while slow / general floating-point scheduler 2504 and simple floating-point scheduler 2506 may create one schedule per main clock cycle of the processor. In at least one embodiment, schedulers 2502, 2504, 2506 arbitrate for dispatch ports to schedule uOps for execution.

[0209] In at least one embodiment, execution block 2511 includes, without limitation, an integer register file / bypass network 2508, a floating-point register file / bypass network (“FP register file / bypass network”) 2510, address generation units (“AGUs”) 2512 and 2514, fast ALUs 2516 and 2518, a slow ALU 2520, a floating-point ALU (“FP”) 2522, and a floating-point move unit (“FP move”) 2524. In at least one embodiment, integer register file / bypass network 2508 and floating-point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510.” In at least one embodiment, the AGUSs 2512 and 2514, the fast ALUs 2516 and 2518, the slow ALU 2520, the floating-point ALU 2522, and the floating-point shift unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524."In at least one embodiment, an execution block may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0210] In at least one embodiment, register files 2508, 2510 may be arranged between uOps schedulers 2502, 2504, 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / bypass network 2508 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2510 performs floating-point operations. In at least one embodiment, each of register files 2508, 2510 may include, without limitation, a bypass network that bypasses just-completed results that have not yet been written to the register file or forwards them to new dependent uOps. In at least one embodiment, register files 2508, 2510 may exchange data with each other.In at least one embodiment, the integer register / bypass network 2508 may include, without limitation, two separate register files: one low-order data register file of thirty-two bits and a second high-order data register file of thirty-two bits. In at least one embodiment, the register file / bypass network 2510 may include, without limitation, 128-bit wide entries, since floating-point instructions typically have operands ranging from 64 to 128 bits wide.

[0211] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524 may execute instructions. In at least one embodiment, register files 2508, 2510 store integer and floating-point data operand values ​​required for microinstruction execution. In at least one embodiment, processor 2500 may include, without limitation, any number and combination of execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524. In at least one embodiment, floating-point ALU 2522 and floating-point shift unit 2524 may perform floating-point, MMX, SIMD, AVX, and SSE or other operations. In at least one embodiment, the floating-point ALU 2522 may include, without limitation, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations.In at least one embodiment, instructions involving a floating-point value may be processed using floating-point hardware. In at least one embodiment, ALU operations may be forwarded to the fast ALUs 2516, 2518. In at least one embodiment, the fast ALUs 2516, 2518 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2520, as the slow ALU 2520 may include, without limitation, integer execution hardware for long-latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by the AGUs 2512, 2514.In at least one embodiment, the fast ALU 2516, the fast ALU 2518, and the slow ALU 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2516, the fast ALU 2518, and the slow ALU 2520 can be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2522 and the floating-point shift unit 2524 can be implemented to support a number of operands having bits of different widths. In at least one embodiment, the floating-point ALU 2522 and the floating-point shift unit 2524 can operate with 128-bit packed data operands in conjunction with SIMD and multimedia instructions.

[0212] In at least one embodiment, the uOps schedulers 2502, 2504, 2506 initiate dependent operations before the parent load completes execution. In at least one embodiment where uOps may be speculatively scheduled and executed in the processor 2500, the processor 2500 may also include logic to handle memory misses. In at least one embodiment, when a data load fails in a data cache, there may be dependent operations in the pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks instructions that use incorrect data and reexecutes them. In at least one embodiment, dependent operations may need to be replayed while independent operations are allowed to complete.In at least one embodiment, schedulers and rendering mechanisms of at least one embodiment of a processor may also be configured to intercept instruction sequences for text string comparison operations.

[0213] In at least one embodiment, the term "registers" may refer to onboard memory locations of the processor that may be used as part of instructions to identify operands. In at least one embodiment, the registers may be those that may be used from outside a processor (from a programmer's perspective). In at least one embodiment, the registers may not be limited to a particular circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein.In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, 32-bit integer data is stored in integer registers. A register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0214] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 25 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 25 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0215] Fig. 26 shows a processor 2600 in accordance with at least one embodiment. In at least one embodiment, the processor 2600 includes, without limitation, one or more processor cores ("cores") 2602A-2602N, an integrated memory controller 2614, and an integrated graphics processor 2608. In at least one embodiment, the processor 2600 may include additional cores, up to and including the additional processor core 2602N represented by dashed boxes. In at least one embodiment, each of the processor cores 2602A-2602N includes one or more internal cache units 2604A-2604N. In at least one embodiment, each processor core also has access to one or more shared cache units 2606. In at least one embodiment, one or more processor cores 2602A-2602N are referred to as one or more computing units.

[0216] In at least one embodiment, the internal cache units 2604A-2604N and the shared cache units 2606 represent a cache hierarchy within the processor 2600. In at least one embodiment, the cache units 2604A-2604N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as L2, L3, Level 4 ("L4"), or other cache levels, with the highest cache level prior to external memory classified as LLC. In at least one embodiment, the cache coherence logic maintains coherence between different cache units 2606 and 2604A-2604N.

[0217] In at least one embodiment, the processor 2600 may also include a set of one or more bus control units 2616 and a system agent core 2610. In at least one embodiment, one or more bus control units 2616 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2610 provides management functions for various processor components. In at least one embodiment, the system agent core 2610 includes one or more integrated memory controllers 2614 for managing access to various external storage devices (not shown).

[0218] In at least one embodiment, one or more of the processor cores 2602A-2602N include support for concurrent multi-threading. In at least one embodiment, the system agent core 2610 includes components for coordinating and operating the processor cores 2602A-2602N during multi-threaded processing. In at least one embodiment, the system agent core 2610 may additionally include a power control unit ("PCU") that includes logic and components for regulating one or more power states of the processor cores 2602A-2602N and the graphics processor 2608.

[0219] In at least one embodiment, processor 2600 additionally includes graphics processor 2608 for performing graphics processing operations. In at least one embodiment, graphics processor 2608 couples to shared cache units 2606 and system agent core 2610, which includes one or more integrated memory controllers 2614. In at least one embodiment, system agent core 2610 also includes a display controller 2611 for driving the output of the graphics processor to one or more coupled displays. In at least one embodiment, display controller 2611 may also be a separate module connected to graphics processor 2608 via at least one interconnect, or it may be integrated into graphics processor 2608.

[0220] In at least one embodiment, a ring interconnect 2612 is used to couple internal components of processor 2600. In at least one embodiment, an alternative interconnect may be used, such as a point-to-point connection, a switch connection, or other techniques. In at least one embodiment, graphics processor 2608 is coupled to ring interconnect 2612 via an I / O connection 2613.

[0221] In at least one embodiment, I / O interconnect 2613 represents at least one of several types of I / O interconnects, including a chassis-mounted I / O interconnect that facilitates communication between various processor components and an embedded high-performance memory module 2618, such as an eDRAM module. In at least one embodiment, each of the processor cores 2602A-2602N and the graphics processor 2608 utilize embedded memory modules 2618 as a shared LLC.

[0222] In at least one embodiment, processor cores 2602A-2602N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2602A-2602N are ISA heterogeneous, where one or more processor cores 2602A-2602N execute a common instruction set, while one or more other cores of processor cores 2602A-2602N execute a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores 2602A-2602N are microarchitecturally heterogeneous, where one or more relatively higher-power cores are coupled with one or more lower-power cores. In at least one embodiment, processor 2600 can be implemented on one or more chips or as an integrated circuit (SoC).

[0223] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 26 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 26 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0224] Fig. 27 shows a graphics processor core 2700 in accordance with at least one of the described embodiments. In at least one embodiment, the graphics processor core 2700 is included in a graphics core array. In at least one embodiment, the graphics processor core 2700, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2700 is exemplary of a graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on targeted power and performance levels. In at least one embodiment, each graphics core 2700 may include a fixed functional block 2730 coupled to a plurality of sub-cores 2701A-2701F, also referred to as slices, which include modular blocks of general-purpose and fixed-function logic.

[0225] In at least one embodiment, functional block 2730 includes a geometry / fixed function pipeline 2736 that may be shared by all subcores in graphics processor 2700, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2736 includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages unified return buffers.

[0226] In at least one embodiment, fixed functional block 2730 also includes a graphics SoC interface 2737, a graphics microcontroller 2738, and a media pipeline 2739. Graphics SoC interface 2737 provides an interface between graphics core 2700 and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller 2738 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2700, including thread dispatch, scheduler, and preemption. In at least one embodiment, media pipeline 2739 includes logic to facilitate decoding, encoding, preprocessing, and / or postprocessing of multimedia data, including image and video data.In at least one embodiment, the media pipeline 2739 implements media operations via requests to compute or sensing logic within the subcores 2701-2701F.

[0227] In at least one embodiment, the SoC interface 2737 enables the graphics core 2700 to communicate with general-purpose application processor cores (e.g., CPUs) and / or other components within an SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, the SoC interface 2737 may also enable communication with fixed devices within an SoC, such as camera imaging pipelines, and enables the use and / or implementation of global memory atomics that may be shared between graphics cores 2700 and CPUs within an SoC.In at least one embodiment, the SoC interface 2737 may also implement power management controls for the graphics core 2700 and enable an interface between a clock domain of the graphics core 2700 and other clock domains within an SoC. In at least one embodiment, the SoC interface 2737 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions may be sent to the media pipeline 2739 when media operations are to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2736, geometry and fixed function pipeline 2714) when graphics processing operations are to be performed.

[0228] In at least one embodiment, graphics microcontroller 2738 may be configured to perform various scheduling and management tasks for graphics core 2700. In at least one embodiment, graphics microcontroller 2738 may perform the scheduling of graphics and / or compute workloads on various parallel graphics engines within execution unit (EU) arrays 2702A-2702F, 2704A-2704F within subcores 2701A-2701F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core 2700 may submit workloads to one of several graphics processor doorbells, which invokes a scheduler operation on an appropriate graphics engine.In at least one embodiment, the scheduling operations include determining the next workload to execute, submitting a workload to an instruction streamer, preempting existing workloads running on an engine, monitoring the progress of a workload, and notifying host software when a workload completes. In at least one embodiment, the graphics microcontroller 2738 may also facilitate low-power or idle states for the graphics core 2700 by providing the graphics core 2700 with the ability to save and restore registers within the graphics core 2700 across low-power state transitions independent of an operating system and / or graphics driver software on a system.

[0229] In at least one embodiment, the graphics core 2700 may include more or fewer subcores than the shown subcores 2701A-2701F, up to N modular subcores. For each set of N subcores, the graphics core 2700 may also include, in at least one embodiment, shared function logic 2710, shared and / or cache memory 2712, a geometry / fixed function pipeline 2714, and additional fixed function logic 2716 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2710 may include logical units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by all N subcores within the graphics core 2700.Shared and / or cache memory 2712 may be an LLC for N subcores 2701A-2701F within graphics core 2700 and may also serve as shared memory accessible by multiple subcores. In at least one embodiment, geometry / fixed function pipeline 2714 may be included within functional block 2730 instead of geometry / fixed function pipeline 2736 and may include the same or similar logic units.

[0230] In at least one embodiment, the graphics core 2700 includes additional fixed function logic 2716, which may include various fixed function acceleration logic for use by the graphics core 2700. In at least one embodiment, the additional fixed function logic 2716 includes an additional geometry pipeline for use in position-dependent shading. In position-dependent shading, there are at least two geometry pipelines: a full geometry pipeline within the geometry and fixed function pipelines 2716, 2736, and a cull pipeline, an additional geometry pipeline that may include the additional fixed function logic 2716. In at least one embodiment, the cull pipeline is a stripped-down version of a full geometry pipeline.In at least one embodiment, a full pipeline and a cull pipeline may execute different instances of an application, each instance having its own context. In at least one embodiment, position-dependent shading may hide long cull runs of discarded triangles, allowing shading to complete sooner in some cases. For example, in at least one embodiment, the cull pipeline logic within the additional fixed function logic 2716 may execute position shaders in parallel with a main application and generally produces critical results faster than a full pipeline because a cull pipeline retrieves and shades position attributes of vertices without performing rasterization and rendering of pixels to a frame buffer.In at least one embodiment, a cull pipeline may use generated critical results to compute visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, a full pipeline (which in this case may be referred to as a replay pipeline) may use visibility information to skip rejected triangles and shade only visible triangles, which are ultimately passed to rasterization.

[0231] In at least one embodiment, the additional fixed function logic 2716 may also include general processing acceleration logic, such as fixed function matrix multiplication logic to accelerate CUDA programs.

[0232] In at least one embodiment, each graphics sub-core 2701A-2701F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-cores 2701A-2701F include a plurality of EU arrays 2702A-2702F, 2704A-2704F, thread dispatcher and inter-thread communication logic ("TD / IC") 2703A-2703F, a 3D sampler (e.g., texture) 2705A-2705F, a media sampler 2706A-2706F, a shader processor 2707A-2707F, and shared local memory ("SLM") 2708A-2708F.The EU arrays 2702A-2702F, 2704A-2704F each include a plurality of execution units, which are GPGPUs capable of performing floating-point and integer / fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2703A-2703F performs local thread dispatch and thread control operations for execution units within a subcore and facilitates communication between threads executing on execution units of a subcore. In at least one embodiment, the 3D sampler 2705A-2705F can read texture or other 3D graphics data into memory. In at least one embodiment, the 3D sampler may read texture data differently based on a configured state and a texture format associated with a particular texture.In at least one embodiment, the media sampler 2706A-2706F may perform similar read operations based on a type and format associated with the media data. In at least one embodiment, each graphics core 2701A-2701F may alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of the subcores 2701A-2701F may utilize the shared local memory 2708A-2708F within each subcore to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0233] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 27 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 27 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0234] Fig. 28 illustrates a parallel processing unit ("PPU") 2800 in accordance with at least one embodiment. In at least one embodiment, the PPU 2800 is configured with machine-readable code that, when executed by the PPU 2800, causes the PPU 2800 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2800 is a multi-threaded processor implemented on one or more integrated circuits that utilizes multithreading as a latency hiding technique to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured for execution by the PPU 2800.In at least one embodiment, PPU 2800 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2800 is used to perform computations such as linear algebra operations and machine learning operations. Fig. Figure 28 shows an example parallel processor for illustration only and should be understood as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.

[0235] In at least one embodiment, one or more PPUs 2800 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2800 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2800 includes, without limitation, an I / O unit 2806, a front-end unit 2810, a scheduler unit 2812, a work distribution unit 2814, a hub 2816, a crossbar (“Xbar”) 2820, one or more general processing clusters (“GPCs”) 2818, and one or more partition units (“memory partition units”) 2822. In at least one embodiment, the PPU 2800 is connected to a host processor or other PPUs 2800 via one or more high-speed GPU interconnects (“SPU interconnects”) 2808.In at least one embodiment, the PPU 2800 is connected to a host processor or other peripheral devices via a system bus or interconnect 2802. In at least one embodiment, the PPU 2800 is connected to local memory, including one or more memory devices ("memory") 2804. In at least one embodiment, the memory devices 2804 include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (HBM) subsystems, with multiple DRAM dies stacked within each device.

[0236] In at least one embodiment, the high-speed GPU interconnect 2808 may refer to a wired multi-lane communication link used by systems including one or more PPUs 2800 in combination with one or more CPUs and is scalable, and supports cache coherency between PPUs 2800 and CPUs, as well as CPU mastering. In at least one embodiment, data and / or commands are transferred via the high-speed GPU interconnect 2808 through the hub 2816 to / from other units of the PPU 2800, such as one or more copy engines, video encoders, video decoders, power management units, and other components included in Fig. 28 may not be shown explicitly.

[0237] In at least one embodiment, the I / O unit 2806 is configured to receive communications (e.g., commands, data) from a host processor (in Fig. 28 not shown) over system bus 2802. In at least one embodiment, I / O unit 2806 communicates with the host processor directly over system bus 2802 or through one or more intermediary devices, such as a memory bridge. In at least one embodiment, I / O unit 2806 may communicate with one or more other processors, such as one or more PPUs 2800, over system bus 2802. In at least one embodiment, I / O unit 2806 implements a PCIe interface for communicating over a PCIe bus. In at least one embodiment, I / O unit 2806 implements interfaces for communicating with external devices.

[0238] In at least one embodiment, the I / O unit 2806 decodes packets received over the system bus 2802. In at least one embodiment, at least some packets represent commands configured to cause the PPU 2800 to perform various operations. In at least one embodiment, the I / O unit 2806 transmits decoded commands to various other units of the PPU 2800, as indicated by the commands. In at least one embodiment, commands are transmitted to the front-end unit 2810 and / or to the hub 2816 or other units of the PPU 2800, such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (in Fig. 28). In at least one embodiment, the I / O unit 2806 is configured to direct communication between and among various logical units of the PPU 2800.

[0239] In at least one embodiment, a program executed by the host processor encodes an instruction stream in a buffer that provides workloads to the PPU 2800 for processing. In at least one embodiment, a workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) to both a processor and the PPU 2800—a host interface may be configured to access the buffer in system memory coupled to the system bus 2802 via memory requests transmitted from the I / O device 2806 over the system bus 2802.In at least one embodiment, a host processor writes an instruction stream to a buffer and then transfers a pointer to the beginning of the instruction stream to the PPU 2800, so that the front-end unit 2810 receives pointers to one or more instruction streams and manages one or more instruction streams, reading instructions from the instruction streams and forwarding instructions to various units of the PPU 2800.

[0240] In at least one embodiment, the front-end unit 2810 is coupled to the scheduler unit 2812, which configures various GPCs 2818 to process tasks defined by one or more instruction streams. In at least one embodiment, the scheduler unit 2812 is configured to track state information related to various tasks managed by the scheduler unit 2812, where the state information may indicate which of the GPCs 2818 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so on. In at least one embodiment, the scheduler unit 2812 manages the execution of a plurality of tasks on one or more of the GPCs 2818.

[0241] In at least one embodiment, the scheduler unit 2812 is coupled to the work distribution unit 2814, which is configured to distribute tasks for execution among the GPCs 2818. In at least one embodiment, the work distribution unit 2814 tracks a number of scheduled tasks received from the scheduler unit 2812, and the work distribution unit 2814 maintains a pending task pool and an active task pool for each GPC 2818.In at least one embodiment, the pending task pool includes a number of slots (e.g., 32 slots) containing tasks assigned for processing by a particular GPC 2818; the active task pool may include a number of slots (e.g., 4 slots) for tasks actively being processed by the GPCs 2818, such that when one of the GPCs 2818 completes execution of a task, that task is removed from the active task pool for the GPC 2818, and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2818.In at least one embodiment, when an active task on the GPC 2818 is idle, for example, while waiting for a data dependency to be resolved, the active task is removed from the GPC 2818 and returned to a pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 2818.

[0242] In at least one embodiment, work distribution unit 2814 communicates with one or more GPCs 2818 via XBar 2820. In at least one embodiment, XBar 2820 is an interconnection network that connects many units of PPU 2800 to other units of PPU 2800 and can be configured to connect work distribution unit 2814 to a particular GPC 2818. In at least one embodiment, one or more other units of PPU 2800 can also be connected to XBar 2820 via hub 2816.

[0243] In at least one embodiment, tasks are managed by the scheduler unit 2812 and forwarded by the work distribution unit 2814 to one of the GPCs 2818. The GPC 2818 is configured to process tasks and produce results. In at least one embodiment, the results may be consumed by other tasks within the GPC 2818, forwarded to another GPC 2818 via the XBar 2820, or stored in memory 2804. In at least one embodiment, results may be written to memory 2804 via partition units 2822, which implement a memory interface for reading and writing data to / from memory 2804. In at least one embodiment, the results may be transferred to another PPU 2804 or CPU via a high-speed GPU interconnect 2808.In at least one embodiment, the PPU 2800 includes, without limitation, a number U of partition units 2822 that corresponds to the number of separate and distinct storage devices 2804 connected to the PPU 2800.

[0244] In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface ("API") that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2800. In at least one embodiment, multiple applications are executed concurrently by the PPU 2800, and the PPU 2800 provides isolation, quality of service ("QoS"), and independent address spaces for multiple applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver kernel to spawn one or more tasks for execution by the PPU 2800, and the driver kernel issues tasks to one or more streams that are processed by the PPU 2800. In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp.In at least one embodiment, a warp comprises a plurality of contiguous threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, cooperating threads may refer to a plurality of threads that comprise instructions for executing a task and that exchange data via a shared memory.

[0245] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 28 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 28 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein.

[0246] Fig. Figure 29 shows a GPC 2900 in accordance with at least one embodiment. In at least one embodiment, the GPC 2900 is the GPC 2818 of Fig. 28. In at least one embodiment, each GPC 2900 includes, without limitation, a number of hardware units for processing tasks, and each GPC 2900 includes, without limitation, a pipeline manager 2902, a work distribution unit (“PROP”) 2904, a raster engine 2908, a work distribution crossbar (“WDX”) 2916, an MMU 2918, one or more processing clusters (“DPCs”) 2906, and any suitable combination of parts.

[0247] In at least one embodiment, the operation of the GPC 2900 is controlled by the pipeline manager 2902. In at least one embodiment, the pipeline manager 2902 manages the configuration of one or more DPCs 2906 for processing tasks associated with the GPC 2900. In at least one embodiment, the pipeline manager 2902 configures at least one of the one or more DPCs 2906 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2906 is configured to execute a vertex shader program on a programmable streaming multiprocessor ("SM") 2914.In at least one embodiment, pipeline manager 2902 is configured to forward packets received from a work distribution unit to appropriate logical units within GPC 2900, and in at least one embodiment, some packets may be forwarded to fixed-function hardware units in PROP 2904 and / or raster engine 2908, while other packets may be forwarded to DPCs 2906 for processing by a primitive engine 2912 or SM 2914. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to implement a computational pipeline. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to execute at least a portion of a CUDA program.

[0248] In at least one embodiment, the PROP unit 2904 is configured to forward the data generated by the raster engine 2908 and the DPCs 2906 to a raster operations partition unit (“ROP”), such as the memory partition unit 2822 described above in connection with Fig. 28. In at least one embodiment, the PROP unit 2904 is configured to perform optimizations for blending colors, organizing pixel data, performing address translations, etc. In at least one embodiment, the raster engine 2908 includes, without limitation, a number of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2908 includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tiling engine, and any suitable combination thereof.In at least one embodiment, a setup engine receives transformed vertices and generates plane equations associated with a vertex-defined geometric primitive; the plane equations are passed to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; the output of the coarse raster engine is passed to a culling engine, where fragments associated with a primitive that fail a z-test are discarded, and to a clipping engine, where fragments that lie outside a view frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine.In at least one embodiment, the output of raster engine 2908 includes fragments that are processed by any suitable unit, such as a fragment shader implemented in DPC 2906.

[0249] In at least one embodiment, each DPC 2906 included in GPC 2900 includes, without limitation, an M-Pipe Controller ("MPC") 2910; a Primitive Engine 2912; one or more SMs 2914; and any suitable combination thereof. In at least one embodiment, MPC 2910 controls the operation of DPC 2906 and forwards packets received from Pipeline Manager 2902 to the appropriate units in DPC 2906. In at least one embodiment, packets associated with a vertex are passed to Primitive Engine 2912, which is configured to retrieve vertex attributes associated with the vertex from memory; in contrast, packets associated with a shader program may be transferred to SM 2914.

[0250] In at least one embodiment, SM 2914 includes, without limitation, a programmable streaming processor configured to process tasks represented by a number of threads. In at least one embodiment, SM 2914 is multi-threaded and configured to concurrently execute a plurality of threads (e.g., 32 threads) from a given group of threads and implements a SIMD architecture in which each thread in a group of threads (e.g., a warp) is configured to process a different set of instructions based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instructions.In at least one embodiment, SM 2914 implements a SIMT architecture, where each thread in a group of threads is configured to process a different set of instructions based on the same instruction set, but where the individual threads in the group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, enabling concurrency between warps and serial execution within warps when threads diverge within a warp. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, enabling equal concurrency among all threads within and between warps.In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instructions may be merged and executed in parallel to improve efficiency. At least one embodiment of SM 2914 is described in connection with. Fig. 30 described in more detail.

[0251] In at least one embodiment, MMU 2918 provides an interface between GPC 2900 and a memory partition unit (e.g., partition unit 2822 of Fig. 28), and MMU 2918 provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2918 provides one or more translation lookaside buffers (TLBs) for performing virtual address to physical address translation in memory.

[0252] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 29 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 29 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0253] Fig. 30 shows a streaming multiprocessor ("SM") 3000 in accordance with at least one embodiment. In at least one embodiment, SM 3000 is SM 2914 of Fig. 29. In at least one embodiment, SM 3000 includes, without limitation, an instruction cache 3002; one or more scheduler units 3004; a register file 3008; one or more processing cores ("cores") 3010; one or more special function units ("SFUs") 3012; one or more LSUs 3014; an interconnect network 3016; a shared memory / L1 cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit distributes tasks for execution among GPCs of parallel processing units (PPUs), and each task is assigned to a particular data processing cluster (DPC) within a GPC, and if a task is associated with a shader program, the task is assigned to one of the SMs 3000.In at least one embodiment, scheduler unit 3004 receives tasks from a work distribution unit and manages the scheduling of instructions for one or more thread blocks assigned to SM 3000. In at least one embodiment, scheduler unit 3004 schedules thread blocks for execution as warps of parallel threads, with each thread block having at least one warp associated with it. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit 3004 manages a plurality of different thread blocks by allocating warps to the different thread blocks and then dispatching instructions from a plurality of different cooperative groups to different functional units (e.g., processing cores 3010, SFUs 3012, and LSUs 3014) during each clock cycle.In at least one embodiment, SM 3000 includes one or more thread block clusters, where a thread block cluster may enable programmatic control of locality at a greater granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently across streaming multiprocessors to synchronize and collectively retrieve, exchange, or otherwise utilize data.

[0254] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads communicate, thus enabling richer, more efficient parallel decompositions. In at least one embodiment, cooperative startup APIs support synchronization between thread blocks for executing parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function).However, in at least one embodiment, programmers can define groups of threads with a granularity smaller than that of the thread block and synchronize within the defined groups to enable higher performance, design flexibility, and software reuse in the form of common group-wide functional interfaces. In at least one embodiment, cooperative groups allow programmers to explicitly define groups of threads with sub-block and multi-block granularity and perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, the granularity of a sub-block is as small as a single thread.In at least one embodiment, a programming model supports clean composition across software boundaries, allowing libraries and utilities to safely synchronize within their local context without requiring convergence assumptions. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0255] In at least one embodiment, a dispatch unit 3006 is configured to transmit instructions to one or more functional units, and the scheduler unit 3004 includes, without limitation, two dispatch units 3006 that allow two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0256] In at least one embodiment, each SM 3000 includes, without limitation, a register file 3008 that provides a set of registers for functional units of the SM 3000. In at least one embodiment, the register file 3008 is partitioned between the individual functional units such that each functional unit is associated with a separate section of the register file 3008. In at least one embodiment, the register file 3008 is partitioned between different warps executed by the SM 3000, and the register file 3008 provides temporary storage for operands associated with data paths of functional units. In at least one embodiment, each SM 3000 includes, without limitation, a plurality of L processing cores 3010. In at least one embodiment, the SM 3000 includes, without limitation, a large number (e.g., 128 or more) of different processing cores 3010.In at least one embodiment, each processing core 3010 includes, without limitation, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, without limitation, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic units implement the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing cores 3010 include, without limitation, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0257] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores 3010. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for training and inferencing neural networks. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiplication and accumulation operation D = AXB + C, where A, B, C, and D are 4x4 matrices.

[0258] In at least one embodiment, the inputs for matrix multiplication A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating-point input data with 32-bit floating-point accumulation. In at least one embodiment, 64 operations are used for the 16-bit floating-point multiplication, resulting in a full-precision product, which is then accumulated by 32-bit floating-point addition with other intermediate products to form a 4x4x4 matrix multiplication. In at least one embodiment, tensor cores are used to perform much larger two-dimensional or higher-dimensional matrix operations constructed from these smaller elements.In at least one embodiment, an API, such as a CUDA C++ API, provides specialized operations for loading, multiplying, accumulating, and storing matrices to efficiently utilize tensor cores in a CUDA C++ program. In at least one embodiment at the CUDA level, a warp-level interface assumes 16x16 matrices spanning all 32 threads of a warp.

[0259] In at least one embodiment, each SM 3000 includes, without limitation, M SFUs 3012 that perform specific functions (e.g., attribute evaluation, reciprocal square root, and the like). In at least one embodiment, the SFUs 3012 include, without limitation, a tree processing unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 3012 include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to generate sampled texture values ​​for use in shader programs executed by SM 3000. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3018.In at least one embodiment, texture units implement texture operations such as filtering operations using mipmaps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 3000 includes, without limitation, two texture units.

[0260] In at least one embodiment, each SM 3000 includes, without limitation, N LSUs 3014 that perform load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, without limitation, an interconnection network 3016 that connects each of the functional units to the register file 3008 and the LSU 3014 to the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnection network 3016 is a crossbar that can be configured to connect each of the functional units to each of the registers in the register file 3008 and to connect LSUs 3014 to the register file 3008 and memory locations in the shared memory / L1 cache 3018.

[0261] In at least one embodiment, shared memory / L1 cache 3018 is an array of on-chip memory that enables data storage and communication between SM 3000 and a primitive engine, and between threads within SM 3000. In at least one embodiment, shared memory / L1 cache 3018 includes, without limitation, 128 KB of memory capacity and is located in a path from SM 3000 to a partition unit. In at least one embodiment, shared memory / L1 cache 3018 is used to cache read and write operations. In at least one embodiment, one or more of shared memory / L1 cache 3018, L2 cache, and memory are backing stores.

[0262] In at least one embodiment, combining data caching and shared memory functionality in a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, the capacity is or can be used as cache by programs that do not use the shared memory; for example, if the shared memory is configured to use half the capacity, texture and load / store operations can use the remaining capacity. In at least one embodiment, integration with the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to act as a high-throughput conduit for streaming data while providing high-bandwidth, low-latency access to frequently reused data.In at least one embodiment, the configuration for general-purpose parallel computing may use a simpler configuration than that used for graphics processing. In at least one embodiment, fixed-function GPUs are bypassed, resulting in a significantly simpler programming model. In at least one embodiment, and in a configuration for general-purpose parallel computing, a work distribution unit allocates and distributes blocks of threads directly to the DPCs.In at least one embodiment, threads within a block execute the same program, using a unique thread ID in a computation to ensure that each thread produces unique results, using SM 3000 to execute a program and perform computations, shared memory / L1 cache 3018 for communication between threads, and LSU 3014 to read and write global memory via shared memory / L1 cache 3018 and a memory partition unit. In at least one embodiment, when configured for general parallel computations, SM 3000 writes instructions that scheduler unit 3004 can use to start new work on DPCs.In at least one embodiment, SM 3000 includes one or more distributed shared memories (or distributed shared memories) that enable direct SM-to-SM operations, such as loading, storing, and executing atoms across multiple shared SM memory blocks.

[0263] In at least one embodiment, SM 3000 includes one or more asynchronous execution functions, including a tensor memory accelerator (TMA) unit capable of transferring data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, SM 3000 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, SM 3000 includes one or more asynchronous transaction barriers for performing atomic data movement and synchronization.In at least one embodiment, SM 3000 includes a Tensor Core Transformer Engine, which includes software and one or more cores to accelerate model training and inferencing of transformers. In at least one embodiment, a transformer manages one or more processor cores executing one or more Tensor Core Transformer Engines and dynamically selects between FP8 and 16-bit computations by rewriting and scaling between FP8 and 16-bit in each layer of one or more neural networks.

[0264] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smartphone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, and more. In at least one embodiment, the PPU is packaged on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC along with one or more other devices, such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), and the like.

[0265] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") that includes the motherboard chipset.

[0266] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 30 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 30 systems shown are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein. Software constructions for general-purpose computing

[0267] The following figures show, without limitation, exemplary software constructs for implementing at least one embodiment.

[0268] Fig. 31 shows a software stack of a programming platform in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computer system to accelerate computational tasks. In at least one embodiment, a programming platform may be accessible to software developers via libraries, compiler directives, and / or programming language extensions. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or Intel One API.

[0269] In at least one embodiment, a software stack 3100 of a programming platform provides an execution environment for an application 3101. In at least one embodiment, the application 3101 may include any computer software that can be launched on the software stack 3100. In at least one embodiment, the application 3101 may include, but is not limited to, an artificial intelligence ("AI") / machine learning ("ML") application, a high-performance computing ("HPC") application, a virtual desktop infrastructure ("VDI"), or a data center workload.

[0270] In at least one embodiment, the application 3101 and the software stack 3100 run on the hardware 3107. The hardware 3107 may, in at least one embodiment, include one or more GPUs, CPUs, FPGAs, AI Engines, and / or other types of devices that support a programming platform. In at least one embodiment, such as with CUDA, the software stack 3100 may be vendor-specific and compatible only with devices from certain manufacturers. In at least one embodiment, such as with OpenCL, the software stack 3100 may be used with devices from different manufacturers. In at least one embodiment, the hardware 3107 includes a host connected to one or more devices that can be accessed via application programming interface (“API”) calls to perform computational tasks.A device within hardware 3107 may, in at least one embodiment, include a graphics processor, an FPGA, a KI engine, or other computing device (but may also include a CPU) and its memory, as opposed to a host within hardware 3107, which may, in at least one embodiment, include, but is not limited to, a CPU (but may also include a computing device) and its memory.

[0271] In at least one embodiment, the software stack 3100 of a programming platform includes, without limitation, a number of libraries 3103, a runtime 3105, and a device kernel driver 3106. In at least one embodiment, each of the libraries 3103 may include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, the libraries 3103 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3103 include functions optimized for execution on one or more types of devices.In at least one embodiment, libraries 3103 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on devices. In at least one embodiment, libraries 3103 are coupled to corresponding APIs 3102, which may include one or more APIs exposing functions implemented in libraries 3103. In at least one embodiment, a processor (e.g., CPU, GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., parent kernel) may launch a second kernel (e.g., child kernel), and the second kernel may be used by a processor to launch additional kernels (e.g., grandchild kernels) independently of the first kernel.In at least one embodiment, a processor executes an API or calls an API from memory to support dynamic stream priority (e.g., updating the priority while a stream is being used to perform operations). When a processor executes said API, a programmer can, for example, copy the stream priority from one stream to one or more other streams.

[0272] In at least one embodiment, software stack 3100 includes an API for supporting dynamic stream priority (e.g., updating the priority while a stream is being used to perform operations), allowing a programmer to set the priority of a stream at any time after creation. In at least one embodiment, software stack 3100 includes an API for supporting dynamic stream priority (e.g., updating the priority while the stream is being used to perform operations), allowing a programmer to obtain the current priority of a stream, where the priority is one of a plurality of attributes of a stream.In at least one embodiment, software stack 3100 includes an API for supporting dynamic stream priority (e.g., updating the priority while the stream is being used to perform operations), allowing a programmer to obtain the current priority of a stream as a single attribute. In at least one embodiment, software stack 3100 includes an API for supporting dynamic stream priority (e.g., updating the priority while the stream is being used to perform operations), allowing a programmer to launch a kernel to perform operations on a stream with a specified priority that may be different from the stream priority.In at least one embodiment, the software stack 3100 includes an API that indicates whether an object (e.g., a thread synchronization object such as a barrier) that tracks whether all data movement operations for a group of threads operating on a GPU have completed has a particular state after a particular period of time, where a particular state may be a state indicating that data has been moved and is ready for use, and is specified using an expected parity value as an input to the API.

[0273] In at least one embodiment, software stack 3100 includes one or more APIs for updated kernels. In at least one embodiment, a processor executes an API or calls an API from memory to update an existing API to support context-free kernels, allowing a programmer to add a kernel node to a graph without a graphics context so that a graphics context can be dynamically associated with a kernel at runtime. In at least one embodiment, software stack 3100 includes one or more APIs that allow a programmer to obtain a kernel identifier and a graphics context as separate parameters from a kernel node, so that the parameters can be obtained from kernels and context-free kernels.In at least one embodiment, the software stack 3100 includes one or more APIs to utilize parallel processors, such as one or more graphics processing units, to launch task graphs (e.g., task graphs) and to execute one or more task graphs (e.g., including one or more programs).

[0274] In at least one embodiment, software stack 3100 includes one or more APIs to associate one or more instructions with one or more memory ordering operations, such as a fence or membar operation. In at least one embodiment, instructions are mapped to one or more domains so that a memory ordering operation is performed in association with one or more particular domains without affecting instructions from other domains. An API to indicate that a thread has arrived (e.g., at a thread synchronization barrier) or completed a phase of work related to asynchronous data movement operations on a GPU.In at least one embodiment, software stack 3100 includes one or more indications that allow programmers to manually specify an expected transaction count when a thread completes a phase of work, which is used to update an object that tracks whether all data movement operations for a group of threads have completed.

[0275] In at least one embodiment, the application 3101 is written as source code that is compiled into executable code, as described below in connection with Fig. 36-38. The executable code of application 3101 may, in at least one embodiment, be executed at least partially in an environment provided by software stack 3100. In at least one embodiment, during execution of application 3101, code may be accessed that must be executed on a device rather than a host. In such a case, in at least one embodiment, runtime 3105 may be invoked to load and launch the required code onto the device. In at least one embodiment, runtime 3105 may comprise any technically feasible runtime system capable of supporting the execution of application S01.

[0276] In at least one embodiment, runtime 3105 is implemented as one or more runtime libraries coupled to corresponding APIs represented as API(s) 3104. One or more such runtime libraries may, in at least one embodiment, include, among other functions, for memory management, execution control, device control, error handling, and / or synchronization. In at least one embodiment, the memory management functions may include, among other functions, for allocating, freeing, and copying device memory, as well as for transferring data between host memory and device memory.In at least one embodiment, execution control functions may include, but are not limited to, functions for starting a function (sometimes referred to as a "kernel" when a function is a global function that can be called from a host) on a device and for setting attribute values ​​in a buffer maintained by a runtime library for a given function to be executed on a device.

[0277] Runtime libraries and corresponding API(s) 3104 may, in at least one embodiment, be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may provide a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs may provide a higher-level set of such functions. In at least one embodiment, a high-level API for the runtime may be built upon a low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered upon a language-independent runtime API.

[0278] In at least one embodiment, one or more processors disclosed in “processing systems” may execute, access, or otherwise use the software stack 3100. For example, APU 1800, CPU 1900, 21A-21B, example graphics processors, general purpose graphics processing unit (“GPGPU”) 2230, parallel processor 2300, processing cluster 2394, graphics multiprocessor 2334, graphics multiprocessor 2396, graphics processor 2400, processor 2500, processor 2600, parallel processing unit (“PPU”) 2800, GPC 2900, and / or streaming multiprocessor (“SM”) 3000 may execute, use, call, or otherwise implement (e.g., by accessing memory) one or more software stacks 3100, one or more APIs included in software stack 3100.

[0279] In at least one embodiment, device kernel driver 3106 is configured to facilitate communication with an underlying device. In at least one embodiment, device kernel driver 3106 may provide low-level functionality relied upon by APIs, such as API(s) 3104, and / or other software. In at least one embodiment, device kernel driver 3106 may be configured to compile intermediate representation ("IR") code into binary code at runtime. With CUDA, device kernel driver 3106 may compile IR code that is not hardware-specific into binary code for a particular device at runtime (with caching of the compiled binary code), which in at least one embodiment is also referred to as "finalization code."In at least one embodiment, code finalized in this manner may be executed on a device that did not exist when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled offline into binary code without requiring the device kernel driver 3106 to compile the IR code at runtime.

[0280] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 31 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 31 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0281] Fig. 32 shows a CUDA implementation of the software stack 3100 of Fig. 31 according to at least one embodiment. In at least one embodiment, a CUDA software stack 3200 on which an application 3201 may be launched includes CUDA libraries 3203, a CUDA runtime 3205, a CUDA driver 3207, and a device kernel driver 3208. In at least one embodiment, the CUDA software stack 3200 executes on hardware 3209, which may include a graphics processor supporting CUDA and developed by NVIDIA Corporation of Santa Clara, CA.

[0282] In at least one embodiment, the application 3201, the CUDA runtime 3205, and the device kernel driver 3208 may perform similar functions to the application 3101, the runtime 3105, and the device kernel driver 3106, respectively, described above in connection with Fig. 31. In at least one embodiment, the CUDA driver 3207 includes a library (libcuda.so) that implements a CUDA driver API 3206. Similar to a CUDA runtime API 3204 implemented by a CUDA runtime library (cudart), the CUDA driver API 3206, in at least one embodiment, may provide, among other functions, for memory management, execution control, device control, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3206 differs from the CUDA runtime API 3204 in that the CUDA runtime API 3204 simplifies device code management by providing implicit initialization, context management (analogous to a process), and module management (analogous to dynamically loaded libraries).In contrast to the high-level CUDA runtime API 3204, the CUDA driver API 3206 is a low-level API that, in at least one embodiment, enables finer-grained control of the device, particularly with respect to contexts and module loading. In at least one embodiment, the CUDA driver API 3206 may provide functionality for context management not provided by the CUDA runtime API 3204. In at least one embodiment, the CUDA driver API 3206 is also language-independent, supporting, for example, OpenCL in addition to the CUDA runtime API 3204. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3205, may be considered separate from the driver components, including the user device CUDA driver 3207 and the kernel device driver 3208 (sometimes referred to as a "display" driver).

[0283] In at least one embodiment, CUDA libraries 3203 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may be accessed by parallel computing applications such as application 3201. In at least one embodiment, CUDA libraries 3203 may include mathematical libraries such as a cuBLAS library, which is an implementation of Basic Linear Algebra Subprograms ("BLAS") for performing linear algebra operations, a cuFFT library for computing Fast Fourier Transforms ("FFTs"), and a cuRAND library for generating random numbers, among others.In at least one embodiment, the CUDA libraries 3203 may include, among others, deep learning libraries such as a cuDNN library of deep neural network primitives and a TensorRT platform for high-performance deep learning inference.

[0284] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 32 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 32 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein.

[0285] Fig. 33 shows a ROCm implementation of the software stack 3100 from Fig. 31 according to at least one embodiment. In at least one embodiment, an ROCm software stack 3300 on which an application 3301 may be launched includes a script runtime 3303, a system runtime 3305, a thunk 3307, and an ROCm kernel driver 3308. In at least one embodiment, the ROCm software stack 3300 executes on hardware 3309, which may include a GPU supporting ROCm and developed by AMD Corporation of Santa Clara, CA.

[0286] In at least one embodiment, the application 3301 may provide similar functionality as described above in connection with Fig. 31. Furthermore, the speech runtime 3303 and the system runtime 3305 may, in at least one embodiment, perform similar functions as those described above in connection with Fig. 31. In at least one embodiment, the Srpach runtime 3303 and the system runtime 3305 differ in that the system runtime 3305 is a language-independent runtime that implements a ROCr system runtime API 3304 and utilizes a Heterogeneous System Architecture ("HSA") runtime API. The HSA runtime API is a lightweight user-mode API that provides interfaces for accessing and interacting with an AMD graphics processor, including, in at least one embodiment, functions for memory management, execution control via architectural kernel dispatch, error handling, system and agent information, and runtime initialization and shutdown, among other things.In contrast to the system runtime 3305, the language runtime 3303 is, in at least one embodiment, an implementation of a language-specific runtime API 3302 that sits on top of the ROCr system runtime API 3304.

[0287] In at least one embodiment, the language runtime API may include, but is not limited to, a Heterogeneous Compute Interface for Portability ("HIP") language runtime API, a Heterogeneous Compute Compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with functionally similar versions of the CUDA mechanisms, and in at least one embodiment, a HIP language runtime API includes functions similar to those described above in connection with Fig. 32 discussed in CUDA Runtime API 3204, such as functions for memory management, execution control, device management, error handling, and synchronization, among others.

[0288] In at least one embodiment, Thunk (ROCt) 3307 is an interface 3306 that can be used to interact with the underlying ROCm driver 3308. In at least one embodiment, the ROCm driver 3308 is a ROCk driver, which is a combination of an AMD GPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMD GPU driver is a device kernel driver for GPUs developed by AMD that provides similar functionality to the one described above in connection with Fig. 31. In at least one embodiment, the HSA kernel driver is a driver that enables different types of processors to more effectively share system resources through hardware features.

[0289] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3300 above the Srpach runtime 3303 and provide similar functionality to the CUDA libraries 3203 described above in connection with Fig. 32. In at least one embodiment, various libraries may include mathematical, deep learning, and / or other libraries, such as a hipBLAS library implementing functions similar to CUDA cuBLAS, a rocFFT library for computing FFTs similar to CUDA cuFFT, among others.

[0290] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 33 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 33 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0291] Fig. 34 shows an OpenCL implementation of the software stack 3100 of Fig. 31 according to at least one embodiment. In at least one embodiment, an OpenCL software stack 3400 on which an application 3401 can be launched includes an OpenCL framework 3410, an OpenCL runtime 3406, and a driver 3407. In at least one embodiment, the OpenCL software stack 3400 executes on hardware 3209 that is not vendor-specific. Because OpenCL is supported by devices developed by different manufacturers, specific OpenCL drivers may be required to interoperate with the hardware of such manufacturers in at least one embodiment.

[0292] In at least one embodiment, the application 3401, the OpenCL runtime 3406, the device kernel driver 3407, and the hardware 3408 may perform similar functions to the application 3101, the runtime 3105, the device kernel driver 3106, and the hardware 3107, respectively, described above in connection with Fig. 31. In at least one embodiment, the application 3401 further comprises an OpenCL kernel 3402 having code to be executed on a device.

[0293] In at least one embodiment, OpenCL defines a "platform" that enables a host to control devices connected to the host. In at least one embodiment, an OpenCL framework provides a platform-layer API and a runtime API, represented as Platform API 3403 and Runtime API 3405. In at least one embodiment, Runtime API 3405 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a corresponding context that Runtime API 3405 can use to manage instruction queues, program objects and kernel objects, shared memory objects, etc. for that device. In at least one embodiment, Platform API 3403 provides functions that allow device contexts to beto select and initialize devices, to submit work to devices via command queues, and to enable data transfer to and from devices. Furthermore, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions.

[0294] In at least one embodiment, a compiler 3404 is also included in the OpenCL framework 3410. The source code may, in at least one embodiment, be compiled offline prior to execution of an application or online during execution of an application. Unlike CUDA and ROCm, in at least one embodiment, OpenCL applications may be compiled online by compiler 3404, which is representative of any number of compilers that may be used to compile source code and / or IR code, such as Standard Portable Intermediate Representation ("SPIR-V") code, into binary code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline before execution.

[0295] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 34 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 34 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0296] Fig. 35 shows software supported by a programming platform according to at least one embodiment. In at least one embodiment, a programming platform 3504 is configured to support various programming models 3503, middleware and / or libraries 3502, and frameworks 3501 that an application 3500 may rely on. In at least one embodiment, the application 3500 may be an AI / ML application implemented, for example, using a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computations on the underlying hardware.

[0297] In at least one embodiment, the programming platform 3504 may implement one of the methods described above in connection with Fig. 32, Fig. 33 respectively Fig. 34. In at least one embodiment, the programming platform 3504 supports multiple programming models 3503, which are abstractions of an underlying computer system that enable expressions of algorithms and data structures. In at least one embodiment, the programming models 3503 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming models 3503 may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0298] In at least one embodiment, libraries and / or middleware 3502 provide implementations of abstractions of programming models 3504. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. At least in one embodiment, such middleware includes software that provides services to applications beyond those available from programming platform 3504. In at least one embodiment, libraries and / or middleware 3502 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries.Furthermore, in at least one embodiment, the libraries and / or middleware 3502 may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries that provide communication routines for GPUs, an MIOpen library for deep learning accelerators, and / or an Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0299] In at least one embodiment, application frameworks 3501 depend on libraries and / or middleware 3502. In at least one embodiment, each of the application frameworks 3501 is a software framework used to implement a standard application software structure. Returning to the AI / ML example discussed above, an AI / ML application may, in at least one embodiment, be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks.

[0300] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 35 are used to create an application programming interface (API), such as for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 35 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or operations otherwise described herein.

[0301] Fig. 36 shows the compilation of code for execution on one of the programming platforms of the Fig. 31-34 according to at least one embodiment. In at least one embodiment, a compiler 3601 receives source code 3600 that includes both host code and device code. In at least one embodiment, the compiler 3601 is configured to convert the source code 3600 into host executable code 3602 for execution on a host and into device executable code 3603 for execution on a device. In at least one embodiment, the source code 3600 can be compiled either offline prior to execution of an application or online during execution of an application. In at least one embodiment, the compiler 3601 includes or has access to one or more libraries to recognize a sequence of API calls to execute a single fused API, where a single fused API is a combined API for two or more APIs.

[0302] In at least one embodiment, source code 3600 may include code in any programming language supported by compiler 3601, such as C++, C, Fortran, etc. In at least one embodiment, source code 3600 may include a single-source file having a mixture of host code and device code, with the locations of the device code indicated therein. In at least one embodiment, a single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3600 may include multiple source code files in which host code and device code are separated, rather than a single source file.

[0303] In at least one embodiment, compiler 3601 is configured to compile source code 3600 into host executable code 3602 for execution on a host and device executable code 3603 for execution on a device. In at least one embodiment, compiler 3601 performs operations including parsing source code 3600 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3600 comprises a single-source file, compiler 3601 may separate device code from host code in such a single-source file, combine the device code and host code into device executable code 3603 and device executable code 3603, respectively.a host executable code 3602 and link the device executable code 3603 and the host executable code 3602 into a single file as described below with respect to . Fig. 37 discussed in more detail.

[0304] In at least one embodiment, host-executable code 3602 and device-executable code 3603 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host-executable code 3602 may comprise native object code, and device-executable code 3603 may comprise PTX intermediate representation code. In the case of ROCm, both host-executable code 3602 and device-executable code 3603 may comprise target binary code, in at least one embodiment.

[0305] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 36 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 36 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0306] Fig. 37 is a more detailed illustration of compiling code for execution on one of the programming platforms of the Fig. 31-34, according to at least one embodiment. In at least one embodiment, a compiler 3701 is configured to receive source code 3700, compile source code 3700, and output an executable file 3710. In at least one embodiment, source code 3700 is a single-source file, such as a .cu file, a .hip.cpp file, or a file in another format that includes both host and device code. In at least one embodiment, compiler 3701 may be, but is not limited to, an NVIDIA CUDA compiler ("NVCC") for compiling CUDA code into .cu files or an HCC compiler for compiling HIP code into .hip.cpp files.

[0307] In at least one embodiment, compiler 3701 includes a compiler front-end 3702, a host compiler 3705, a device compiler 3706, and a linker 3709. In at least one embodiment, compiler front-end 3702 is configured to separate device code 3704 from host code 3703 in source code 3700. Device code 3704 is compiled by device compiler 3706 into device-executable code 3708, which, as described, may include binary code or IR code in at least one embodiment. Separately, host code 3703 is compiled by host compiler 3705 into executable host code 3707 in at least one embodiment.For NVCC, the host compiler 3705 may be a general-purpose C / C++ compiler that outputs native object code, while the device compiler 3706 may be a Low Level Virtual Machine ("LLVM")-based compiler that forks an LLVM compiler infrastructure and outputs PTX code or binary code, at least in one embodiment. For HCC, both the host compiler 3705 and the device compiler 3706 may be, but are not limited to, LLVM-based compilers that output target binary code, in at least one embodiment.

[0308] Following compilation of source code 3700 into host executable code 3707 and device executable code 3708, in at least one embodiment, device compiler 3709 links host executable code 3707 and device executable code 3708 together in an executable file 3710. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (ELF) file, which is a container format for storing object code.

[0309] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 37 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 37 systems depicted are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein.

[0310] Fig. 38 illustrates the translation of source code prior to compiling source code, according to at least one embodiment. In at least one embodiment, source code 3800 is passed through a translation tool 3801, which translates source code 3800 into translated source code 3802. In at least one embodiment, a compiler 3803 is used to compile translated source code 3802 into host-executable code 3804 and device-executable code 3805, in a process similar to compiler 3601 compiling source code 3600 into host-executable code 3602 and device-executable code 3603, as described above in connection with Fig. 36 described.

[0311] In at least one embodiment, a translation performed by the translation tool 3801 is used to port the source code 3800 for execution in a different environment than the one in which it was originally intended to be executed. In at least one embodiment, the translation tool 3801 may include, but is not limited to, a HIP translator used to "hipify" CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the translation of the source code 3800 may include parsing the source code 3800 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as described below in connection with Fig. 39A-40. Returning to the example of HIPification of CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA libraries may be converted into corresponding HIP API calls. In at least one embodiment, the automatic translations performed by the translation tool 3801 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3800.

[0312] In at least one embodiment, one or more systems and / or other hardware / software included in Fig. 38 are used to create an application programming interface (API), for example for one or more neural networks, with various algorithms, formulas and processes as used in conjunction with Fig. 7 and / or otherwise perform operations described herein. In at least one embodiment, one or more of the Fig. 38 depicted systems are used to implement one or more systems and / or processes as used in conjunction with Fig. 1-11, and / or to execute an application programming interface (API) to perform one or more cryptographic operations / functions and / or to otherwise perform operations described herein. CONFIGURING GPUS FOR GENERAL-PURPOSE COMPUTING

[0313] The following figures illustrate, without limitation, exemplary architectures for compiling and executing computational source code in accordance with at least one embodiment.

[0314] Fig. 39A shows a system 3900 configured to compile and execute CUDA source code 3910 using different types of processing units, according to at least one embodiment. In at least one embodiment, the system 3900 includes, without limitation, the CUDA source code 3910, a CUDA compiler 3950, host executable code 3970(1), host executable code 3970(2), and CUDA device executable code 3984, a CPU 3990, a CUDA-capable GPU 3994, a GPU 3992, a CUDA-to-HIP translation tool 3920, HIP source code 3930, a HIP compiler driver 3940, an HCC 3960, and HCC device executable code 3982.

[0315] In at least one embodiment, the CUDA source code 3910 is a collection of human-readable code in a CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in a CUDA programming language. At least in one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the device code is source code that, after compilation, is executable in parallel on a device. In at least one embodiment, a device may be a processor optimized for parallel processing of instructions, such as a CUDA-capable GPU 3990, GPU 39192, or other GPGPU, etc.In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, a host is a processor optimized for processing sequential instructions, such as a CPU 3990.

[0316] In at least one embodiment, the CUDA source code 3910 includes, without limitation, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, global functions 3912, device functions 3914, host functions 3916, and host / device functions 3918 may be intermixed in the CUDA source code 3910. In at least one embodiment, each of the global functions 3912 is executable on a device and invokable by a host. Therefore, in at least one embodiment, one or more of the global functions 3912 may serve as entry points for a device. In at least one embodiment, each of the global functions 3912 is a kernel.In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3912 define a kernel executable on a device and invokable from such a device. In at least one embodiment, a kernel is executed N (where N is any positive integer) times in parallel by N different threads on a device during execution.

[0317] In at least one embodiment, each of the device functions 3914 executes on a device and is callable only from such a device. In at least one embodiment, each of the host functions 3916 executes on a host and is callable only from such a host. In at least one embodiment, each of the host / device functions 3916 defines both a host version of a function executable on a host and callable only from such a host, and a device version of the function executable on a device and callable only from such a device.

[0318] In at least one embodiment, the CUDA source code 3910 may also include, without limitation, any number of calls to any number of functions defined via a CUDA runtime API 3902. In at least one embodiment, the CUDA runtime API 3902 may include, without limitation, any number of functions executed on a host to allocate and deallocate device memory, transfer data between host memory and device memory, manage multi-device systems, etc. In at least one embodiment, the CUDA source code 3910 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API intended for use by CUDA code.In at least one embodiment, the CUDA APIs include, without limitation, the CUDA Runtime API 3902, a CUDA Driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment, a CUDA Driver API is a lower-level API compared to the CUDA Runtime API 3902, but enables finer-grained control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0319] In at least one embodiment, the CUDA compiler 3950 compiles the input CUDA code (e.g., the CUDA source code 3910) to generate host executable code 3970(1) and device executable code 3984. In at least one embodiment, the CUDA compiler 3950 is NVCC. In at least one embodiment, the host executable code 3970(1) is a compiled version of the host code that includes the input source code executable on the CPU 3990. In at least one embodiment, the CPU 3990 may be any processor optimized for processing sequential instructions.

[0320] In at least one embodiment, the CUDA device executable code 3984 is a compiled version of the device code included in the input source code executable on the CUDA-capable GPU 3994. In at least one embodiment, the device executable CUDA code 3984 includes, without limitation, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, without limitation, IR code, such as PTX code, that is further compiled at runtime by a driver into binary code for a particular target device (e.g., CUDA-capable GPU 3994). In at least one embodiment, the CUDA-capable GPU 3994 can be any processor optimized for processing parallel instructions and supporting CUDA. In at least one embodiment, the CUDA-capable graphics processor 3994 is developed by NVIDIA Corporation in Santa Clara, CA.

[0321] In at least one embodiment, the CUDA-to-HIP translation tool 3920 is configured to translate CUDA source code 3910 into functionally similar HIP source code 3930. In at least one embodiment, the HIP source code 3930 is a collection of human-readable code in a HIP programming language. In at least one embodiment, the HIP code is human-readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, a HIP programming language may include a subset of the functionality of a CUDA programming language.For example, in at least one embodiment, a HIP programming language includes, without limitation, one or more mechanisms for defining global functions 3912, but such a HIP programming language may lack support for dynamic parallelism, and therefore global functions 3912 defined in HIP code may only be called from host code.

[0322] In at least one embodiment, the HIP source code 3930 includes, without limitation, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, the HIP source code 3930 may also include any number of calls to any number of functions specified in a HIP runtime API 3932. In at least one embodiment, the HIP runtime API 3932 includes, without limitation, functionally similar versions of a subset of functions included in the CUDA runtime API 3902.In at least one embodiment, the HIP source code 3930 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API intended for use by HIP code and / or ROCm. In at least one embodiment, the HIP APIs include, without limitation, the HIP runtime API 3932, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0323] In at least one embodiment, the CUDA-to-HIP translation tool 3920 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, the CUDA-to-HIP translation tool 3920 converts any number of calls to functions specified in the CUDA runtime API 3902 to any number of calls to functions specified in the HIP runtime API 3932.

[0324] In at least one embodiment, the CUDA-to-HIP translation tool 3920 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, the CUDA-to-HIP translation tool 3920 is a tool known as hipify-clang, which performs a more complex and robust translation process than hipify-perl, including parsing CUDA code using clang (a compiler front-end) and then translating the resulting symbols. In at least one embodiment, correctly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to those performed by the CUDA-to-HIP translation tool 3920.

[0325] In at least one embodiment, the HIP compiler driver 3940 is a front end that determines a target device 3946 and then configures a compiler compatible with the target device 3946 to compile HIP source code 3930. In at least one embodiment, the target device 3946 is a processor optimized for processing parallel instructions. In at least one embodiment, the driver of the HIP compiler 3940 can determine the target device 3946 in any technically feasible manner.

[0326] In at least one embodiment, the HIP compiler driver 3940 generates a HIP / NVCC compilation command 3942 if the target device 3946 is CUDA compatible (e.g., a CUDA-enabled GPU 3994). In at least one embodiment, and as described in connection with Fig. 39B, the HIP / NVCC compile command 3942 configures the CUDA compiler 3950 to compile the HIP source code 3930 using, without limitation, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment, and in response to the HIP / NVCC compile command 3942, the CUDA compiler 3950 generates host executable code 3970(1) and CUDA device executable code 3984.

[0327] In at least one embodiment, the HIP compiler driver 3940 generates a HIP / HCC compilation command 3944 if the target device 3946 is not CUDA compatible. In at least one embodiment, and as described in connection with Fig. 39C, the HIP / HCC compile command 3944 configures HCC 3960 to compile HIP source code 3930 using, without limitation, an HCC header and a HIP / HCC runtime library. In at least one embodiment, and in response to the HIP / HCC compile command 3944, HCC 3960 generates host executable code 3970(2) and device executable code 3982. In at least one embodiment, the HCC device executable code 3982 is a compiled version of the device executable code that includes the HIP source code 3930 and is executable on the GPU 3992. In at least one embodiment, the GPU 3992 may be any processor optimized for processing parallel instructions, is non-CUDA compatible, and is HCC compatible. In at least one embodiment, the GPU 3992 is developed by AMD Corporation in Santa Clara, CA.In at least one embodiment, GPU 3992 is a non-CUDA-capable GPU 3992.

[0328] For clarification, Fig. 39A depicts three different flows that may be implemented, in at least one embodiment, to compile CUDA source code 3910 for execution on CPU 3990 and different devices. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3910 for execution on CPU 3990 and CUDA-enabled GPU 3994 without translating CUDA source code 3910 into HIP source code 3930. In at least one embodiment, an indirect CUDA process translates the CUDA source code 3910 into the HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and the CUDA-enabled GPU 3994. In at least one embodiment, a CUDA / HCC process translates the CUDA source code 3910 into HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and the GPU 3992.

[0329] A direct CUDA flow that may be implemented in at least one embodiment is depicted by dashed lines and a series of bubbles labeled A1-A3. In at least one embodiment, and as depicted with the bubble labeled A1, the CUDA compiler 3950 receives the CUDA source code 3910 and a CUDA compile command 3948 that configures the CUDA compiler 3950 to compile the CUDA source code 3910. In at least one embodiment, the CUDA source code 3910 used in a direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compilation command 3948, the CUDA compiler 3950 generates host executable code 3970(1) and device executable code 3984 (depicted with bubble A2).In at least one embodiment, and as depicted in bubble A3, the host executable code 3970(1) and the CUDA device executable code 3984 may be executed on the CPU 3990 and the CUDA-enabled GPU 3994, respectively. In at least one embodiment, the device executable CUDA code 3984 comprises, without limitation, binary code. In at least one embodiment, the device executable CUDA code 3984 comprises, without limitation, PTX code and is further compiled at runtime into binary code for a particular target device.

[0330] An indirect CUDA flow that may be implemented in at least one embodiment is depicted by dashed lines and a series of bubbles labeled B1-B6. In at least one embodiment, and as depicted in the bubble labeled B1, the CUDA-to-HIP translation tool 3920 receives the CUDA source code 3910. In at least one embodiment, and as depicted in the bubble labeled B2, the CUDA-to-HIP translation tool 3920 translates the CUDA source code 3910 into the HIP source code 3930. In at least one embodiment, and as depicted in bubble B3, the HIP compiler 3940 receives the HIP source code 3930 and determines that the target device 3946 is CUDA-capable.

[0331] In at least one embodiment, and as depicted with bubble B4, the HIP compiler driver 3940 generates the HIP / NVCC compilation instruction 3942 and transmits both the HIP / NVCC compilation instruction 3942 and the HIP source code 3930 to the CUDA compiler 3950. In at least one embodiment, and as depicted in connection with Fig. 39B, the HIP / NVCC compile command 3942 configures the CUDA compiler 3950 to compile the HIP source code 3930 using, without limitation, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment, and in response to the HIP / NVCC compile command 3942, the CUDA compiler 3950 generates host executable code 3970(1) and CUDA device executable code 3984 (depicted with the bubble labeled B5). In at least one embodiment, and as depicted in the bubble labeled B6, the host executable code 3970(1) and the CUDA device executable code 3984 may be executed on the CPU 3990 and the CUDA-enabled GPU 3994, respectively. In at least one embodiment, the device executable CUDA code 3984 comprises, without limitation, binary code.In at least one embodiment, the CUDA code 3984 executable on the device comprises, without limitation, PTX code and is further compiled at runtime into binary code for a particular target device.

[0332] A CUDA / HCC flow that may be implemented in at least one embodiment is depicted by solid lines and a series of bubbles labeled C1-C6. In at least one embodiment, and as depicted in the bubble labeled C1, the CUDA-HIP translation tool 3920 receives the CUDA source code 3910. In at least one embodiment, and as depicted in the bubble labeled C2, the CUDA-HIP translation tool 3920 translates the CUDA source code 3910 into the HIP source code 3930. In at least one embodiment, and as depicted in bubble C3, the HIP compiler 3940 receives the HIP source code 3930 and determines that the target device 3946 is not CUDA-capable.

[0333] In at least one embodiment, the HIP compiler driver 3940 generates the HIP / HCC compilation command 3944 and transmits both the HIP / HCC compilation command 3944 and the HIP source code 3930 to the HCC 3960 (depicted with bubble C4). In at least one embodiment, and as described in connection with Fig. 39C, the HIP / HCC compile command 3944 configures the HCC 3960 to compile the HIP source code 3930 using, without limitation, an HCC header and a HIP / HCC runtime library. In at least one embodiment, and in response to the HIP / HCC compile command 3944, the HCC 3960 generates host-executable code 3970(2) and device-executable HCC code 3982 (depicted with bubble C5). In at least one embodiment, and as depicted with the bubble labeled C6, the host-executable code 3970(2) and the device-executable code 3982 may be executed on the CPU 3990 and the GPU 3992, respectively.

[0334] In at least one embodiment, after translating the CUDA source code 3910 into the HIP source code 3930, the HIP compiler driver 3940 can then be used to generate executable code for either the CUDA-capable GPU 3994 or the GPU 3992 without re-executing the CUDA-HIP translation tool 3920. In at least one embodiment, the CUDA-HIP translation tool 3920 translates the CUDA source code 3910 into HIP source code 3930, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3940 then configures the HCC 3960 to generate host executable code 3970(2) and the HCC device executable code 3982 based on the HIP source code 3930.In at least one embodiment, the HIP compiler driver 3940 then configures the CUDA compiler 3950 to generate host executable code 3970(1) and CUDA device executable code 3984 based on the stored HIP source code 3930.

[0335] Fig. 39B shows a system 3904 configured to run the CUDA source code 3910 from Fig. 39A using a CPU 3990 and a CUDA-capable GPU 3994 in accordance with at least one embodiment. In at least one embodiment, the system 3904 includes, without limitation, the CUDA source code 3910, the CUDA-to-HIP translation tool 3920, the HIP source code 3930, the HIP compiler driver 3940, the CUDA compiler 3950, the host executable code 3970(1), the host executable CUDA device compiler 3984, the CPU 3990, and the CUDA-capable GPU 3994.

[0336] In at least one embodiment, and as previously described herein in connection with Fig. 39A, the CUDA source code 3910 includes, without limitation, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, the CUDA source code 3910 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0337] In at least one embodiment, the CUDA-to-HIP translation tool 3920 translates the CUDA source code 3910 into the HIP source code 3930. In at least one embodiment, the CUDA-to-HIP translation tool 3920 converts each kernel call in the CUDA source code 3910 from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in the CUDA source code 3910 into any number of other functionally similar HIP calls.

[0338] In at least one embodiment, the HIP compiler driver 3940 determines that the target device 3946 is CUDA-capable and generates a HIP / NVCC compilation command 3942. In at least one embodiment, the HIP compiler driver 3940 then configures the CUDA compiler 3950 via the HIP / NVCC compilation command 3942 to compile HIP source code 3930. In at least one embodiment, the HIP compiler driver 3940 provides access to a HIP-to-CUDA translation header 3952 as part of the configuration of the CUDA compiler 3950. In at least one embodiment, the HIP-to-CUDA translation header 3952 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs.In at least one embodiment, the CUDA compiler 3950 uses the HIP-CUDA translation header 3952 in conjunction with a CUDA runtime library 3954 corresponding to the CUDA runtime API 3902 to generate host executable code 3970(1) and device executable code 3984. In at least one embodiment, the host executable code 3970(1) and the CUDA device executable code 3984 may then be executed on the CPU 3990 and the CUDA-enabled GPU 3994, respectively. In at least one embodiment, the device executable code 3984 comprises, without limitation, binary code. In at least one embodiment, the device executable code 3984 comprises, without limitation, PTX code and is further compiled at runtime into binary code for a particular target device.

[0339] Fig. 39C shows a system 3906 configured to run CUDA source code 3910 from Fig. 39A using a CPU 3990 and a non-CUDA-capable GPU 3992 according to at least one embodiment. In at least one embodiment, the system 3906 includes, without limitation, the CUDA source code 3910, the CUDA-to-HIP translation tool 3920, the HIP source code 3930, the HIP compiler driver 3940, the HCC 3960, the host executable code 3970(2), the HCC host executable code 3982, the CPU 3990, and the GPU 3992.

[0340] In at least one embodiment, and as previously described herein in connection with Fig. 39A, the CUDA source code 3910 includes, without limitation, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, the CUDA source code 3910 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0341] In at least one embodiment, the CUDA-to-HIP translation tool 3920 translates the CUDA source code 3910 into the HIP source code 3930. In at least one embodiment, the CUDA-to-HIP translation tool 3920 converts each kernel call in the CUDA source code 3910 from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in the source code 3910 into any number of other functionally similar HIP calls.

[0342] In at least one embodiment, the HIP compiler driver 3940 then determines that the target device 3946 is not CUDA-capable and generates the HIP / HCC compilation command 3944. In at least one embodiment, the HIP compiler driver 3940 then configures HCC 3960 to execute the HIP / HCC compilation command 3944 to compile the HIP source code 3930. In at least one embodiment, the HIP / HCC compilation command 3944 configures HCC 3960 to use, without limitation, a HIP / HCC runtime library 3958 and an HCC header 3956 to generate host executable code 3970(2) and device executable code 3982. In at least one em...

Claims

[1] Processor comprising: one or more circuits for executing an application programming interface (API) to cause encrypted information to be decrypted based at least in part on one or more encryption algorithm indicators. [2] The processor of claim 1, wherein the one or more encryption algorithm indicators are for identifying one or more salts. [3] The processor of claim 1, wherein execution of the API further maps encryption algorithm identifiers to be generated to salts. [4] The processor of claim 1, wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms. [5] The processor of claim 1, wherein the one or more encryption algorithm indicators identify one or more salts usable to decrypt the encrypted information. [6] The processor of claim 1, wherein the one or more encryption algorithm indicators identify cryptographic information usable for decrypting the encrypted information for providing information, and wherein the cryptographic information is not accessible outside of software for using the information. [7] The processor of claim 1, wherein the execution of the API is to decrypt the encrypted information to provide decrypted information, such that at least both cryptographic information accessible to a user and cryptographic information not accessible outside of software for using the decrypted information are to be used to decrypt the encrypted information. [8] The processor of claim 1, wherein execution of the API further results in the encrypted information being decrypted using at least one user key and an encryption algorithm indicated by the one or more encryption algorithm indicators. [9] Method comprising: Executing an application programming interface (API) to cause information to be decrypted based at least in part on one or more encryption algorithm indicators. [10] The method of claim 9, wherein the one or more encryption algorithm indicators are for identifying one or more salts. [11] The method of claim 9, wherein the execution of the API further causes an assignment of encryption algorithm identifiers to salts to be generated. [12] The method of claim 9, wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms. [13] The method of claim 9, wherein the one or more encryption algorithm indicators identify one or more salts usable to decrypt the information. [14] The method of claim 9, wherein the one or more encryption algorithm indicators identify cryptographic information usable for decrypting the encrypted information to provide decrypted information, and wherein the cryptographic information is not accessible outside of software to use the information. [15] System comprising: one or more processors for executing an application programming interface (API) to cause information to be decrypted based at least in part on one or more encryption algorithm indicators. [16] The system of claim 15, wherein the one or more encryption algorithm indicators are for identifying one or more salts. [17] The system of claim 15, wherein execution of the API further causes identifications of encryption algorithms to be assigned to salts to be generated. [18] The system of claim 15, wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms. [19] The system of claim 15, wherein the one or more encryption algorithm indicators identify one or more salts usable to decrypt the information. [20] The system of claim 15, wherein the execution of the API is to decrypt the information, such that at least both cryptographic information accessible to a user and cryptographic information not accessible outside of software are used to decrypt the information.

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