SYSTEM, METHOD AND DEVICE FOR SUPPORTING A MULTI-MODE AMPLIFIER FOR MULTIPLE WIRELESS COMMUNICATION PROTOCOLS

Abstract

In one aspect, a device comprises: a dual-mode power amplifier for amplifying a first radio frequency (RF) signal of a first wireless protocol according to a linear operating mode and for amplifying a second RF signal of a second wireless protocol according to a non-linear operating mode; at least one digital feedback circuit coupled to the power amplifier, wherein the at least one digital feedback circuit provides feedback information; and a controller for controlling the power level of the dual-mode power amplifier, at least partially based on the feedback information.

Description

background

[0001] As the number of wireless devices continues to grow, there is a significant need for wireless transceivers capable of operating under multiple wireless communication protocols. However, integrating separate circuitry into a single transceiver to support multiple protocols incurs undesirable costs in terms of size, power consumption, and complexity. And, of course, providing separate transceivers for separate protocols also leads to additional component costs and similar issues related to size, power consumption, and complexity. Summary of the invention

[0002] In one aspect, a device comprises: a dual-mode power amplifier to amplify a first radio frequency (RF) signal of a first wireless protocol according to a linear operating mode and to amplify a second RF signal of a second wireless protocol according to a non-linear operating mode; at least one digital feedback circuit coupled to the power amplifier, wherein the at least one digital feedback circuit provides feedback information; and a controller to control a power level of the dual-mode power amplifier at least partially based on the feedback information.

[0003] In one embodiment, the at least one digital feedback circuit comprises an envelope detector comprising: a comparator for comparing a measure of the first RF signal with a reference value and outputting a digital value based on the comparison; a digital filter coupled to the comparator, which outputs the feedback information, at least partially based on the digital value, which includes a root mean square of the first RF signal.In this or any other implementation, the at least one digital feedback circuit comprises a current detector, comprising: a comparator to compare a first value, representative of a current output from a voltage regulator coupled to the dual-mode power amplifier, with a reference value and to output a digital value based on the comparison; and a digital filter coupled to the comparator, which outputs, at least partially, the feedback information comprising the current output of the voltage regulator based on the digital value.

[0004] In one implementation, the controller should determine a correction value for the dual-mode power amplifier, based at least partially on feedback information received during a preamble section of a first packet and at least one stored calibration value. The controller should: calculate a gain change based on a voltage value from the feedback information and a first calibration value from non-volatile memory; calculate a difference between a current value from the feedback information and a second calibration value from the non-volatile memory; determine a load gain at least partially based on this difference; and determine the correction value based on the gain change and the load gain.

[0005] In one or more embodiments, the controller shall apply the correction value for a second packet after the first packet. The controller shall apply the correction value for the second packet by updating a level of digital data of the second packet. The dual-mode power amplifier may comprise a plurality of disks, wherein a section of the plurality of disks is to be reused in both the linear and nonlinear operating modes. The controller shall update a number of active disks of the plurality of disks, at least partially based on the feedback information.

[0006] In another aspect, a method comprises: amplifying a first RF signal of a first wireless protocol in a power amplifier of a wireless device operating in a linear mode; amplifying a second RF signal of a second wireless protocol in the power amplifier operating in a nonlinear mode; and controlling a programmable impedance circuit coupled to an output of the power amplifier, at least partially based on a power level of the power amplifier.

[0007] In one embodiment, the method further comprises: digitally measuring a voltage at the output of the power amplifier via a first digital detector during a preamble section of a first packet; and digitally measuring the current output of a voltage regulator supplying the power amplifier with an operating voltage via a second digital detector during the preamble section of the first packet. The method may further comprise: determining a gain calibration for the power amplifier, at least partially based on the voltage, current, and one or more calibration values ​​stored in non-volatile memory; and applying the gain calibration to the power amplifier during a second packet.

[0008] In an implementation, applying gain calibration includes one or more of the following: updating a level of digital data of the second packet; controlling the programmable impedance circuit; and / or, updating a number of the multiple disks to be activated if the power amplifier includes a plurality of disks.

[0009] In one embodiment, if the power amplifier comprises a plurality of disks, the method further comprises: amplifying the second RF signal of the second wireless protocol in a first number of disks of the plurality of disks of the power amplifier operating in nonlinear mode; and amplifying the first RF signal of the first wireless protocol in a second number of disks of the plurality of disks of the power amplifier operating in linear mode, wherein at least some of the first number of disks are included in the second number of disks. The method may further comprise: controlling the programmable impedance circuit to have a first impedance level when the first RF signal is amplified; and controlling the programmable impedance circuit to have a second impedance level when the second RF signal is amplified.

[0010] In another aspect, a system comprises: an antenna for transmitting and receiving RF signals; and a multiprotocol transceiver coupled to the antenna. The multiprotocol transceiver comprises: a dual-mode power amplifier to amplify a first RF signal of a first wireless protocol according to a linear operating mode and to amplify a second RF signal of a second wireless protocol according to a non-linear operating mode; an impedance transformation circuit coupled to an output of the dual-mode power amplifier; at least one digital feedback detector coupled to the dual-mode power amplifier, wherein the at least one digital feedback detector provides feedback information; and a controller to control an impedance of the impedance transformation circuit, at least partially, based on the feedback information.

[0011] In one embodiment, the system further comprises non-volatile memory for storing compensation data, wherein the compensation data includes a first compensation value associated with the output voltage of the dual-mode power amplifier and a second compensation value associated with the load current of the dual-mode power amplifier. The controller can be configured to further control the impedance of the impedance transformation circuit based on at least one of the first compensation values ​​or the second compensation value. Brief description of the drawings Fig. Figure 1 is a diagram at a high level of abstraction of a multimode wireless transmitter according to one embodiment. Fig. Figure 2 is a more detailed representation of a transmission path according to one embodiment. Fig. Figure 3 is a schematic diagram of a circuit with a digital-to-analog converter (DAC) according to one embodiment. Fig. Figure 4 is a schematic diagram of another aspect of a transmission path architecture according to one embodiment. Fig. Figure 5 is a schematic diagram of another aspect of a transmission path architecture according to one embodiment. Fig. Figure 6 is a schematic diagram of a plurality of driver disks of a dual-mode power amplifier according to one embodiment. Fig. Figure 7A is a schematic diagram of a digital encapsulation detector according to one embodiment. Fig. Figure 7B is a schematic diagram of a digital encapsulation detector according to a further embodiment. Fig. Figure 8 is a schematic diagram of a digital current detector according to one embodiment. Fig. Figure 9 is a flowchart of a process according to one embodiment. Fig. Figure 10 is a block diagram of a representative integrated circuit according to one embodiment. Fig. Figure 11 is a diagram at a high level of abstraction of a network according to one embodiment. Detailed description

[0012] In various embodiments, a wireless transmitter architecture is provided that includes specific transmitting circuitry capable of operating in multiple modes. This means that this circuitry, which, as described herein, comprises a power amplifier (PA) and an impedance transformer circuit, can be dynamically controlled to support multiple wireless protocols with varying requirements. For example, a first wireless protocol might require the use of a linear transmitter (to meet linearity requirements), while a second wireless protocol might require the use of a nonlinear transmitter (for improved efficiency).

[0013] As non-exhaustive examples, this transmit architecture can, in one implementation, share circuitry for use with Bluetooth Classic (BTC) and Bluetooth Low Energy (BLE) protocols. The transmit architecture is configured to operate at different saturated power levels for these various protocols. In embodiments, the multimode transmitter can be implemented with a reduced chip area and optimized efficiency for each protocol and power level, as described herein.

[0014] In one or more embodiments, a transmitter can support multiple operating modes (such as different communication protocols) and optimize efficiency across different power levels. To achieve such operation, a dual-mode power amplifier (PA) can be implemented to send a constant envelope-modulated signal when configured as a non-linear PA and a variable envelope-modulated signal when configured as a linear PA. The PA output is coupled to a programmable inductor, which optimizes PA efficiency at different power levels. As will be described later, additional transmitter circuitry can help reduce size, including a baseband R-2R digital-to-analog converter (DAC), sharing the PA across multiple protocols, and eliminating the need for a balun.

[0015] With reference to Fig. Figure 1 shows a diagram at a high level of abstraction of a multimode wireless transmitter according to one embodiment. In the high-level representation of Fig. Figure 1 shows a device 100 according to the invention 100, which comprises only certain circuits. However, it should be noted that the device 100 can be a multiprotocol transceiver in various embodiments, such as one that can be implemented on one or more semiconductor chips of a single integrated circuit (IC).

[0016] In other embodiments, the device 100 can be a specific wireless device containing such a transceiver. For example, in various applications, the device 100 can be an Internet of Things (IoT) device, a smartphone, a tablet computer, an access point, a wireless router, a gateway device, or one of many other such wireless devices.

[0017] In any case, the device comprises 100 in the Fig. Figure 1 shows a high-level abstraction low-power wireless (LPW) modem 110 capable of performing various PHY operations, including encoding and decoding operations for multiple wireless protocols, in both transmit and receive directions. For the sake of simplicity, the representation and explanation are shown in Fig. Figure 1 shows only the transmit path. However, in typical applications, such as a multiprotocol transceiver, a receiver path circuit is also present.

[0018] As shown, separate transmission paths 120 and 150 are available. In the embodiment of Fig. In the embodiment of Fig. Figure 1 shows a dual-mode transmitter for communication according to BLE and BTC communication protocols; the embodiments are not limited in this respect. In other embodiments, the transmission paths can be used for other wireless protocols, for example, combinations of a Bluetooth protocol, Wi-Fi, Wi-SUN, and others. For example, the dual-mode transmitter can be configured as a linear transmitter to send Wi-Fi signals or other non-constant envelopes in addition to BTC signals, and it can be configured as a non-linear transmitter to send Zigbee, Thread, or other constant envelopes in addition to BLE signals.

[0019] Starting with the transmit path 120, the baseband signals output by the modem 110 are provided as a complex data stream, which is formed from I and Q data and is processed in corresponding digital-to-analog converters (DACs) 122. I,Qis converted into analog form. The baseband signals are then processed by a complex mixer 125. (I,Q) The signals are upconverted to a specific radio frequency (RF). As shown, mixer 125 converts the signals using a signal to send a local oscillator frequency clock signal (Flotx).

[0020] Referring to Fig. 1. The resulting RF signals pass through a multiplexer (shown as logic circuit 130), which, as shown, can be controlled via this LO clock signal. The RF signal is then supplied to the BLE transmitter circuit 140, which, as shown, drives pre-drivers 1420 and drivers, also referred to here as PAs 144. 0,1Designated, includes. These various pre-drivers and drivers can be configured to operate at different power levels. For example, PA 1440 can be implemented as a 0 dBm PA and PA 1441 as a 20 dBm PA. Depending on its installation in a particular device, it is possible that only one of these PAs is active, and only this active PA is coupled to the output terminal 190 via a specific set of bond wires 1851 and 1852. More precisely, in the representation of Fig. 1 The bond wire 1852 is shown as a dashed line, indicating that there is no bond wire present here, so PA 1441 is configured to be inactive.

[0021] It should also be noted that the BLE-RF signal is also provided to another BLE pre-driver 1422, which, as shown, is integrated into the transmit path 150. However, it should be noted that the position of the pre-driver 1422 is not critical and this pre-driver can just as easily be located in the transmit path 120, depending on the layout of a particular device.

[0022] As in Fig. As shown in Figure 1, an RF signal output by PA 1440 is coupled to an output terminal 1841 via the output inductor L2. Note the presence of a programmable capacitor CP, coupled to inductor L4, and a programmable filter formed by a series-connected capacitor C1 and a resistor R1. An RF signal output by PA 1441 is converted into a single-ended signal via a balun formed by a transformer T1. A filter circuit is also coupled to output terminal 1842, namely a series-connected inductor L5 and a capacitor C2.

[0023] At a high level of abstraction, the transmit path 150 can include similar circuits to those described above in relation to the transmit path 110, for example DACs 152. I,Q and mixer 155 I,Q As shown, low-pass filters (LPFs) are 154 I,Q between DACs 152 and mixer 155 I,Qcoupled.

[0024] It should also be noted that there are 150 variations and additional transmit circuits in the transmit path. For example, mixer 155 I,Q This is coupled with a BTC pre-driver 160, which outputs a differential signal that is then converted back into a single-ended signal via a transformer T2. Next, a dual-mode (DM) PA 170 is coupled to receive both BLE and BTC-RF signals, with a specific signal stream being active at any given time, as will be explained in more detail later.

[0025] Although the dual-mode power amplifier 170 in Fig. As depicted in Figure 1 at a high level, it should be noted that in practical implementations it can consist of multiple units or disks that can be individually controlled to output a transmit RF signal at a desired power level. As shown, the dual-mode PA 170 is a single-ended PA that outputs a single-ended amplified RF signal.

[0026] Additional circuitry is provided at the output of the power amplifier 170, namely a harmonic filter circuit 175, which can filter certain harmonics (e.g., H3 harmonics for BLE mode), and a switchable impedance transformer 180, which can be dynamically controlled depending on the desired power level. In one embodiment, the harmonic filter circuit 175 comprises a series-connected inductor L1 and a programmable capacitor C3, which can be controlled to reduce or eliminate H3 harmonics that may fall within a GPS band. Furthermore, the coupling capacitor CC acts 1,2 as DC blockers and direct currents to an output pin 1843.

[0027] Depending on an active wireless protocol, the dual-mode PA 170 can amplify and output phase-modulated signals and amplitude-modulated (AM)-PM-modulated signals with reduced losses and area requirements. Furthermore, the impedance transformer 180, which can be implemented as a programmable shunt inductor, can be dynamically controlled to achieve different power amplifier impedances. In the embodiment of Fig. Figure 1 describes the switchable impedance transformer 180 comprising series-coupled inductors L2 and L3, which can be programmably bridged via switches S1 and S2, which can be implemented as metal-oxide-semiconductor field-effect transistors (MOSFETs). As described herein, the impedance transformer 180 can be controlled to provide suitable power control and impedance matching for the various modes of the DM-PA 170. In one particular implementation, the impedance transformer 180 can be dynamically controlled to provide an impedance between approximately 5 and 20 ohms. In this way, the efficiency of the PA 170 can be optimized for different power levels.

[0028] Finally, as also in Fig. As shown in Figure 1, one or more feedback detectors 172 are coupled to the output of the PA 170 to monitor current and / or envelope information and provide this feedback information to the modem 110. As further described below, these detectors can be implemented digitally in certain embodiments. In turn, a controller (contained in or coupled to the modem 110, but not shown for the sake of simplicity) can determine suitable power levels for the drivers 142 and / or the power amplifiers 144, 170. Although this is not shown in the embodiment of Fig. As shown at this high level, many variations and alternatives are possible.

[0029] With reference to Fig. Figure 2 shows a more detailed representation of a transmission path according to one embodiment. More precisely, as shown in Fig. 2 shown, in which Fig. The general view of transmitter 200 shown in section 2 is implemented as a BTC transmission path. Of course, the same transmission path, as explained above, can also be used with other wireless protocols. At a high level, in Fig. 2 a similar circuit to that in transmission path 150 of Fig. 1 is shown, so the above discussion also applies here (it should be noted that the same components with the same numbers as in Fig. 1 are shown, however with the series “200”).

[0030] In one embodiment, DACs 252 can be implemented as 11-bit DACs to receive incoming 11-bit data in the I and Q paths. Furthermore, DACs 252 will be implemented as segmented R-2R DACs. This arrangement of DACs 252 significantly reduces the chip area (compared to current-steering topologies with the same resolution). The resulting analog signals are then fed to the corresponding LPFs 254. I,Qprovided. In one embodiment, LPFs 254 can be implemented as second-order smoke filters with a Butterworth magnitude response.

[0031] As shown, the quadrature signals are fed to a passive mixer 255. I,Q The mixers 255 can be implemented differentially with bootstrap NMOS switches. In various embodiments, the mixers 255 can be implemented as passive voltage-controlled mixers, which reduces the area and power consumption (compared to a Gilbert cell-based mixer). The resulting up-converted signals, now in the RF range, are then provided to a pre-driver 260. In one embodiment, the pre-driver 260 can be implemented as a complementary class AB pre-driver.

[0032] The resulting driven signals are provided to a transformer T2, which, as shown on the secondary side, acts as a balun to forward single-ended signals to a switch arrangement 265, which, as explained below, can be implemented with NMOS switches.

[0033] It should also be noted that frequency tuning can be achieved via a corresponding shunt-coupled capacitor C5, which can be implemented as a programmable capacitor. Additionally, another shunt-coupled capacitor C6, also implemented as a programmable capacitor, is configured to provide load capacitance compensation based on an active parameter of a PA 270, which is implemented as a dual-mode driver.

[0034] Referring to Fig. 2. Incoming signals from a BLE transmit path, namely BLE-RF signals, are also provided to the dual-mode driver 270, for example via another pre-driver (in Fig. (2 omitted for simplification). Based on an incoming enable signal, a selected number of switches of the switch assembly 265 and corresponding disks of the driver 270 (and elements of the programmable capacitor C6) can be enabled. The enabled disks amplify the corresponding RF signals, which are output via an output terminal 284 through a bond connection 285 to an RF input / output (RFIO) terminal 290.

[0035] As further shown, the harmonic trap 275 is implemented with a series connection of an inductor L1 and a capacitor C3. In BTC mode, capacitor C3 is bypassed to suppress harmonics, specifically an H3 harmonic. Conversely, the impedance transformer 280 can be programmably controlled based on the desired power level. For example, if a desired saturation power level (Psat) is 10 dBm, the inductors of the impedance transformer 280 can be deactivated. Continuing this example, if a desired Psat is 13 dBm, a higher value for the inductors is achieved by bypassing inductor L3 of the impedance transformer 280. And further, continuing this example, if a desired Psat is 16 dBm, inductor L2 of the impedance transformer 280 can be bypassed. Of course, other control schemes are possible in other examples.

[0036] In one or more embodiments, this programmable control can dynamically control the impedance (namely the output impedance at a node of the driver 270) via the impedance transformer 280 so that it lies, for example, between about 16 ohms and about 5 ohms.

[0037] As further shown, a supply voltage is provided to the PA 270 via a low-dropout (LDO) voltage regulator 276. An LDO current can be measured via a current detector 2721, which, as further described below, can be implemented as a digital detector. Similarly, an envelope detector 2722 can be implemented as a digital detector to measure the voltage level of the output RF signal, as further described below. Although this is not the case in the embodiment of Fig. Since 2 is shown at this high level, many variations and alternatives are possible.

[0038] With reference to Fig. Figure 3 shows a schematic diagram of a circuit comprising a digital-to-analog converter (DAC) according to one embodiment. As shown in Fig. As shown in Figure 3, the circuit 300, which can be part of a transmission path, includes a DAC 310. As shown in Fig. As shown in Figure 3, the DAC 310 is implemented as a segmented R-2R DAC with a current-providing mode. As shown, an incoming digital word (d[10:0]) is provided via a buffer 305 to a segmented decoder 312. The decoder 312 drives a set of D-type flip-flops 320, which, as shown, are clocked by a clock signal (Fclkin) received via an inverter 314. As further shown, this clock signal is output as an output clock signal (Fclkout) via another inverter 315.

[0039] Referring to Fig. 3. The outputs of flip-flops 320 drive a set of branches of corresponding resistor ladders, formed from 2R resistors connected in series and R resistors connected in parallel. As can be seen, the individual bits of the bitstream are passed through sets of buffers 325. 0,1 coupled to the resistance conductors . In a segmented design, 8 bits are passed directly through these buffers, while 3 bits are segmented, e.g. with thermometer weighting.

[0040] In some embodiments, the segmentation can be a function of the DAC output resistance, with greater segmentation resulting in a shorter settling time, lower resistance, higher filter capacitance, and higher sink / source current capability of the operational amplifier. It should be noted that a reference voltage (vref_DAC) can be generated by a reference voltage generator, such as an LDO regulator, which can be provided per channel (i.e., per I- and Q-DAC). In contrast, an LDO providing a supply voltage for digital circuitry (dvdd_dac) can be shared by the I- and Q-DACs.

[0041] Referring to Fig. The analog output of DAC 310 is provided to filter 350, which can be implemented as a second-order filter with a Butterworth-Rauch architecture, via common mode paths coupled together by capacitor C10. As also shown, programmable capacitors C11 are coupled to the nodes of filter 350. The analog signals are then fed into operational amplifier 355 via programmable resistors R10. Operational amplifier 355 outputs a filtered signal through a corresponding RC filter formed from resistors Rhf and capacitors Chf. In one embodiment, an output filter formed from capacitors CHF and resistors RHF implements a low-pass filter at 800 MHz to prevent filter noise from entering a GPS band.

[0042] Furthermore, as shown, the filter 350 implements a feedback loop featuring programmable feedback resistors R11 and programmable feedback capacitors C12. This feedback loop allows the common mode to remain centered. It should be noted that the input signal to the operational amplifier 355 has a fixed common mode. Capacitor C10 can improve out-of-band noise. Although in Fig. Not shown in Figure 3, it should be noted that the analog output signals are provided to a mixer to be up-converted to RF levels.

[0043] In Fig. Figure 4 is a schematic diagram illustrating further aspects of a transmission path architecture according to one embodiment. As in Fig. As shown in Figure 4, the circuit 400 includes a mixer 455, which upconverts the analog signals to RF levels. These RF signals are then provided to a driver 460, which forwards the outputs to a switch assembly 465.

[0044] Starting with mixer 455, implemented as a passive mixer, incoming filtered signals (FILT_OUT_M, P) are coupled to corresponding source terminals of metal-oxide-semiconductor field-effect transistors (MOSFETs) M1, which, as shown, are implemented as N-channel MOSFETs (NMOS). The filtered signal is also coupled to a gate terminal of the NMOS M1 at a midpoint between a series resistor RM and a capacitor CM. As can be seen, the capacitor CM is coupled to a buffer 452 (powered by an LDO 415), which outputs clock signals to perform the step-up to RF level. In particular, mixer 455 is implemented to receive, via buffer 452, 25% of the phases of the Local Oscillator (LO) clock signal that can be received by a clock generator and used to control a switching of the given phases to output an RF output signal (RF_OUT_P, M).In the embodiment of . Fig. 4. Mixer 455 is provided as a fully differential passive mixer with 25% LO stages to drive the driver 460. By providing a passive mixer, power consumption can be reduced.

[0045] It should be noted that the specific implementation shown on the left side of Fig. 4 is shown as a simple set of switches in the middle of Fig. Figure 4 shows how to provide RF input signals to a driver 460. As shown, the driver 460 can be equipped with two units 461. 1-2As shown, each unit receives a corresponding RF signal, which is supplied via capacitors CP to the gate terminals of a pair of MOSFETs M2, M3, namely a P-channel MOSFET (PMOS) M2 and an NMOS M3. The jointly coupled drain terminals of the MOSFETs M2, M3 in turn drive a transformer T3, which is implemented as a balun, to supply a single-ended signal to corresponding stages of a switch array 465.

[0046] In the embodiment of Fig. 4. The driver 460 can be implemented as a complementary class AB driver. With this design, a double transconductance can be achieved for a given current. Furthermore, the driver 460 can reduce / eliminate the second harmonic distortion and serve to filter out the out-of-band noise of the baseband, mixer, and driver.

[0047] As further shown, a feedback loop is provided by a center tap of the primary side of transformer T3, which is coupled to a first input of an operational amplifier 462, the second input of which is coupled to receive a voltage from a resistor ladder formed by resistors R4 and R5. As shown, the operational amplifier 462 outputs a feedback voltage that is applied to the resistors RP of the driver 460 to keep the common-mode signal centered.

[0048] The switch arrangement 465 can be implemented to isolate the driver inputs while operating with low power and low noise linearity. This switch circuit can be provided in various embodiments to decouple driven RF signals from the pre-driver circuit to a dual-mode power amplifier when that signal path is inactive (e.g., as used for BTC communication). Such a switch circuit can be used to decouple pre-driver circuits like the pre-driver 460, since the presence of transformer T3 prevents isolation between the inputs.

[0049] As shown, the switch arrangement 465 can be combined with a set of individual switching units 466 1-12Switching units 466 are implemented, each controlled by a digital control signal (ctrl[11:0]) and (CTRL_b[11:0]). As shown, each switching unit 466 is implemented with a shunt NMOS M4 and a series NMOS M5, along with corresponding capacitors CS and resistors RS. When a particular switching unit 466 is active via an active CTRL control signal (and an inactive CTRL_b control signal) and receives an input from the driver 460 via transformer T3, a single-ended RF signal is coupled via NMOS M5 and output as RFN_IN_BTC. NMOS M4 can be controlled to enable automatic tuning of transformer T3 along with the output stage disks.It should be noted that a corresponding RF signal is output via additional switching units 466. It should also be noted that the outputs of the switching arrangement 465 are provided as inputs for one or more disks of a dual-mode power amplifier, as described herein.

[0050] With reference to Fig. Figure 5 is a schematic diagram of additional aspects of a transmission path architecture according to one embodiment. As shown in Fig. As shown in Figure 5, the circuit 500 comprises a driver 560, which outputs driven RF signals to a switching arrangement 565, which forwards the RF signals switchably to a dual-mode PA 570. As shown, the driver 560 (formed from the driver stages 561) can 1,2 and the switching arrangement 565 (formed from the switching units 566 1a-12a / 1b-12b ) as above in Fig. 4 can be configured as described and is therefore not explained further here (it should be noted that the in Fig. The four specific lists shown are for the purpose of simplifying the presentation in Fig. 5 are not included, but the same components are present).

[0051] In Fig. Figure 5 shows a detailed implementation of a single slice of a dual-mode PA 570. More precisely, the driver 570, namely the dual-mode PA, is shown with a plurality of slices 571. 1-192 implemented. Although in the embodiment of Fig. While Figure 5 shows a specific number of disks, the number of disks can vary. As shown, disk 571 receives incoming RF signals from both the BTC and BLE paths (namely RF(P,N)_IN_BTC and RF_IN_BLE). These RF signals are coupled via capacitors CD to the corresponding gate terminals of the MOSFETs, namely the PMOS device M10 and the NMOS device M12. As shown, a specific disk can be controlled via a series of switches S10-S13 to control MOSFETs M10 and M13, which, when activated, activate the disk (and vice versa). Additionally, bias signals VBP and VBN can be driven by separate bias blocks to bias the MOSFETs according to the operating mode.

[0052] It should be noted that in this arrangement, each disk 571 can be reused for both BTC and BLE modes, thus reducing the circuit module size. When a particular disk 571 is activated, it outputs an amplified RF signal RFout, which is combined with similar RF output signals from other disks to form an amplified RF output signal.

[0053] It should be noted that in some implementations only a certain number of disks are used for BLE mode, while potentially all disks can be used for BTC mode, depending on performance requirements. As a specific example, half of the disks might be available for BLE mode, while all disks are available for BTC mode.

[0054] With reference to Fig. Figure 6 is a schematic diagram of several driver disks 671 1,2A dual-mode PA 670 is shown according to one embodiment. In this implementation, disk 6711 can be active in both BTC and BLE modes, while disk 6712 is only active in BTC mode. This is evident because the BLE inputs provided to disk 6712 are driven by a dummy driver 660. BLE2 originate from. It should be noted that this driver is controlled in such a way that it remains in the tri-state state via the fixed pull-up of PMOS M23 and the pull-down of M24. In contrast, the BLE driver 660 BLE1 It can be dynamically controlled to forward a BLE-RF signal for input to the 6711 disk when activated via corresponding enable signals coupled to the gate terminals of MOSFETs M21 and M22. And when BLE communication is inactive, the 660 driver can BLE1 be put into a tri-state state to present a high impedance to the PA 670.

[0055] As in Fig. As further shown in section 6, a switch circuit 665 is shown. 1,2 (which takes the form of a switch arrangement 565 from Fig. 5 can be assumed) provided, which can be controlled to send BTC-RF signals to the disks 671 1,2 to forward.

[0056] Furthermore, reference is made to the dual-mode driver 670 and the amplified RF outputs of the disks 671. 1,2 are coupled to each other via a node 675 (which can also be coupled to the outputs of all other activated disks of the driver 670). Although this is the embodiment of Fig. As shown in Figure 6 at this high level of abstraction, many variations and alternatives are possible.

[0057] As explained above, feedback detectors coupled to the output of a dual-mode power amplifier can be implemented as digital detectors to simplify implementation. Referring to Fig. Figure 7A shows a schematic diagram of a digital envelope detector according to one embodiment. As shown in Fig. As shown in Figure 7A, the detector 700 is coupled in such a way that it receives an RF signal (RFin), which may be the RF signal output by the PA (e.g., an output voltage at the drain terminals of the output MOSFETs of the activated disks of the PA).

[0058] As shown, this RF input is coupled via capacitor C30 to the gate terminals of a pair of jointly coupled NMOS devices M31a and M31b. The NMOS devices M31 have jointly coupled source terminals connected to a reference voltage node and jointly coupled drain terminals connected to a PMOS device M30, specifically to the gate and source terminals of the diode-connected PMOS device M30. The PMOS device M30 is, in turn, coupled via resistor R31 to another PMOS device M33 via jointly coupled gate terminals. The PMOS device M33 has a drain terminal connected to a feedback path.

[0059] As further shown, the common drain and gate terminals of the PMOS M33 are coupled to a first input of an operational amplifier 705, which compares this signal, representative of the RF signal current (Is), with a feedback signal (Ifb) received via a feedback path coupled to an output of a level detector 710. The operational amplifier 705 is configured to output a comparison signal based on the incoming signals. This comparison signal is provided to the level detector 710, which digitizes the input into a digital value (0 or 1, depending on the comparison result) and provides a pulse density.

[0060] With further reference to Fig. The digital value representing the detected output voltage is provided to a digital filter consisting of an accumulator 720 and a delay element 725, which is coupled to the accumulator 720 via feedback. It should be noted that the digital filter may have different topologies in other implementations. The digital value output by the digital filter is proportional to the PA output voltage (rMS squared value).

[0061] Based on the digital value output by the level detector 710, a series of switches S30-S33 are controlled to apply either a bias voltage or a positive / negative reference voltage to the gate terminals of the NMOS devices M32. In this way, the NMOS devices M32 force the feedback current (Ifb) towards the value of the signal current (Is).

[0062] Thus, the envelope detector 700 is configured to generate a digital output signal proportional to the RF output signal (with respect to the square of the envelope amplitude). In one embodiment, the output of the level detector 710 is a single-bit value (or can be a multi-bit value) provided to the digital filter. Because the envelope detector 700 outputs a pre-digitized measurement, the envelope measurement can be performed at any time and for as long as required without sharing the ADC with other circuitry.

[0063] In one embodiment, the encapsulation detector 700 receives the RF signal, which is output by a dual-mode power amplifier as Rfin = A(t)*cos(ωt+φ(t)), and generates a voltage measurement as Vdet_out = D = (A(t) / Vref / 2) 2 , where “D” is the density of “ones”.

[0064] In the embodiment of Fig. In 7A, the digital detector 700 is implemented as a voltage-mode detector, since the gate voltages of the NMOS components are M32 switches; however, due to the RC time constant at these gate terminals, switching can be relatively slow.

[0065] In another implementation, a digital encapsulation detector can be implemented as a current-mode detector. Referring to Fig. Figure 7B shows a schematic diagram of a digital encapsulation detector according to a further embodiment. In general, the detector 700' can be used in the same way as the detector 700 from Fig. 7A are implemented. It should be noted, however, that the differences lie in the switchable feedback, which in turn is coupled to a series of switches S34-S37 connected to the drain terminals of the MOSFETs M32. A-Care coupled. In this implementation, the drain currents generated by the M32 NMOS devices therefore switch, which enables fast switching because the voltages are fixed, and furthermore allows the impedance constraints for the reference and bias voltages to be relaxed. In other aspects, the Detector 700' can be implemented in the same way as the Detector 700.

[0066] With reference to Fig. Figure 8 shows a schematic diagram of a digital current detector according to one embodiment. In the embodiment of Fig. In section 8, the current detector 800 is configured to measure a current (LDO_OUT) output by an LDO 801, which provides a supply voltage for a dual-mode power amplifier (PA) as described herein. This load current allows an understanding of the load impedance. In this way, by sensing this current value, control can minimize gain or backoff operations, resulting in the operation of a dual-mode PA at or near an optimal (efficiency-related) power level.

[0067] As shown, the LDO current signal is coupled to a gate terminal of an NMOS device M41, which is coupled together with another NMOS device M42. These devices are in turn coupled to a diode-like PMOS device M43 and a PMOS device M44. The common drain terminals of the MOSFETs M42 and M44 are coupled to a gate terminal of a replication circuit that replicates the output stage circuit of the LDO regulator 801. More precisely, this replication circuit comprises a PMOS device M46 with a drain terminal coupled to a second input of an operational amplifier 805, and a PMOS device M47R, which is coupled via a drain terminal to a source terminal of the PMOS device M46R and a gate terminal of the NMOS device M42.These PMOS components thus function as a replication circuit for the corresponding circuit of the LDO regulator 801 (output stage circuit represented by PMOS components M47M and M46M, which generate a main current Im). Naturally, the LDO PMOS components are significantly larger than the replication PMOS components. Therefore, the measured current (Isns) is proportional to this main current.

[0068] As shown, the current detector 800 includes an operational amplifier 805, which compares the detected current (a measure of the LDO output current received at the second input of the operational amplifier 805) with a reference value. The operational amplifier 805 compares the signals and outputs a signal to a level detector 810, which provides a digital value to a digital filter consisting of an accumulator 820 and a delay element 825, which is coupled in feedback with the accumulator 820. Thus, the current detector 800 contains a similar digital circuit to that found in the voltage detector 700.

[0069] Here, however, the current detector 800 is configured to generate a digital output signal proportional to the LDO current, which in turn depends on a load impedance. In one embodiment, the output of the level detector 810 is a one-bit value (or can be a multi-bit value) provided to a digital filter. Because the current detector 800 outputs an already digitized measurement, this current measurement can be performed at any time and for as long as required without sharing the ADC with other circuitry.

[0070] During production testing, the digital detectors can be characterized to obtain characterization results that can be stored in non-volatile memory (e.g., flash or fuse circuitry) and then used during field operation. In one embodiment, a two-step process can be used for each detector, based at least partially on a known PA load impedance and a given power level for dual-mode operation. In one embodiment, the current detector calibration is a two-point calibration in which the LDO current consumption is varied (by changing the PA disks or the bias current). The two points allow for the calibration of the offset and gain error. In another embodiment, the encapsulation detector calibration is a four-point calibration in which two DC differential voltages with two different polarities are applied to the NMOS devices M31a / b (in Fig. 7A) are applied. The four measured outputs are used to compensate for the offset and gain error.

[0071] From this characterization, calibration data, such as voltage and current measurements, can be determined and stored. More precisely, this calibration data can be stored in non-volatile memory (e.g., flash memory or fuses) of the transceiver. In one embodiment, the calibration data for a given fixed impedance and power level can include a load current value (hereinafter referred to as "ildopte") and an output voltage (hereinafter referred to as "Vdrainpte").

[0072] During field operation, the PA gain can be measured during a preamble segment of a communication. In one embodiment, a PA drain voltage fluctuation (Vdrainpreamble) and a measured LDO current (ildopreamble) can be measured during the preamble using the digital detectors. Based on these measurements and the stored calibration values ​​from production tests (Vdrainpte and ildopte), a gain change (Gswing = Vdrainpreamble / Vdrainpte) and a current difference (Δildo = ildopte / ildopreamble) can be measured. Next, a load gain can be calculated as follows, in one embodiment: Gload = Δildo / k (where k is an empirically determined constant, e.g., 1.5 mA, which can be a digital value). Conversely, a gain correction can be determined as follows: Gcorrection = Gswing * Gload. This gain correction can be applied to the PA, e.g., in a subsequent package.Depending on the implementation, such gain correction can be performed by controlling a number of disks of the dual-mode PA to be activated, by providing digital I / Q values ​​to be fed into the transmit path, and / or by adjusting the output impedance via an impedance transformation circuit as described herein.

[0073] With reference to Fig. Figure 9 shows a flowchart of a process according to one embodiment. As in Fig. As shown in Figure 9, Method 900 is a method for dynamically calibrating the gain of a dual-mode power amplifier. In one or more embodiments, Method 900 can be performed by a controller of a wireless device that can execute instructions from firmware and / or software stored in non-volatile memory of the wireless device.

[0074] As shown, Method 900 begins with the measurement of a power amplifier output voltage and a load current (Block 910). In one embodiment, these measurements can be performed using digital detectors, as described herein, and during a preamble of a first packet. In one implementation, the output voltage can be measured based on a drain voltage of all active disks of the power amplifier, and the load current can be measured based on an LDO current provided by the power amplifier.

[0075] Next, a gain change can be calculated in block 920. More precisely, this gain change can be calculated based on the measured output voltage and the stored calibration data. As explained above, the stored calibration data, which can be retrieved from the device's non-volatile memory, includes a calibration output voltage. Subsequently, a current difference between the measured load current and the stored calibration data can be determined in block 930. As previously explained, the stored calibration data includes an LDO current.

[0076] Referring to Fig. In block 940, a load gain can be determined. This load gain can be based, at least partially, on this current difference. Subsequently, a gain correction can be calculated in block 950. In the embodiment of Fig. 9. This gain correction can be calculated based on the gain change and the gain load. In a specific implementation, the gain correction can be the product of the gain change and the gain load. Thus, a correction value for the gain correction is available at this point.

[0077] Due to timing issues, gain correction can be applied to the next communication packet (Block 960). Depending on the implementation and degree of gain correction, this gain compensation can be achieved by adjusting a number of active disks of the PA, controlling a level of digital I / Q values ​​provided on the transmit path, and / or adjusting an impedance level of an impedance transformer, as described herein. Although this is not the case in the embodiment of Fig. As is shown at this high level, many variations and alternatives are possible.

[0078] With reference to Fig. Figure 10 shows a block diagram of a representative integrated circuit 1000, which includes a dual-mode power amplifier described herein. In the Fig. In the embodiment shown in Figure 10, the integrated circuit 1000 can, for example, be a multimode wireless transceiver that can operate according to one or more wireless protocols (e.g., Wi-Fi, Bluetooth, BLE, IEEE 802.15.4, Matter, and / or Zigbee, among others) or another device that can be used in a variety of applications. In one or more embodiments, the Fig. The integrated circuit 1000 shown can be implemented on a single semiconductor chip or on separate chips for wireless communication, MCU computation, external flash memory and / or other IP blocks required to perform a variety of functions.

[0079] The integrated circuit 1000 can be included in a variety of devices, but for the purposes of discussion, it can be integrated into an IoT device. In the embodiment shown, the integrated circuit 1000 includes a memory system 1010, which in one embodiment can comprise volatile memory, such as RAM, and non-volatile memory, such as flash memory. Flash memory is a non-volatile storage medium that can store instructions and data.In embodiments, this memory can contain calibration data 10051 (including, but not limited to, PA drain voltage and LDO current measurements taken at a specific power level and impedance level during the production tests described above) and a calibration routine 10052 for performing dynamic field calibration using calibration data 10051 and measurements from digital detectors as described above, which can be executed on a main or host processor (implemented in at least one core of one or more digital cores 1020). The integrated circuit 1000 can also include a controller for the memory 1090.

[0080] The memory system 1010 is coupled via a bus 1050 to digital cores 1020, which may comprise one or more cores, coprocessors, and / or microcontrollers that function as processing units of the integrated circuit described herein. The digital cores 1020 can, in turn, be coupled to clock generators 1030, which may provide one or more phase-locked loops or other clock generator circuits to generate various clocks for use by circuits of the IC.

[0081] As further shown, the IC 1000 also includes power circuits 1040. Depending on the specific implementation, additional circuits may be present to provide various functions and interactions with external devices. Such circuits may include an interface circuit 1060, which provides a digital communication interface with additional circuits coupled to the IC 1000 via a link 1095. The IC 1000 may also include a security circuit 1070 to implement wireless security techniques.

[0082] Furthermore, as in Fig. Figure 10 shows a 1080 transceiver circuit provided to enable the transmission and reception of wireless signals, e.g., according to one or more local or long-range wireless communication schemes such as Matter, Zigbee, Bluetooth Classic, BLE, IEEE 802.11, IEEE 802.15.4, cellular communication, etc., using a dual-mode power amplifier and impedance transformation circuit as described herein. It should be noted that despite this general representation, many variations and alternatives are possible.

[0083] ICs, as described here, can be implemented in a wide variety of devices, as described above. With reference to Fig. Figure 11 shows a diagram at a high level of abstraction of a network according to one embodiment. As in Fig. As shown in Figure 11, a network 1100 comprises a variety of devices, including IoT devices, which may contain dual-mode PAs as described here, access points, and remote service providers.

[0084] In the embodiment of Fig. 11 is a wireless mesh network 1105 present, e.g. in a building with several wireless devices 1110 0-n As shown, the wireless devices 1110, which can include IoT devices with dual-mode PAs, are paired with an access point 1130, which in turn communicates with a remote service provider 1160 via a wide area network 1150, e.g., the internet. It should be noted that in the embodiment of Fig. 11 Although a general representation is shown, many variations and alternatives are possible.

[0085] Although the present invention has been described with reference to a limited number of embodiments, those skilled in the art will recognize numerous modifications and variations thereof. It is intended that the appended claims cover all such modifications and variations that are within the scope and purpose of the present invention.

Claims

[1] Device comprising: a dual-mode power amplifier to amplify a first radio frequency (RF) signal of a first wireless protocol according to a linear operating mode and to amplify a second RF signal of a second wireless protocol according to a non-linear operating mode; at least one digital feedback circuit coupled to the dual-mode power amplifier, which provides at least one digital feedback circuit with feedback information; and a control system to control the power level of the dual-mode power amplifier, at least partially, based on feedback information. [2] Device according to claim 1, wherein the at least one digital feedback circuit comprises an envelope detector, comprising: a comparator to compare a measure of the first RF signal with a reference value and output a digital value based on the comparison; and a digital filter coupled to the comparator, which outputs the feedback information, at least partially based on the digital value, which includes a root mean square of the first RF signal. [3] Device according to claim 1, wherein the at least one digital feedback circuit comprises a current detector, comprising: a comparator to compare an initial value, representative of a current output from a voltage regulator coupled to the dual-mode power amplifier, with a reference value and to output a digital value based on the comparison; and a digital filter coupled to the comparator, which outputs feedback information, at least partially based on the digital value, that includes the current output of the voltage regulator. [4] Device according to claim 1, wherein the controller determines a correction value for the dual-mode power amplifier at least partially based on the feedback information obtained during a preamble section of a first packet and at least one stored calibration value. [5] Device according to claim 4, wherein the control: a gain change is calculated based on a voltage value of the feedback information and an initial calibration value from a non-volatile memory; a difference is calculated between a current value of the feedback information and a second calibration value from the non-volatile memory; a load amplification is determined at least partially based on the difference; and the correction value is determined based on the change in gain and the load gain. [6] Device according to claim 1, wherein the dual-mode power amplifier comprises a plurality of disks, wherein a section of the plurality of disks is to be reused in the linear operating mode and in the non-linear operating mode. [7] Device according to claim 6, wherein the control system updates a number of active disks of the majority of disks based on the feedback information. [8] Device according to claim 1, further comprising a programmable impedance circuit coupled to an output of the dual-mode power amplifier, wherein the programmable impedance circuit is to be controlled based on the power level of the dual-mode power amplifier. [9] Device according to claim 8, wherein the programmable impedance circuit comprises: a first inductor coupled to the output of the dual-mode power amplifier; a second inductor that is coupled to the first inductor unit at a first node; a first switch coupled to the first node to selectively bypass the first inductor; and a second switch coupled to the second inductor to selectively bypass the second inductor. [10] Device according to claim 1, further comprising: a first driver to drive the first RF signal to the dual-mode power amplifier; and a second driver to drive the second RF signal to the dual-mode power amplifier. [11] Device according to claim 10, further comprising a switch arrangement coupled between the first driver and the dual-mode power amplifier to couple the first driver to the dual-mode power amplifier in linear operating mode and to decouple the first driver from the dual-mode power amplifier in non-linear operating mode. [12] Device according to claim 11, further comprising a balun coupled to the switch arrangement, wherein the first driver is to output a differential signal and the balun is to convert the differential signal into a single-ended signal comprising the first RF signal. [13] Device according to claim 11, wherein the switch arrangement comprises a plurality of switching units, each of the plurality of switching units comprising: at least one first switch to couple at least one first section of the first RF signal to the dual-mode power amplifier for a first period of time; and at least a second switch to couple at least the first section of the first RF signal to the dual-mode power amplifier for a second period of time. [14] Procedure encompassing: Amplification of an initial radio frequency (RF) signal of an initial wireless protocol in a power amplifier of a wireless device operating in a linear mode; Amplifying a second RF signal of a second wireless protocol in the power amplifier operating in a non-linear mode; and Control of a programmable impedance circuit coupled to an output of the power amplifier, at least partially based on a power level of the power amplifier. [15] The method of claim 14, further comprising: digital measurement of a voltage at the output of the power amplifier via a first digital detector during a preamble section of a first packet; and Digital measurement of the current output of a voltage regulator supplying the power amplifier with an operating voltage, via a second digital detector during the preamble section of the first packet. [16] The method of claim 15, further comprising: Determining a gain calibration for the power amplifier, based at least partially on the voltage, current, and one or more calibration values ​​stored in non-volatile memory; and Applying gain calibration to the power amplifier during a second package. [17] Method according to any one of claims 14 to 16, wherein the power amplifier comprises a plurality of disks and applying the gain calibration comprises updating a number of the multiple disks to be activated. [18] The method of claim 14, wherein the power amplifier comprises a plurality of disks, the method further comprising: Amplifying the second RF signal of the second wireless protocol in a first number of disks of the majority of the disks of the power amplifier, which operates in non-linear mode; and Amplifying the first RF signal of the first wireless protocol in a second number of disks of the majority of disks of the power amplifier operating in linear mode, wherein at least some of the first number of disks are included in the second number of disks. [19] The method of claim 14, further comprising: Control the programmable impedance circuit to have an initial impedance level when the first RF signal is amplified; and Control the programmable impedance circuit to have a second impedance level when the second RF signal is amplified. [20] System encompassing: an antenna for sending and receiving radio frequency (RF) signals; and a multiprotocol transceiver coupled to the antenna, comprising: a dual-mode power amplifier to amplify a first RF signal of a first wireless protocol according to a linear operating mode and to amplify a second RF signal of a second wireless protocol according to a non-linear operating mode; an impedance transformation circuit coupled to an output of the dual-mode power amplifier; at least one digital feedback detector coupled to the dual-mode power amplifier, wherein the at least one digital feedback detector provides feedback information; and a control to adjust the impedance of The impedance transformation circuit can be controlled at least partially based on the feedback information. [21] System according to claim 20, further comprising a non-volatile memory for storing compensation data, the compensation data comprising a first compensation value associated with an output voltage of the dual-mode power amplifier and a second compensation value associated with a load current of the dual-mode power amplifier. [22] System according to claim 20, wherein the controller further controls the impedance of the impedance transformation circuit based on at least one of the first compensation value or the second compensation value.

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