SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a SiC semiconductor substrate (1S) of a first conductivity type; a SiC epitaxial layer (NE) of the first conductivity type provided on the SiC semiconductor substrate (1S) and having an impurity concentration lower than that of the SiC semiconductor substrate (1S); a first semiconductor layer (L1) provided as a part of the SiC epitaxial layer (NE) and including first semiconductor pillars (PC) of the first conductivity type and second semiconductor pillars (NC) of a second conductivity type extending in a first direction and alternately and repeatedly arranged in a main surface of the SiC semiconductor substrate (1S); a second semiconductor layer (L2) of the first conductivity type, which is a different layer than the first semiconductor layer (L1) in the SiC epitaxial layer (NE) and is arranged between the SiC semiconductor substrate (1S) and the first semiconductor layer (L1); a device active region (AC) provided on a main surface of the first semiconductor layer (L1); a termination region (TR) provided on the main surface of the first semiconductor layer (L1) and surrounding the active region (AC) of the device; a channel limiter region (CS) of the first conductivity type provided on the main surface of the first semiconductor layer (L1), surrounding the termination region (TR), and having an impurity concentration higher than that of the first semiconductor pillars (PC) and the SiC epitaxial layer (NE); and a plurality of first chip end portions (CEP1) parallel to a second direction intersecting the first direction, and a plurality of second chip end portions (CEP2) parallel to the first direction, wherein the first chip end portions (CEP1) and the second chip end portions (CEP2) are provided to define a four-sided semiconductor chip, wherein the first chip end portion (CEP1) has a first side surface (S) with a height of a cross section from the first semiconductor layer (L1) to a center of the second semiconductor layer (L2) and a second side surface (SS2) with a height from the center of the second semiconductor layer (L2) to a back side of the semiconductor substrate, and wherein the channel limiter region (CS) covers exposed cross sections of the first semiconductor pillars (PC) and the second semiconductor pillars (NC) at the first side surfaces, and is in contact with the first semiconductor pillars (PC) and the second semiconductor pillars (NC) at the first chip end portions (CEP1).