DYNAMIC CHIP-TO-CHIP HOT- AND POWER-GATING

Abstract

System (100, 200), encompassing: a plurality of systems-on-a-chip (SoCs) (101) located on respective chips, wherein the plurality of SoCs (101) are connected by a network (105) of which respective sections are located on different of the respective chips, and wherein the plurality of SoCs (101) and the network (105) are configured to operate as a single logical computing system; wherein the multitude of SoCs (101) are configured to exchange local performance information (130) indicating network activity taking place in their respective sections of the network (105); and where a given of the multitude of SoCs (101) is configured to: Determine that a local condition for switching the respective section of the network (105) corresponding to the given SoC (101) into a reduced power mode has been met; and Switching the respective section of the network (105) to the reduced power mode in response to determining that a global condition for the reduced power mode is met, wherein the global condition is evaluated based on current local power information (130) for the remaining plurality of SoCs (101).

Description

BACKGROUND Technical area

[0001] The embodiments described herein relate to systems-on-a-chip (SoCs) and, in particular, to parallel communication interfaces used for coupling SoCs. Description of the state of the art

[0002] Integrated circuits (ICs) of a system-on-a-chip (SoC) generally include one or more processors that serve as the central processing units (CPUs) for a system, along with various other components, such as memory controllers and peripherals. Additional components can be included on a specific SoC IC to serve as the primary processor for a given device. For example, an SoC can include any suitable combination of one or more general-purpose processors, a graphics processor, an audio processor, networking circuits (e.g., Ethernet, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe)), memory controllers, display controllers, and the like. The combination of processors and components can be interconnected via one or more networks within the SoC to enable communication.

[0003] Increasing the number of processors and / or other discrete components included on a SoC IC may be desirable for enhanced capabilities in a performance-oriented application, while a reduced set of capabilities may be acceptable for a cost-sensitive application. Increasing the number of processors and / or other components on an IC can lead to a cost increase, which is detrimental to cost-sensitive applications. Furthermore, ICs may have a physical limitation in chip size. Increasing the number of processors and / or other circuitry on an SoC may reach this physical limit before the desired performance level is achieved. Another technique for scaling SoC capabilities is to use multiple SoCs in a single design.A basic SoC can be used for a cost-sensitive application, while two or more instances of the basic SoC can be included in a performance-oriented application.

[0004] US 2016 / 0239454 A1 describes a system-on-a-chip (SoC) with a management compute unit (CUU) configured to operate the SoC in one of several modes. In a first mode, the SoC is configured to operate a network compute unit for managing network traffic. In a second mode, the SoC is configured to operate a server compute unit for providing computing services. In a third mode, the SoC is configured to operate both the network compute unit and the server compute unit simultaneously.

[0005] US 2020 / 0401205 A1 describes techniques and mechanisms for identifying a power state to be provided by an integrated circuit (IC). In one embodiment, the evaluation circuit of a system-on-chip is programmable based on several criteria, each applicable to a different power mode. Programming the evaluation circuit allows simultaneous evaluations to determine, for each different power mode, whether a detected state of the IC can support that power mode. The results of the evaluations are transmitted in parallel to a circuit that selects such a power mode based on the relative priorities of the power modes to one another.In another embodiment, the evaluation circuit comprises an arrangement of circuit cells, each of which can be configured to perform a different evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

[0006] US 2010 / 0318822 A1 describes a system-on-chip that can include initiators, targets that exchange information with the initiators, and a control module. The control module can selectively put each of the initiators and each of the targets into one of several reduced-power modes based on external instructions, and selectively wake each initiator and each target from the reduced-power mode.

[0007] US 2020 / 0192462 A1 describes a processor, a first plurality of IP circuits for performing operations; and a second plurality of integrated voltage regulators, wherein the second plurality of integrated voltage regulators is over-constrained with respect to the first plurality of IP circuits.

[0008] Providing a system or procedure that enables a reduced performance mode without causing undesirable effects on the system or procedure can be considered a technical problem. SUMMARY

[0009] The problem is solved by a system with the features of claim 1, a method with the features of claim 8, or a device with the features of claim 15. Preferred embodiments and further developments of the invention are disclosed in the dependent claims.

[0010] In one embodiment, a system comprises a plurality of systems-on-a-chip (SoCs) connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs can be configured to exchange local power information indicating network activity occurring in their respective segments of the network. A given SoC can be configured to determine that a local condition for placing the respective segment of the network corresponding to that SoC into a reduced power mode has been met. The given SoC can further be configured to place the respective segment of the network into the reduced power mode in response to the determination that a global reduced power mode condition has been met.The global condition can be assessed based on current local performance information for the remaining multitude of SoCs.

[0011] In another example, the multitude of SoCs can be configured to exchange local power information, sending their respective local power information to at least one other SoC in the multitude at a specified time interval. In yet another example, the given SoC is configured to exchange local power information, sending a request to enter reduced power mode to the remaining SoCs. The given SoC can further be configured to receive the respective local power information for each SoC from the remaining SoCs and to determine whether the received local power information satisfies the global condition.

[0012] In one example, the given SoC can be a primary SoC configured to initiate entry into reduced power mode. The remaining SoCs can be secondary SoCs configured to wait for a signal from the primary SoC to enter reduced power mode. In one embodiment, to put the respective segment of the network into reduced power mode, the given SoC can be configured to send a request to enter reduced power mode to the remaining SoCs and wait for responses from them, which will either approve or deny the request.

[0013] In another embodiment, a specific SoC among the remaining SoCs can be further configured to delay sending a response to the request in response to a determination that the respective segment of the network in that specific SoC is waiting for a transaction to complete, and to send the response in response to a determination that the transaction is complete. The response can include an authorization to enter reduced power mode.

[0014] In another embodiment, a specific SoC among the remaining SoCs is further configured to send a response to a request in response to a determination that the respective segment of the network in that specific SoC is waiting for the completion of a transaction. The response may include a denial of entry into reduced power mode. The given SoC may also be configured to cancel the request to enter reduced power mode upon receiving the denial response. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following detailed description refers to the accompanying drawings, which will now be briefly described. Fig. Figure 1 illustrates a block diagram of an embodiment of a system that includes a plurality of systems-on-chips coupled via a shared network. Fig. Figure 2 shows a block diagram of an embodiment of another system that includes a plurality of systems-on-chips (SoCs) coupled via two shared networks. Fig. Figure 3 shows a block diagram of an embodiment of a SoC that is used in the systems of Fig. 1 and Fig. 2 can be used. Fig. Figure 4 illustrates a representation of tasks performed by two SoCs coupled through a shared network in a system to put a network circuit into a reduced power mode. Fig. Figure 5 shows another representation of tasks performed by two SoCs coupled through a shared network in a system to put a network circuit into a reduced power mode. Fig. Figure 6 represents tasks performed by two SoCs coupled through a shared network in a system to wake up a network circuit that is in a reduced power mode. Fig. Figure 7 shows a flowchart of an embodiment of a method for putting a network circuit into a reduced power mode. Fig. Figure 8 shows a flowchart of an embodiment of a method for waking up a network circuit that is in a reduced power mode. Fig. Figure 9 presents various embodiments of systems that include coupled integrated circuits. Fig. Figure 10 shows a block diagram of an exemplary computer-readable medium according to some embodiments.

[0016] While embodiments described in this disclosure may be subject to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. It is understood, however, that the drawings and the detailed description thereto are not intended to limit the embodiments of the disclosed particular form, but rather that, on the contrary, they are intended to cover all modifications, equivalents, and alternatives that are within the nature and scope of protection of the accompanying patent claims. DETAILED DESCRIPTION OF EXECUTION FORMS

[0017] As described above, a system-on-a-chip (SoC) design may include one or more network circuits to enable communication between a variety of agents. As used herein, an "agent" refers to a functional circuit capable of initiating or being a target for a transaction on a network. Accordingly, general-purpose processors, graphics processing units (GPUs), memory controllers, and other similar circuits may be referred to as agents. An exchange of data between two agents over one of the network circuits is referred to herein as a "transaction." To manage the variety of data transactions between the different agents, a variety of network circuits may be implemented.

[0018] Using multiple instances of a SoC can present several challenges. For example, to reduce the latency associated with communication between SoCs, a network interface between them may include a large number of pins, allowing a large number of bits to be exchanged in parallel between two or more SoCs. An on-chip network for a multi-core SoC can utilize one or more communication buses with hundreds, or even thousands or more, of parallel signals. To connect two or more of such SoCs, a network interface may be required that provides access to a significant portion of the communication buses, potentially requiring hundreds of pins connected across the two or more chips.Such a network between SoCs can allow internal communication buses on two or more instances of an SoC to function as a single, coherent communication fabric, enabling transactions to be exchanged between agents on different chips in a similar way to how transactions are exchanged between two agents on the same chip. From a functional perspective, the multiple instances of SoCs can operate as a single integrated circuit.

[0019] To achieve, or even approximate, the internal on-chip communication frequency of the communication buses, the timing characteristics of the large number of pins in the network circuits between SoCs may utilize high-speed circuitry that may not be energy-efficient when inactive. Accordingly, it may be desirable to put the network circuits between SoCs into a reduced-power mode when inactive. In a reduced-power mode, the power consumption of a given network circuit is lower than when operating in a normal mode. For example, power to one or more power nodes in the given network circuit can be reduced or turned off. Similarly, the frequency of a clock signal can be reduced, or the clock signal can be driven by one or more clock nodes in the given network circuit.In other embodiments, a reduced power mode can correspond to performing a shutdown of an active network circuit, so that the shut-down network circuit does not respond to network traffic between other network circuits that may remain active on a common interface.

[0020] Along with reduced performance, the capabilities of a given network circuitry in reduced-power mode may also be lower than when operating in full-service mode. Accordingly, in a multi-SoC system, if a particular SoC autonomously puts its network circuitry into a reduced-power state, a transaction sent from another SoC to an agent on that SoC may be missed or blocked while waiting for the first SoC to return its network circuitry to full-service mode. An uncoordinated process for putting network circuitry into reduced-power modes can therefore result in an unacceptable number of missed or blocked transactions, thus reducing the effectiveness of the multi-SoC system.

[0021] To address this problem, techniques are considered that involve the exchange of local power information, indicating network activity occurring in each segment of a multi-SoC network, by multiple SoCs comprising respective sections of the network. A given SoC can then determine that a local condition for putting its respective network segment into a reduced power mode has been met. In response, the given SoC can then determine whether a global condition for the reduced power mode has been met. Such a global condition can be evaluated based on current local power information for the other SoCs in the multi-SoC system. After determining that the global condition has been met, the respective network segment can then be put into the reduced power mode.

[0022] Fig. Figure 1 illustrates a block diagram of an embodiment of a logic computing system that includes four SoCs coupled by a shared network. As illustrated, the system includes 100 SoCs 101a-101d (collectively, SoCs 101). Each SoC 101 includes a respective power management circuit 120a-120d (collectively, power management circuits 120). The SoCs 101 also include respective sections of the network 105, including respective network circuits 110a-110d (collectively, network circuits 110). Using network 105, the SoCs 101 can exchange their respective power information (power info) 130a-130d (collectively, power information 130).

[0023] As shown, the SoCs 101 are located on individual chips and are connected via the network 105, with sections of the network located on different chips, including the respective network circuits 110. The SoCs 101 and the network 105 are configured to operate as a single logical computing system, for example, as the main application processor in a computing device such as a laptop or desktop computer, a tablet computer, a smartphone, and the like.As used herein, a “logical computing system” refers to a computing system that includes one or more processor circuits configured to execute program instructions contained in a software program that causes the one or more processor circuits to receive, process, and generate data using one or more memory circuits and / or other functional circuits accessed via a common bus protocol. A logical computing system can be implemented using multiple system-on-a-chips (SoCs), which may be arranged on a single integrated circuit (IC) or across two or more ICs. In the multi-IC implementation, as shown in System 100, a common bus protocol across the multiple ICs is used to allow software programs to access agents on the different ICs without knowing the physical location of the agents.Each SoC 101 includes one or more agents (not shown), such as processor cores, graphics processors, storage systems, wired and / or wireless network interfaces, and the like. Using the network 105, agents on the SoC 101a, for example, can communicate with agents on the other SoCs 101 in the same way they communicate with other agents within the SoC 101.

[0024] The SoCs 101 are, as illustrated, configured to exchange respective performance information 130, which indicates the network activity taking place in their respective sections of the network 105. For example, the performance management circuit 120b on the SoC 101b manages performance information 130, which indicates the activity on a network circuit 110b. In some embodiments, the performance information 130b is an indication of network activity taking place in the network circuit 110b, which includes, for example, one or more information elements such as the number of consecutive clock cycles in which the network circuit 130b was inactive, the number of pending transactions in one or more queues contained in the network circuit 110b, the destinations of pending transactions in the queues, and the like.In other embodiments, additional information, such as a current power mode status, can be included in the power information 130b. In some embodiments, the power information 130 can simply include an indication from a corresponding SoC 101 that local traffic on the respective network circuit 110 meets the conditions for shutting down the network 105, without providing any additional information about the network traffic. The power management circuit 120b can update the power information 130b when changes occur and / or at specific intervals, including, for example, with each cycle of a clock signal associated with the network circuit 110b. In various embodiments, the SoCs 101 can exchange their respective power information 130 at a specific time interval or in response to a specific event, such as a request from another SoC 101.

[0025] As illustrated, the SoC 101b is configured to determine when a local condition is met for putting the network circuit 110b into a reduced power mode. This local condition might be, for example, that the network circuit 110b remains idle for a successive number of clock cycles. As used here, an "idle" state of a network circuit refers to the network circuit having no transaction to process. Transactions to be sent and / or received by the network circuit can be stored in one or more queues. A transaction can remain in the queue until resources are available to process it. For example, a queued transaction might remain in the queue until a destination agent has the necessary bandwidth to receive the transaction.A network circuit with queued transactions that are not actively being processed cannot be considered inactive, as it has a transaction to process as soon as resources become available. If no transactions are queued or being processed, the network circuit can be considered inactive. Each clock cycle in which the network circuit is in a resting state is called an "idle cycle."

[0026] A given network circuit 110, as shown, enables the respective SoC 101 to communicate with the other three SoCs 101 via the network 105. In some embodiments, a given network circuit 110 may be in a sleep state while two or more agents within the respective SoC 101 exchange transactions. The network circuits 110 are configured to provide a bridge between on-chip communication buses (not shown) and the network 105, thus enabling, for example, an agent on SoC 101a to send a transaction to an agent on SoC 101d using similar instructions as for sending a transaction to another agent on SoC 101a.

[0027] After the SoC 101b has determined that the power information 130b satisfies the local condition, the SoC 101b is further configured to put the network circuit 110b into reduced power mode in response to the determination that a global reduced power mode condition is met. As mentioned, the SoCs 101 exchange their respective power information 130 so that each power management circuit 120 can evaluate global power utilization conditions over the network 105. In some embodiments, the plurality of SoCs 101 is configured to exchange power information 130, sending their respective power information 130 to other SoCs 101 at a specified time interval.In other embodiments, the SoC 101b can send a request to enter reduced power mode to the SoCs 101a, 101c, and 101d and, in turn, receive the respective power information 130 for the corresponding SoC from the SoCs 101a, 101c, and 101d. The SoC 101b is further configured to determine that the received power information 130a, 130c, and 130d satisfies the global condition.

[0028] The global condition is evaluated, as shown, based on current power information 130 for the remaining SoCs 101a, 101c, and 101d. For example, the power information 130 received from other SoCs 101 may include targets for queued transactions. Examples of global conditions for SoC 101b include that network circuits 110a, 110c, and 110d have no transaction queued with a target on SoC 101b. In some embodiments, the shared power information 130 includes current idle cycle counts. The power management circuit 120b can place network circuit 110b into reduced power mode only if all four network circuits have been inactive for a threshold time period.

[0029] In some embodiments, a given SoC 101 is designated as the primary SoC, configured to initiate a determination of whether network traffic, as indicated by the power information 130a-130d, meets the conditions for terminating all network traffic, rather than allowing any of the SoCs 101 to initiate a request to enter reduced power mode. The remaining SoCs 101 are secondary SoCs configured to wait for a request from the primary SoC to provide their respective power information 130. Each SoC 101 can provide an indication of whether the conditions are met to allow one or more of the network circuits 110 to enter reduced power mode. If all SoCs 101 agree, any SoC 101 can place its respective network circuit 110 into reduced power mode.

[0030] For example, SoC 101a can be the designated primary SoC, while SoCs 101b-101d are secondary SoCs. In such an example, the exchange of power information 130 involves SoCs 101b-101d sending their respective power information 130b-130d to SoC 101a, either based on the elapsed time interval or in response to a request from SoC 101a. The power management circuit 120a receives the power information 130b-130d and, in combination with the local power information 130a, determines whether conditions are met to shut down the network 105 and allow one or more SoCs 101 to enter reduced power mode.In some embodiments, the power information 130a-130d is shared by all SoCs 101, enabling each SoC 101 to refuse to shut down the network 105, in which case no network circuit 110 can be put into reduced power mode.

[0031] In some embodiments, the primary SoC 101a can determine whether global conditions exist for all SoCs 101 to put their respective network circuits 110 into low-power mode. For example, the power information 130 might indicate that no transactions are queued in any of the network circuits 110 and no transactions are pending completion. The power management circuit 120a can then send a notification to the power management circuits 120b-120d that network 105 is being shut down and that they can put their respective network circuits 110b-110d into reduced-power mode when their respective local conditions are met. In some cases, a specific power management circuit 120b-120d can respond with a veto. Such a veto can cancel the shutdown of network 105.

[0032] In other embodiments, the primary SoC 101a determines individually for each of the SoCs 101 whether local and global conditions exist for one or more SoCs 101 to put their respective network circuits 110 into low-power mode. For example, based on the power information 130, the power management circuit 120a may determine that network circuit 110a and network circuit 110d meet the conditions for entering reduced power mode, while network circuits 110b and 110c have active and / or queued transactions for exchange between SoC 101b and 101c and therefore must remain active. In such an embodiment, the SoC 101a may delegate the primary setting to one of the SoCs 101b or 101c, so that a SoC 101 with an active network circuit 110 is the designated primary SoC 101.In other embodiments, the SoC 101a can maintain the primary setting despite the network circuit 110a entering reduced power mode.

[0033] Such a power management system for network circuits can enable a multi-SoC system, such as the System 100, to reduce the power consumption of the network circuits while maintaining the proper operation of a distributed network system. The disclosed power management techniques can allow the distributed network system to support software running on any one of the SoCs to address agents on other SoCs without being aware that the other agent resides on a different SoC chip.

[0034] It is pointed out that the system in question is 100, as in Fig. Figure 1 illustrates that this is merely an example. The illustration of Fig. Figure 1 has been simplified to highlight features relevant to this disclosure. Different embodiments may include different configurations of circuit elements. For example, System 100 is shown with four SoCs. In other embodiments, any suitable number of SoCs may be included. For clarity, each SoC is illustrated with only its respective network circuit and power management circuit. In other embodiments, SoCs may include any suitable number of additional circuits, including, for example, one or more processor cores, graphics processors, security processors, memory circuits and / or interfaces, image and / or audio acquisition circuits, and the like.

[0035] Fig. Figure 1 represents a system with a signaling network distributed across multiple SoCs. Other embodiments may include different numbers of networks, and the networks may have more than one topology. An example of a system with two networks with different topologies is shown in Figure 1. Fig. 2 shown.

[0036] Transition to Fig. Figure 2, a block diagram of an embodiment of a system that includes four SoCs coupled by two shared networks. As illustrated, System 100 includes the SoCs 101, each of which, as previously described, includes one of the power management circuits 120 and one of the network circuits 110. The network circuits 110 support two networks in System 200, Network 105 and Network 205, each network having a different topology.

[0037] As shown, networks 105 and 205 enable communication between agents on different SoCs 101. Each network can be assigned to a specific transaction type. For example, network 105 can be assigned to memory transactions where at least one of the source and / or destination agents includes a memory circuit, allowing agents on different SoCs 101 to access memory circuits on other SoCs 101. Network 205 can be assigned to processor cores on each SoC 101, allowing one or more processor cores on each SoC 101 to share information with cores on the other SoCs 101.

[0038] To execute their respective transaction types, networks 105 and 205 are configured in different topologies: a mesh topology and a ring topology, respectively. Network 105 uses a mesh topology in which each network node (e.g., individual circuits within each of the network circuits 110) can be connected to one or more other network nodes. Generally, a mesh network does not have a fixed structure. In network 105, for example, SoC 101a can be directly connected to each of SoCs 101b-101d, while SoCs 101b and 101d also share a direct connection. SoC 101c can only be directly connected to SoC 101a. Accordingly, a transaction on network 105 to / from SoC 101c can always pass through network circuit 110a of SoC 101a.

[0039] Network 205, on the other hand, is a ring network in which each network node is directly coupled to two other network nodes. As shown, Network 205 directly couples SoC 101a to SoCs 101b and 101c, SoC 101b to SoCs 101a and 101d, SoC 101d to SoCs 101b and 101c, and SoC 101c to SoCs 101a and 101d. In a ring network, transactions are sent "around the ring" until they reach their destination. In some ring networks, transactions can be sent in a single direction. If network 205, for example, has a clockwise direction, then a transaction from SoC 101a to SoC 101c would pass through SoC 101b and then SoC 101d before reaching SoC 101c. However, a transaction from SoC 101c to 101a would be direct, bypassing SoCs 101b and 101d.In other embodiments, the network 205 can be bidirectional, enabling, for example, the SoCs 101a and 101c to exchange transactions directly.

[0040] System designers can choose network topologies for various reasons. A ring network can be used with processor cores to create a more predictable network structure, while a mesh network allows for faster, more direct transaction transmission under low network traffic, but can also result in longer paths between network nodes under high network traffic. An additional factor in selecting a network topology among the SoCs 101 involves choosing the topology for a corresponding network within the SoCs. Network 105, as illustrated, is an extension of a memory network within each of the SoCs 101.If the SoCs 101 use a mesh network for internal memory transactions, using a mesh network to form the network 105 allows a processor core coupled to the network circuit 110a to access memory circuits coupled to the network circuits 110b-110d by using the same network protocol as is used to access memory circuits within the SoC 101a.

[0041] Several techniques can be used to put a given network circuit 110 into reduced power mode. In some embodiments, putting a given network circuit 110 into reduced power mode blocks communication on both network 105 and network 205. In other embodiments, the network circuits 110 can be partitioned such that sub-circuits for either network 105 or network 205 can be put into reduced power mode independently, thus allowing one network to remain operational while the other enters reduced power mode.

[0042] Furthermore, the network topology can determine whether a single network circuit 110 can enter reduced power mode individually, or whether all network circuits 110 in the system 200 must meet certain conditions to enter reduced power mode simultaneously. For example, a mesh network, such as network 105, may allow a single network circuit 110 (e.g., network circuit 110c) to enter reduced power mode as long as network circuits 110a, 110b, and 110d have active network paths between them, enabling communication between any combination of the three active network circuits. In contrast, a ring network (such as network 205) may block communication between one or more active network circuits if a given network circuit 110 enters reduced power mode. For example, if network 205 is unidirectional (e.g.,(Transmission only in a clockwise direction) then, if a single network circuit, such as network circuit 110b, enters the reduced power state, network circuit 110c cannot send transactions to network circuit 110d, and network circuit 110a cannot send transactions to network circuit 110d or 110c. In such an embodiment, all four network circuits 110 would have to enter the reduced power mode simultaneously.

[0043] Accordingly, to put the network circuit 110a into reduced power mode, the SoC 101a is configured to send a request 240 to enter reduced power mode to the SoCs 101b-101d. The SoC 101a is further configured to wait for respective responses 245b-245d from the SoCs 101b-101d, with the respective responses 245b-245d either approving (245c) or denying (245b and 245d) the request 240. If requirement 240 is a requirement to put a section of network circuit 110a, which supports ring network 205, into reduced power mode, or if network circuits 110 are not partitioned to support networks 105 and 205 independently, then network circuit 110a may only enter reduced power mode if global conditions for network circuits 110b-110d are also met.As shown, a transaction 235 between network circuits 110b and 110d is either active or queued to be processed using network 205. Therefore, network circuits 110b and 110d must remain active until transaction 235 completes or, in some embodiments, is otherwise terminated. If network 205 is a unidirectional ring network, as described above, network circuit 110d requires network circuit 110a to remain active in order to send its portion of transaction 235 to network circuit 110b. Accordingly, SoCs 101b and 101d can send responses 245b and 245d, respectively, to SoC 101a, denying the request 240 to enter reduced power mode.In other embodiments, SoC 101b and 101d can delay a response to request 240 until transaction 235 is completed / finished, and can send approval responses instead of denials if local conditions are met.

[0044] Accordingly, power modes can be managed in a system of SoCs coupled by multiple networks using the disclosed techniques. The disclosed techniques make it possible to put some or all sections of the networks into reduced power modes when certain conditions are met, thereby reducing the system's power consumption.

[0045] It should be noted that the embodiment of Fig. Figure 2 is an example. Other embodiments may include a different combination of elements. For example, a different number of SoCs and / or networks may be included. Although ring and mesh networks are illustrated, other types of known network topologies may also be included, such as star and / or tree topologies.

[0046] In the description of Fig. 1 and Fig. Figure 2 shows systems with multiple SoCs coupled via one or more shared networks. The SoCs include individual power management circuits that monitor network activity and can initiate requests to put network circuits into reduced power modes. Such power management circuits can be implemented in various ways. A more detailed example of an SoC with a power management circuit is shown in Figure 2. Fig. 3 shown.

[0047] With reference to Fig. Figure 3 shows a SoC used in multi-SoC systems. As illustrated, the SoC 101 can be used in any one or more SoCs 101 systems. Fig. 1 and Fig. 2. The SoC 101 includes the network circuit 110 and power management circuit 120 described above. The SoC 101 further includes a plurality of function circuits 370a-370c (collectively 370) and one or more communication buses 360, which are used to implement a network within the SoC 101. The network circuit 110 includes an interface circuit 310. The power management circuit 120 includes a timer circuit 320, which generates the timing control value 325, as well as several status and control registers 330.

[0048] As shown, network circuit 110 is configured to form a section of network 105 when connected to other compatible network circuits, e.g., network circuits 110b-110d in Fig. 1 and Fig. 2, is coupled. The network circuit 110 is further configured to exchange a variety of transactions with the other compatible network circuits. The network circuit 110 includes an interface circuit 310, which is configured to drive and receive various signals associated with network 105. In some embodiments, multiple instances of the interface circuit 310 may be included to connect the SoC 101 to several different networks, such as networks 105 and 205 in Fig. 2, to couple.

[0049] The network circuit 110 bridges the communication between some of the function circuits 370 and function circuits enclosed in other SoCs coupled via the network 105. The communication buses 360 can combine to form a section of the network 105 within the SoC 101. The function circuits 370 can act as agents for procuring and receiving transactions over the network 105. Accordingly, a function circuit 370a, for example, can be configured to send a transaction to a function circuit 370b using the same network protocol as is used to send a transaction to a function circuit on another SoC coupled via the network 105.Such a configuration can enable software running on the SoC 101 to address the function circuits 370 as well as the function circuits on the other SoCs without knowledge of the specific SoC on which a given function circuit is located.

[0050] As illustrated, the power management circuit 120 is configured to track local power information 130 associated with the network circuit 110 and, using the power information 130, determine whether a local condition for entering reduced power mode has been met. For example, the power information 130 might include tracking a number of consecutive cycles during which the network circuit 110 was inactive. The timer circuit 320 is configured to increment (or, in other embodiments, decrement) the time control value 325 based on, for example, a network clock signal 365. The network clock signal 365 can be used by the network circuit 110 to synchronize transmissions of transactions on the network 105.When the time control value 325 reaches a certain value, the power management circuit 120 can compare the power information 130 with a threshold value 335. If a value in the power information 130 meets the threshold value 335 (e.g., a quiescent cycle count in the power information 130 reaches or exceeds the threshold value 335), the local condition for the network circuit 110 to enter reduced power mode can be met.

[0051] In some embodiments, the power management circuit 120 is further configured to receive other local power information associated with some of the other compatible network circuits. In some embodiments, all power management circuits on all SoCs coupled to the network 105 can exchange their respective power information with each other on a periodic basis or in response to a request from a specific SoC. As disclosed above, in some embodiments, a specific SoC of the network 105 can be designated as the primary SoC, while the remaining SoCs operate in a secondary function. In such an embodiment, the primary power management circuit 120 of the primary SoC 101 is the one power management circuit that can initiate the entry into a reduced power mode by one of the network circuits 110 of the network 105.For example, SoC 101 can be designated as the primary SoC in network 105 by setting primary enable 333 to a specific value. After determining that the local condition has been met, the power management circuit 120, operating in the primary function, can use recently received values ​​of the power information 130 from the other SoCs or request current values ​​of the power information 130 from the other SoCs. The power management circuit 120 can then determine whether network circuit 110 and / or other network circuits in network 105 can be put into reduced power mode. In various embodiments, the idle cycle counts from the other network circuits can be compared to the same threshold 335, or individual thresholds can be used for the other idle cycle counts.In some embodiments, power information from the other SoCs can include different information from the local power information 130. For example, power management circuits on the other SoCs can perform respective determinations when their local conditions are met, and the received power information includes details for each of the other SoCs, regardless of whether their local conditions are met.

[0052] In some embodiments where SoC 101 is the designated primary SoC, the power management circuit 120 is further configured to receive a request from one of the other compatible network circuits to enter reduced power mode. Using the other local power information received, the power management circuit 120 is configured to determine whether to approve or deny the request. For example, the network circuit for a particular SoC may meet local conditions for entering reduced power mode and, in response, send a request to SoC 101 for approval to put that particular network circuit into reduced power mode.Upon receiving the request from the specified SoC, the power management circuit 120, in response to a determination that the other local power information satisfies a global condition for entering reduced power mode, sends a response 145 to the specified SoC, causing the network circuit of the specified SoC to enter reduced power mode. In some embodiments, the power management circuit 120 may further determine that the network circuit 110 can be placed in reduced power mode if no additional responses are to be sent to other SoCs in the network 105.

[0053] In embodiments where SoC 101 is designated as a secondary SoC (e.g., the primary enable 333 is set to a different value to indicate a secondary SoC designation), to determine that the other local power information satisfies a global condition for entering reduced power mode, the power management circuit 120 is configured to send the reduced power mode entry request 240 to a specific of the other compatible network circuits via the network circuit 110. For example, the power management circuit 120 first determines that the local conditions are met. Then, the power management circuit 120 sends the reduced power mode entry request 240 to the designated primary SoC.The power management circuit 120 is further configured to wait for a response from the specified compatible network circuit (e.g., the primary SoC's network circuit), with the response approving or denying the request.

[0054] To put the network circuit 110 into reduced power mode, the power management circuit 120 can reduce or switch off the voltage of one or more power signals to the network circuit 110. Additionally or instead, the power management circuit 120 can reduce the frequency of the network clock signal 365 or drive the network clock signal 365 from the network circuit 110.

[0055] After network circuit 110 enters reduced power mode, regardless of whether SoC 101 is designated as the primary or secondary SoC, the power management circuit 120 is further configured to cause network circuit 110 to exit reduced power mode in response to receiving a signal indicating that a specific transaction should be sent via network circuit 110 to one of the other compatible network circuits. After network circuit 110 wakes up from reduced power mode, the power management circuit 120 is configured to cause network circuit 110 to send a wake-up signal 350 to the other compatible network circuits. In some embodiments, the wake-up signal 350 is an asynchronous signal that does not rely on the network clock signal 365 to be detected by the other compatible network circuits.

[0056] Similarly, if network circuit 110 is in reduced power mode and a wake-up signal is received from one of the other network circuits of network 105, the power management circuit 120 can detect the reception of the wake-up signal while the network clock signal 365 is being driven by network circuit 110. For example, the wake-up signal could be a transition from a logic low voltage to a logic high voltage or vice versa. The transition at a specific pin of interface circuit 310 can be detected by the power management circuit 120, enabling the power management circuit 120 to reset power signals, clock signals, and / or any other states of network circuit 110 back to an operating mode.Once network circuit 110 is in operating mode, an acknowledgment 355 can be sent to the other network circuits on network 105.

[0057] It is noted that the SoC of Fig. Figure 3 serves only to illustrate disclosed concepts. In other embodiments, the SoC may have different configurations. Although, for example, three functional circuits are shown, the SoC may include any suitable number of functional circuits. The number of pin connections coming from the interface circuit is just one example. In other embodiments, interface circuits may include any number of pins, including, for example, hundreds or even thousands of pins.

[0058] Fig. 1, Fig. 2 to Fig. Section 3 describes respective embodiments of a system with multiple SoCs connected by a shared network, and an embodiment of an SoC enclosed in such a system. The disclosed systems describe techniques for managing the power of network circuits used to implement the shared network. The power can be managed to these network circuits using a variety of techniques. Fig. Figures 4-6 illustrate several techniques for managing network circuit power modes used to implement a multi-SoC network.

[0059] Continuing to Fig. 4 A flowchart showing the tasks performed by SoCs 101a and 101b to enter a reduced power mode in an embodiment of System 100. Fig. Figure 1 represents the SoC. As illustrated, SoC 101a is designated as the primary SoC, while SoC 101b is a secondary SoC. The two columns indicate which SoC performs which task. Fig. 4 represents a case in which entry into reduced performance mode is requested before an active transaction is completed.

[0060] In the illustrated example, the power management circuit 120a in the SoC 101a tracks the idle time of the network circuit 110a (Task 402). While the SoC 101a tracks this idle time, the SoC 101b sends a packet to the SoC 101a via the network circuit 110b as part of a specific transaction (Task 405). The packet includes a specific request to which a response from the SoC 101a is expected (for example, a flow control message acknowledging receipt of the packet). Before the SoC 101a is able to respond, the power management circuit 120a determines that the idle time of the network circuit 110a meets a threshold time interval (Task 410). For example, a certain number of clock cycles during which the network circuit 110a has been inactive meets or exceeds a threshold number of cycles.In response to the determination, the power management circuit 120a uses the network circuit 110a to send a request to SoCs 101b, 101c, and 101d to enter reduced power mode (Task 415). SoCs 101c and 101d can respond with permissions to enter reduced power mode. However, SoC 101b delays sending a response to the request in response to a determination that network circuit 110b is waiting in SoC 101b for the completion of the specified transaction (Task 420).

[0061] At a later time, the specific transaction within SoC 101a is completed, and SoC 101a is therefore ready to respond to the received packet. The packet response is sent via network circuit 110a to network circuit 110b (Task 422). Upon receiving the packet response, SoC 101b determines that the specific transaction is complete. In response to this determination that the specific transaction is complete, SoC 101b can send a response to SoC 101a's request to enter reduced power mode (Task 425). The response includes authorization to enter reduced power mode, which allows power management circuit 120b to put network circuit 110b into reduced power mode (Task 430).Similarly, in response to receiving the approval response, the power management circuit 120b may put the network circuit 110b into reduced power mode (Task 435).

[0062] In Fig. 5 is another embodiment of the scenario of Fig. 4 shown. In a similar way to in Fig. 4. SoC 101a is designated as the primary SoC, while SoC 101b is a secondary SoC, and represents a case where entry into reduced performance mode is requested before an active transaction is completed. Fig. Figure 5 illustrates a different way of handling the request in response to determining that a transaction remains active.

[0063] As shown, SoC 101a, using power management circuit 120a, tracks the idle time of network circuit 110a (Task 502). While SoC 101a is tracking the idle time, SoC 101b sends a packet to SoC 101a via network circuit 110b as part of a specific transaction (Task 505), where the specific transaction requires a response from SoC 101a. Power management circuit 120a continues to track the idle time of network circuit 110a while the response to the specific transaction is processed. Power management circuit 120a determines that network 110a has been inactive for a threshold duration (Task 510).In response, the power management circuit 120a sends a request to enter reduced power mode to the SoCs 101b, 101c, and 101d via the network circuit 110a (Task 515) and receives responses from the SoCs 101c and 101d approving the reduced power mode. It is noted that Tasks 502-515 of . Fig. 5 the tasks 402-415 of Fig. 4 correspond.

[0064] SoC 101b determines that a response to the specific transaction is still pending (Task 520). Network circuit 110b, for example, includes a transaction queue that tracks pending and / or active transactions until completion. Accordingly, SoC 101b sends a response to the reduced power mode request in response to the determination that network circuit 110b is waiting for the specific transaction to complete, with the response including a denial of entry into reduced power mode (Task 525). SoC 101a is further configured to cancel the reduced power mode entry request upon receiving the denial response from SoC 101b (Task 535). SoC 101a can also send notifications to SoCs 101c and 101d indicating the cancellation of the reduced power mode request.

[0065] Furthermore, as shown, the SoC 101a reinitializes the idle count, and the power management circuit 120a can resume tracking a new idle time (Task 540). If the network circuit 110a remains inactive for another threshold time period, another request to enter reduced power mode can be sent. If the specified transaction is complete and the network circuit 110b also meets local conditions, the SoC 101b can respond with an approval for reduced power mode.

[0066] Fig. 4 and Fig. 5 correspond to different techniques for managing a case in which a request to enter reduced power mode is sent. Fig. Figure 6 represents a case where the SoCs 101 are in reduced power mode when a transaction is ready to be sent from one SoC 101 to another. As in Fig. 4 and Fig. 5. The SoC 101a is designated as the primary SoC, while the SoC 101b is a secondary SoC. Fig. Figure 6 illustrates a technique for waking network circuits from reduced power mode in response to determining that a transaction is ready to be sent.

[0067] The current example begins with the network circuits 110 in reduced power mode for at least the SoCs 101a and 101b in the system 100 of Fig. 1. The power management circuit 102b on the SoC 101b receives a signal that a specific transaction should be sent via network circuit 110b to network circuit 110a of the SoC 101a (Task 605). In some embodiments, a section of network circuit 110b can remain active while other sections are in reduced power mode, with the active section configured to handle transactions on an internal bus (e.g., one of the communication buses 360 in Fig. 3) to recognize and send the information to the power management circuit 120b. In other embodiments, a circuit within the internal bus or a circuit coupled to the internal bus, such as a network switch circuit, sends the information in response to the determination that the specific transaction should be sent via the network circuit 110b.

[0068] As shown, the power management circuit 120b is further configured to cause the network circuit 110b to exit reduced power mode in response to a signal (Task 610). For example, the power management circuit 120b opens one or more gates for a power signal and / or a clock signal to cause the network circuit 110b to wake up from reduced power mode. Once the network circuit 110b is in an operating mode, the power management circuit 120b causes the network circuit 110b to send a wake-up signal to the network circuit 110a and, if applicable, to the network circuits 110c and 110d (Task 615).

[0069] The wake-up signal can be implemented in various ways. For example, each of the network circuits 110 can include a dedicated pin for an asynchronous wake-up signal, which can be coupled via a common connection so that all wake-up signal pins are connected together. In reduced-power mode, a voltage level on the common connection is maintained at a first logic level (e.g., a low logic level). When a given network circuit 110 wants to wake up the other network circuits, that network circuit pushes the opposite logic level (e.g., a high logic level) on the common connection through its respective wake-up signal pin. The transition from the first to the second logic level can cause all network circuits coupled to the common connection to wake up from reduced-power mode.If a particular network circuit 110 is already awake, it can ignore the wake-up signal. In other embodiments, other methods can also be used, such as generating one or more transitions on any given pin of the network interface, such as an address or data pin.

[0070] In response to the wake-up signal being enforced by network circuit 110b, power management circuit 120a causes network circuit 110a to exit reduced power mode in a manner similar to how power management circuit 120b wakes network circuit 110b, as described above (Exercise 620). After network circuit 110a has exited reduced power mode and is in an operating mode, network circuit 110a sends an acknowledgment to network circuit 110b to indicate that network circuit 110a is now able to receive transactions (Exercise 625). The acknowledgment can be made in any suitable way. For example, the network circuits 110 can have an additional pin for enforcing acknowledgments, similar to the wake-up signal pin.In other embodiments, the awakened network circuits 110 can send a specific packet over the network 105 to indicate that they have returned to an operating mode. As shown, network circuit 110b is further configured to send the specific transaction to network circuit 110a in response to receiving the acknowledgment from network circuit 110a (Task 630).

[0071] In the illustrated embodiment, network circuit 110b waits for acknowledgment from the target network circuit 110a before sending the specific transaction. In other embodiments, network circuit 110b can wait until acknowledgments are received from all network circuits in network 105 before sending transactions. This technique prevents a late-awakening network circuit from missing a part of the transaction, which in some embodiments could lead to the late-awakening network circuit performing inappropriate or unknown operations.

[0072] It is pointed out that the techniques of Fig. 4 and Fig. 5. A designated primary SoC initiates the request to enter reduced power mode. In the Fig. Using the technique shown in section 6, any of the SoCs can initiate a wake-up from reduced power mode.

[0073] It is further noted that the techniques of Fig. Figures 4-6 are merely examples to illustrate disclosed concepts. Other embodiments may include additional tasks, and / or some tasks may be performed in a different order or simultaneously. For example, in Fig. 4. The network circuits 110a and 110b are simultaneously switched to their respective reduced power modes (Tasks 430 and 435).

[0074] The circuits and techniques described above relating to Fig. 1-6 can be used to manage power modes for network circuits enclosed in a shared network. Two procedures associated with entering and exiting the reduced power mode are described below with respect to Fig. 7 and Fig. 8 described.

[0075] Transition to Fig. Figure 7 now presents a flowchart for an embodiment of a method for putting a network circuit into a reduced power mode. Method 700 can be performed by a system that includes two or more SoCs coupled together to form a shared network, such as systems 100 and 200 in Figure 7. Fig. 1 and Fig. 2. With common reference to Fig. 1 and Fig. Procedure 700 begins at block 710.

[0076] In block 710, the procedure 700 includes the exchange of the performance information 130 for each individual SoC 101 with individual information from a multitude of SoCs 101 located on the respective chips. As in Fig. As shown in Figure 1, the SoCs 101 are connected by the network 105, which is implemented across the respective chips of the SoCs 101. As disclosed above, the network 105 can extend within each of the SoCs 101, so that software running on a particular SoC 101 uses the same network protocol to communicate both internally and with other SoCs 101. For example, software running on SoC 101a accesses functional circuits on SoCs 101b-101d in the same way as it accesses the functional circuits on SoC 101a. In some embodiments, the exchange of power information 130 involves the individual SoCs 101 sending their respective power information 130 to other SoCs 101 at a specific time interval. For example, the performance information can be sent every second or after a certain number of clock cycles (e.g., network clock signal cycles 365).In other embodiments, the exchange of power information 130 involves a first SoC 101 (e.g., one of the SoCs 101 designated as the primary SoC) sending a request for power information 130 from the remaining SoCs 101.

[0077] Procedure 700 further includes, at block 720, determining by the SoC 101a that the power information 130a satisfies a local condition for the SoC 101a to enter a reduced power mode. As illustrated, the power information 130a can include any suitable information that can be used to determine an activity level and thus specify the power consumption of the network circuit 110a. The power information 130a can be combined with a threshold value (e.g., the threshold value 335 in Fig. 3) be compared to determine that a current value of the power information 130a meets the threshold, indicating that an activity level of the network circuit 110a is low enough to put it into reduced power mode.

[0078] In block 730, procedure 700 also includes the entry into reduced power mode by SoC 101a in response to the determination that the power information 130b, 130c, and 130d satisfies a global condition for entering reduced power mode for SoCs 101b, 101c, and 101d, respectively. As shown, SoC 101a determines whether the power information 130b-130d received at block 710 satisfies a global condition for entering reduced power mode. In various embodiments, the power information 130b-130d can include the same information as power information 130a, more or less information than power information 130a, or different information than power information 130a. The global condition can have the same threshold as the local condition, or they can have different dependencies.In some embodiments, the power information 130b-130d may include an indication of whether the respective SoC 101b-101d meets its local condition for entering the reduced power mode.

[0079] In some embodiments, the exchange of power information 130 is performed after the SoC 101a determines that the local condition is met. In response to this determination, the method 700 may include the SoC 101a sending a request to enter reduced power mode to the SoCs 101b-101d. The SoC 101a may then receive the respective power information 130b-130d from the SoCs 101b-101d and determine whether the received power information 130b-130d satisfies the global condition. In such an embodiment, the power information 130b-130d received from the SoCs 101b-101d may include an approval or denial for the SoC 101a to enter reduced power mode.

[0080] In some embodiments, the method 700 may end at block 730 with the SoC 101a putting the network circuit 110a into reduced power mode in response to the determination that the other SoCs 101 also meet the conditions for entering reduced power mode. In response to the determination that the network circuit 110a cannot be put into reduced power mode, the method 700 may return to block 710 to repeat. It is noted that the method of Fig. 7 is merely an example of putting a network circuit into a reduced power mode.

[0081] With reference to Fig. Figure 8 illustrates a flowchart for an embodiment of a method for waking up a network circuit that has been placed in a reduced-power mode. Similar to the preceding Method 700, Method 800 can be performed by a system that includes a network running on a variety of SoCs, such as the Systems 100 and 200 in Fig. 1 and Fig. 2, is implemented. Procedure 800 can be performed following the execution of Procedure 700, which has resulted in some or all network circuits entering reduced power mode. With common reference to Fig. 1 and Fig. Procedure 800 begins at block 810 after block 730 of procedure 700 has been carried out and the network circuits 110 of system 100 have been put into reduced power modes.

[0082] Method 800 includes, at block 810, the determination by SoC 101d that a specific transaction to be sent has a destination within SoC 101a. As shown, the power management circuit 120d receives a signal indicating that the specific transaction is ready to be sent from SoC 101d to an agent in SoC 101a. In various embodiments, the signal can be received from the source agent, from a section of the network circuit 110d that remains active in reduced power mode, from a local network switch in SoC 101d, or the like.

[0083] In block 820, procedure 800 also includes causing the SoC 101d to exit the reduced power mode of network circuit 110d of network 105. In response to the specification of the particular transaction, the power management circuit 120d resets power and / or clock signals in network circuit 110d, thereby causing network circuit 110d to wake up from reduced power mode.

[0084] Procedure 800 further includes, at block 830, the enforcement of a wake-up signal by the SoC 101d via network 105. The network circuit 110d can send a signal to the power management circuit 1120d indicating that it has entered an operating mode. In response, the power management circuit 120d can cause the network circuit 110d to send the wake-up signal (e.g., wake-up signal 350). Fig. 3) sends to the network circuit 110a. The network circuit 110d may use any suitable method for sending the wake-up signal, including those described above in relation to Fig. 6 described procedures.

[0085] At block 840, procedure 800 further includes, in response to receiving an acknowledgment from SoC 101a, the sending of the specified transaction by SoC 101d to SoC 101a. Network circuit 110a wakes up from reduced power mode in response to the wake-up signal from network circuit 110d. After power and / or clock signals have been reset to their operating levels, network circuit 110a sends an acknowledgment to network circuit 110d indicating that network circuit 110a is operational and ready to receive transactions. In response to this acknowledgment, the specified transaction is sent from network circuit 110d to network circuit 110a.

[0086] In some embodiments, procedure 800 may terminate at block 840, and system operations may revert to procedure 700. Network circuits 110a and 110d may remain active and continue exchanging packets associated with the specific transaction until the transaction is completed.

[0087] The use of such power management techniques, as described in Procedures 700 and 800 and presented in the remainder of this disclosure, can enable power reduction techniques in a multi-SoC system with a complex distributed network fabric. Such complex network fabrics can consume a significant amount of power when activated. Power reduction techniques, as described, can reduce power consumption, thereby extending battery life and / or reducing thermal levels within the system.

[0088] It is pointed out that the procedures of Fig. 7 and Fig. Figure 8 merely provides examples of managing the power modes of network circuits in a shared network. Variations of the disclosed methods are considered, including combinations of operations from Methods 700 and 800, such as performing the methods concurrently when more than one network is used to couple the SoCs, as in Fig. 2 shown.

[0089] Fig. Figures 1-8 illustrate the devices and methods for a system that includes encoding and decoding data packets transmitted between two or more interface circuits. Each embodiment of the disclosed logic computing systems can be incorporated into one or more of a variety of computer systems, such as a desktop computer, laptop computer, smartphone, tablet, wearable device, and the like. In some embodiments, the circuits described above (e.g., the SoCs 101) can be implemented on one or more integrated circuits. A block diagram illustrating one embodiment of the computer system 900 is shown in Fig. 9 illustrates.

[0090] In some embodiments, the computer system 900 can include any disclosed embodiment of systems 100 and 200.

[0091] In the illustrated embodiment, the System 900 includes two or more instances of a SoC 906 (corresponding, for example, to any or all of the SoCs 101), which may include several types of processing circuitry, such as a central processing unit (CPU), a graphics processing unit (GPU), or something else, a communication fabric, and interfaces to storage and input / output devices. In some embodiments, one or more processors in the SoC 906 include multiple execution lanes and an instruction output queue. In various embodiments, the SoC 906 is coupled with an external memory 902, peripheral devices 904, and a power supply 908. In one embodiment, the SoC 906 can be implemented using a combination of SoCs 101 coupled together by the networks 105 and / or 205 to operate as a single SoC.

[0092] A power supply 908 is also provided, which supplies the SoC 906 with the supply voltages and one or more supply voltages to the memory 902 and / or the peripheral devices 904. In various embodiments, the power supply 908 is a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet computer, or other device). In some embodiments, more than one instance of the SoC 906 is included (and more than one external memory 902 is also included).

[0093] The 902 memory is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR, DDR2, DDR3, etc.) (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled onto a printed circuit board to form memory modules, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a system-on-chip (SoC) or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0094] The peripheral devices 904 include any desired switching logic, depending on the type of system 900. For example, in one embodiment, the peripheral devices 904 include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular communication, global positioning systems, etc. In some embodiments, the peripheral devices 904 also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripheral devices 904 include user interface devices, such as a display screen, including touchscreens or multi-touchscreens, keyboards or other input devices, microphones, speakers, etc.

[0095] As illustrated, the System 900 is shown to have applications in a wide range of fields. For example, the System 900 can be used as part of the chips, switching logic, components, etc., of a desktop computer 910, laptop computer 920, tablet computer 930, mobile phone 940, or television 950 (or a set-top box coupled with a television). Also illustrated are a smartwatch and a health monitoring device 960. In some embodiments, a smartwatch can include a variety of general-purpose computing functions. For example, the smartwatch can provide access to email, a mobile phone service, a user calendar, and so on. In various embodiments, a health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functionality.For example, a health monitoring device can monitor a user's vital signs, track a user's proximity to other users for the purpose of maintaining epidemiological distance, track contacts, facilitate communication with an emergency service in the event of a health emergency, and so on. In various embodiments, the aforementioned smartwatch may include some or no health monitoring-related functions. Other wearable devices are also considered, such as devices worn around the neck, devices worn on hats or other headwear, devices that can be implanted in the human body, glasses designed to provide an augmented and / or virtual reality experience, and so forth.

[0096] The System 900 can also be used as part of a cloud-based service (970). For example, the devices mentioned above and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, the System 900 can be used in one or more other devices within a dwelling (980) besides those mentioned above. For example, devices within the dwelling can monitor and detect conditions that require attention. For example, various devices within the dwelling (e.g., a refrigerator, a cooling system, etc.) can monitor the device's status and provide an alert to the dwelling owner (or, for example, a repair facility) should a specific event be detected.Alternatively, a thermostat can monitor the temperature in the apartment and automate settings of a heating / cooling system based on a history of responses to different conditions by the apartment owner. Also in . Fig. Figure 9 illustrates the application of System 900 to various modes of transportation. For example, System 900 can be used in the control and / or entertainment systems of airplanes, trains, buses, rental cars, passenger vehicles, watercraft, from private boats to cruise ships, (rental or owned) scooters, and so on. In various cases, System 900 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, and other functions.

[0097] It should be noted that the wide variety of potential applications for System 900 may include a variety of performance, cost, and power consumption requirements. Accordingly, a scalable solution that allows the use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be advantageous. These and many other embodiments are possible and are being considered. It should be noted that the in Fig. The devices and applications illustrated in Figure 9 are for illustrative purposes only and are not intended to be limiting. Other devices are possible and will be considered.

[0098] As in relation to Fig. Disclosed in Figure 9, the Computer System 900 can include two or more integrated circuits coupled together and enclosed within a personal computer, smartphone, tablet computer, or other type of computing device. A process for designing and manufacturing an integrated circuit using design information is described below. Fig. 10 shown.

[0099] Fig. Figure 10 is a block diagram illustrating an example of a non-transitory, computer-readable storage medium that stores circuit design information, according to some embodiments. The embodiment of Fig. 10 can be used in a process to design and manufacture integrated circuits, such as the SoCs 101, as in Fig. 1, Fig. 2 to Fig. Figure 3 shows. In the illustrated embodiment, the semiconductor manufacturing system 1020 is configured to process the design information 1015 stored on the non-transitory computer-readable storage medium 1010 and to manufacture the integrated circuit 1030 (e.g., the SoCs 101) based on the design information 1015.

[0100] The non-transitory computer-readable storage medium 1010 can comprise any of several suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 1010 can be an installation medium, such as a CD-ROM, floppy disks, or a tape device; computer system memory or random-access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as a hard disk or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 1010 can also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 can include two or more storage media, which may be located in different positions, for example,in different computer systems that are connected via a network.

[0101] The design information 1015 can be specified using any of several suitable computer languages, including, but not limited to, hardware description languages ​​such as VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 can be used by the semiconductor manufacturing system 1020 to fabricate at least one section of the integrated circuit 1030. The format of the design information 1015 can be recognized by at least one semiconductor manufacturing system, such as the semiconductor manufacturing system 1020. In some embodiments, the design information 1015 can include a netlist that specifies elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of circuits included in the integrated circuit 1030 can also be included in the design information 1015.Such cell libraries can include information specifying device- or transistor-level netlists, mask design data, characterization data, and the like of cells included in the cell library.

[0102] The integrated circuit 1030, in various embodiments, may include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, the design information 1015 may include information relating to the included macrocells. Such information may, but is not limited to, a schematic capture database, mask design data, behavioral models, and device- or transistor-level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (GDSII) or any other suitable format.

[0103] The Semiconductor Manufacturing System 1020 can include any of several suitable elements configured to manufacture integrated circuits. These can include, for example, elements for depositing semiconductor materials (e.g., onto a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), and so on. The Semiconductor Manufacturing System 1020 can also be configured to perform various tests on manufactured circuits to ensure their correct operation.

[0104] In various embodiments, the integrated circuit 1030 is configured to operate according to a circuit design specified by Design Information 1015, which may include performing any of the functionality described herein. For example, the integrated circuit 1030 may include any of the various elements shown or described herein. Furthermore, the integrated circuit 1030 may be configured to perform various functions described herein in conjunction with other components. The functionality described herein may also be provided by several interconnected integrated circuits, such as the integrated circuits 405a and 405b in Fig. 4, will be carried out.

[0105] As used herein, an expression of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured for the element to be satisfied. Rather, this expression indicates that the design information describes a circuit that, after manufacturing, will be configured to perform the specified actions or to include the specified components.

[0106] The present disclosure includes references to “embodiments” that are non-limiting implementations of the disclosed concepts. References to “embodiment,” “an embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are considered, including specific embodiments described in detail, as well as modifications or alternatives that fall within the nature or scope of the disclosure. Not all embodiments necessarily exhibit any or all of the potential advantages described herein.

[0107] Unless otherwise stated, the specific embodiments are not intended to limit the scope of protection of claims formulated on the basis of this disclosure to the disclosed forms, even if only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative and not limiting, unless otherwise stated. The application is intended to cover alternatives, modifications, and equivalents that are obvious to those skilled in the art who benefit from this disclosure.

[0108] Specific features, structures, or properties may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to encompass any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, during the further pursuit of this application (or an application claiming priority thereof), new claims may be formulated to any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined with those of the independent claims, and features of the respective independent claims may be combined in any suitable manner, not limited to the specific combinations listed in the appended claims.

[0109] While, for example, the accompanying dependent claims are formulated such that each depends on a single other claim, additional dependencies are also considered, including the following: Claim 3 (could depend on one of Claims 1-2); Claim 4 (a preceding claim); Claim 5 (Claim 4), etc. Where appropriate, consideration is also given to the possibility that claims formulated in one given type (e.g., apparatus) may point to corresponding claims of another given type (e.g., process).

[0110] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and legal interpretation. It is hereby announced that the following paragraphs, as well as definitions provided throughout this disclosure, shall be used in determining how claims formulated based on this disclosure are to be interpreted.

[0111] References to singular forms, such as "ein," "eine," and "der," "die," "das," are intended to mean "one or more," unless the context clearly indicates otherwise. A reference to "an element" in a claim therefore does not preclude additional instances of the element.

[0112] The word “can / can” is used here in a permissive sense (i.e. having the potential to be able to) and not in an obligatory sense (i.e. must / must).

[0113] The terms “comprehensive” and “inclusive” and forms thereof are open and mean “including without being limited to”.

[0114] When the term “or” is used in this revelation in reference to a list of options, it is generally understood to be used in an inclusive sense, unless the context indicates otherwise. Thus, a statement of “x or y” is equivalent to “x or y or both” and covers x but not y, y but not x, and both x and y. On the other hand, a phrase such as “either x or y, but not both” makes it clear that “or” is used in an exclusive sense.

[0115] A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities, from a single element to the total number of elements in the sentence. For the sentence [w, x, y, z], for example, these phrases cover every single element of the sentence (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "at least one of ... w, x, y, and z" thus refers to at least one element of the sentence [w, x, y, z], thereby covering all possible combinations in this list of options. This phrase must not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0116] Various “labels” may precede nouns in this disclosure. Unless the context indicates otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third,” when applied to a particular feature, do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise stated.

[0117] Within this disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed to be "configured" to perform one or more tasks or operations. This phrase—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be described as "configured to" perform a task even if the structure is not currently operating.Thus, an entity described or specified as "configured to" perform a task refers to something physical, such as a device, a circuit, a memory that stores program instructions executable to implement the task, etc. This phrase is not used here to refer to something intangible.

[0118] The hardware circuits can include any combination of switching logic, combinational logic, clocked data storage devices such as FLOPS, registers, latches, etc., finite state machines, memory such as static random-access memory or embedded dynamic random-access memory, user-designed switching logic, analog switching logic, programmable logic arrays, etc. Similarly, various units / circuits / components may, for convenience, be described in such a way as to perform a task or tasks. Such descriptions should be interpreted as containing the term "configured."

[0119] In one embodiment, hardware circuits according to this disclosure can be implemented by encoding the circuit description in a hardware description language (HDL), such as Verilog or VHDL. The HDL description can be synthesized against a library of cells designed for a given integrated circuit fabrication technology and can be modified for timing, power, and other reasons to result in a final design database that can be submitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or sections thereof can also be user-defined in a schematic editor and incorporated into the integrated circuit design along with synthesized switching logic.The integrated circuits can include transistors and may further include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and provide a connection between the transistors and circuit elements. Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuits, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic device, such as a user-programmable gate array (FPGA), and implemented within the FPGA.

[0120] The term "configured to" should not be interpreted as "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA may be "configurable to" perform that function.

[0121] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on stated factors, or on the stated factors as well as other, unspecified factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A, or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based on B. As used here, the phrase "based on" is synonymous with the phrase "based at least partially on."

[0122] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, an effect may occur solely in response to these factors, or it may occur in response to the stated factors as well as other, unspecified factors. Consider the phrase "perform A in response to B." This phrase indicates that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that performing A may also occur in response to another factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.

Claims

[1] System (100, 200), comprising: a plurality of systems-on-a-chip (SoCs) (101) located on respective chips, wherein the plurality of SoCs (101) are connected by a network (105) of which respective sections are located on different of the respective chips, and wherein the plurality of SoCs (101) and the network (105) are configured to operate as a single logical computing system; wherein the multitude of SoCs (101) are configured to exchange local performance information (130) indicating network activity taking place in their respective sections of the network (105); and where a given of the multitude of SoCs (101) is configured to: Determine that a local condition for switching the respective section of the network (105) corresponding to the given SoC (101) into a reduced power mode has been met; and Switching the respective section of the network (105) to the reduced power mode in response to determining that a global condition for the reduced power mode is met, wherein the global condition is evaluated based on current local power information (130) for the remaining plurality of SoCs (101). [2] System according to claim 1, wherein for exchanging local power information (130) the plurality of SoCs are configured to send their respective local power information (130) to at least one other SoC (101) of the plurality at a certain time interval. [3] System according to claim 1, wherein the given SoC (101) is configured to exchange local power information (130): Send, to the remaining SoCs (101), a request to enter reduced power mode; Received from the remaining SoCs (101), the respective local performance information for the corresponding SoCs and Determine whether the received local power information (130) satisfies the global condition. [4] System according to claim 1, wherein the given SoC (101) is a primary SoC configured to initiate entry into reduced power mode; and wherein the remaining SoCs (101) are secondary SoCs configured to wait for a signal from the primary SoC to enter reduced power mode. [5] System according to claim 1, wherein to put the respective section of the network (105) into the reduced power mode the given SoC (101) is configured to: Sending a request to enter reduced power mode to the remaining SoCs (101) and Waiting for responses from the remaining SoCs (101), where the responses either approve or deny the request. [6] System according to claim 5, wherein a specific SoC (101) of the remaining SoCs is further configured to: Delaying the sending of a response to the request in response to a determination that the respective section of the network (105) in the specified SoC (101) is waiting for the completion of a transaction; and Sending the response in response to a determination that the transaction is complete, with the response including an authorization to enter reduced performance mode. [7] System according to claim 5, wherein a particular SoC (101) of the remaining SoCs is further configured to send a response to the request in response to a determination that the respective section of the network (105) in the particular SoC (101) is waiting for the completion of a transaction, wherein the response includes a refusal to enter the reduced power mode; and wherein the given SoC (101) is further configured to cancel the request to enter the reduced power mode in response to receiving the refusal response. [8] Procedures, comprehensive: Exchange, through individual a plurality of systems-on-a-chip (SoCs) (101) located on respective chips, of local power information (130) for each individual SoC, wherein the plurality of SoCs are connected by a network implemented across the respective chips; Determine, by means of a given SoC (101) of the plurality of SoCs, that the local power information (130) for the given SoC satisfies a local condition for entering a reduced power mode; and In response to the determination that the local power information (130) for the remaining SoCs (101) satisfies a global condition for entering reduced power mode, the given SoC (101) enters reduced power mode. [9] Method according to claim 8, further comprising accessing, by software running on a first SoC (101) of the plurality of SoCs, functional circuits on a second SoC (101) of the plurality of SoCs in the same way as functional circuits on the first SoC (101). [10] The method of claim 8, further comprising: Determine, through another SoC of the multitude of SoCs, that a transaction to be sent has a destination within the given SoC (101); and Enforcement, through the other SoC, of ​​a wake-up signal over the network (105). [11] The method of claim 10, further comprising, in response to receiving an acknowledgment from the given SoC, the sending of the transaction by the other SoC to the given SoC. [12] Method according to claim 8, wherein the exchange of local power information includes the sending of respective local power information (130) by the individual SoCs to other SoCs of the plurality in a specific time interval. [13] Method according to claim 8, wherein the exchange of local performance information (130) includes: Sending, through the given SoC to the remaining SoCs (101) of the multitude, a request to enter reduced power mode; Received by the given SoC from the remaining SoCs (101), the respective local power information for the corresponding remaining SoCs and Determine whether the received local performance information meets the global condition. [14] Method according to claim 13, wherein the respective local power information (130) received from the remaining SoCs includes an approval or denial for the given SoC to enter the reduced power mode. [15] Institution, comprehensive: a network circuit (110) that is configured to: Forming a section of a network (105) when coupled with other compatible network circuits; and Exchanging a large number of transactions with other compatible Network circuits (110); a power management circuit (120) that is configured to: Tracking local performance information (130) associated with the network circuit (110); Determine, using the local performance information (130), that a local condition for entering a reduced power mode is met; Receiving other local power information (130) associated with some of the other compatible network circuits (110); and In response to a determination that the other local power information (130) satisfies a global condition for entering reduced power mode, cause the network circuit (110) to enter reduced power mode. [16] Device according to claim 15, wherein the power management circuit (120) is further configured to: In response to receiving a notification that a specific transaction should be sent via network circuit (110) to one of the other compatible network circuits, cause the network circuit to exit reduced power mode; and Causing the network circuit (110) to send a wake-up signal to the other compatible network circuits. [17] Device according to claim 16, wherein the network circuit (110) is further configured to send the specified transaction to one of the other compatible network circuits in response to receiving acknowledgments from the other compatible network circuits. [18] Device according to claim 15, wherein the power management circuit (120) is further configured to: Receiving a request from another of the other compatible network circuits (110) to enter reduced power mode and Using the other received local performance information, determine whether the request should be approved or denied. [19] Device according to claim 15, wherein, to determine that the other local power information (130) meets the global condition for entering the reduced power mode, the power management circuit (120) is configured to: Send, via the network circuit (110), a request to enter reduced power mode to a specific of the other compatible network circuits and Waiting for a response from the specified compatible network circuit, where the response either approves or denies the request. [20] Device according to claim 15, further comprising a processor circuit which is included on the same integrated circuit as the network circuit (110) and the power management circuit (120) and is configured to access function circuits which are coupled with the other compatible network circuits by using the same network protocol as function circuits on the integrated circuit.

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