METHOD AND DEVICE FOR POWER REDUCTION IN A MULTI-THREAD MODE
Patent Information
- Application Number
- DE602016091718
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2016-08-17
- Filing Date
- 2016-09-21
- Publication Date
- 2025-03-26
- Estimated Expiration
- 2036-09-21
AI Technical Summary
In multi-threaded computing systems, the high power consumption in Translation Lookaside Buffers (TLBs) due to frequent toggling of comparators during virtual address to physical address translation leads to increased dynamic power consumption, especially when multiple threads with independent address bits are active.
Implementing a multi-thread CAM device with dedicated comparator banks for each thread, where the input address retains its previous value when a thread is inactive, reducing the need for frequent state changes and thus minimizing power consumption.
This approach reduces thrashing of comparator states and decreases dynamic power consumption by ensuring that each thread's comparator bank only changes state when switching between pages, thereby enhancing the efficiency of virtual address translation in multi-threaded environments.